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| PIC18F46J11 Family Data Sheet 28/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology (c) 2009 Microchip Technology Inc. DS39932C Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39932C-page 2 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 28/44-Pin, Low-Power, High-Performance Microcontrollers Power Management Features with nanoWatt XLPTM for Extreme Low Power: * Deep Sleep mode: CPU off, Peripherals off, Currents Down to 13 nA and 850 nA with RTCC - Able to wake-up on external triggers, programmable WDT or RTCC alarm - Ultra Low-Power Wake-up (ULPWU) * Sleep mode: CPU off, Peripherals off, SRAM on, Fast Wake-up, Currents Down to 105 nA Typical * Idle: CPU off, Peripherals on, Currents Down to 2.3 A Typical * Run: CPU on, Peripherals on, Currents Down to 6.2 A Typical * Timer1 Oscillator/w RTCC: 1 A, 32 kHz Typical * Watchdog Timer: 2.2 A, 2V Typical Peripheral Highlights (Continued): * Four Programmable External Interrupts * Four Input Change Interrupts * Two Enhanced Capture/Compare/PWM (ECCP) modules: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart - Pulse steering control * Two Master Synchronous Serial Port (MSSP) modules featuring: - 3-wire SPI (all 4 modes) - 1024-byte SPI Direct Memory Access (DMA) channel - I2CTM Master and Slave modes * 8-Bit Parallel Master Port/Enhanced Parallel Slave Port * Two-Rail - Rail Analog Comparators with Input Multiplexing * 10-Bit, up to 13-Channel Analog-to-Digital (A/D) Converter module: - Auto-acquisition capability - Conversion available during Sleep - Self-Calibration * High/Low-Voltage Detect module * Charge Time Measurement Unit (CTMU): - Supports capacitive touch sensing for touch screens and capacitive switches - Provides a Precise Resolution Time Measurement for Both Flow Measurement and Simple Temperature Sensing * Two Enhanced USART modules: - Supports RS-485, RS-232 and LIN/J2602 - Auto-wake-up on Start bit * Auto-Baud Detect Special Microcontroller Features: * 5.5V Tolerant Inputs (digital only pins) * Low-Power, High-Speed CMOS Flash Technology * C Compiler Optimized Architecture for Re-Entrant Code * Priority Levels for Interrupts * Self-Programmable under Software Control * 8 x 8 Single-Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s * Single-Supply In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * In-Circuit Debug (ICD) with Three Breakpoints via Two Pins * Operating Voltage Range of 2.0V to 3.6V * On-Chip 2.5V Regulator * Flash Program Memory of 10,000 Erase/Write Cycles Minimum and 20-Year Data Retention Peripheral Highlights: * Peripheral Pin Select: - Allows independent I/O mapping of many peripherals - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes * Hardware Real-Time Clock and Calendar (RTCC): - Provides clock, calendar and alarm functions * High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC) Flexible Oscillator Structure: * 1% Accurate High-Precision Internal Oscillator * Two External Clock modes, up to 48 MHz (12 MIPS) * Internal 31 kHz Oscillator, Internal Oscillators Tunable at 31 kHz and 8 MHz or 48 MHz with PLL * Secondary Oscillator using Timer1 @ 32 kHz * Fail-Safe Clock Monitor: - Allows for safe shutdown if any clock stops * Two-Speed Oscillator Start-up * Programmable Reference Clock Output Generator (c) 2009 Microchip Technology Inc. DS39932C-page 3 PIC18F46J11 FAMILY Program Memory (bytes) 10-Bit A/D (ch) SRAM (bytes) Comparators ECCP/(PWM) Remappable Pins Deep Sleep MSSP EUSART SPI w/DMA I2CTM PMP/PSP Timers 8/16-Bit RTCC Y Y Y Y Y Y Y Y Y Y Y Y PIC18F/LF(1) Device CTMU Y Y Y Y Y Y Y Y Y Y Y Y Pins 28 28 28 44 44 44 28 28 28 44 44 44 PIC18F24J11 PIC18F25J11 PIC18F26J11 PIC18F44J11 PIC18F45J11 PIC18F46J11 PIC18LF24J11 PIC18LF25J11 PIC18LF26J11 PIC18LF44J11 PIC18LF45J11 PIC18LF46J11 Note 1: 16K 32K 64K 16K 32K 64K 16K 32K 64K 16K 32K 64K 3776 3776 3776 3776 3776 3776 3776 3776 3776 3776 3776 3776 16 16 16 22 22 22 16 16 16 22 22 22 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2/3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 10 10 10 13 13 13 10 10 10 13 13 13 2 2 2 2 2 2 2 2 2 2 2 2 Y Y Y Y Y Y N N N N N N N N N Y Y Y N N N Y Y Y See Section 1.3 "Details on Individual Family Devices", Section 3.6 "Deep Sleep Mode" and Section 25.3 "On-Chip Voltage Regulator" for details describing the functional differences between PIC18F and PIC18LF variants in this device family. DS39932C-page 4 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Diagrams 28-Pin SPDIP/SOIC/SSOP(1) MCLR RA0/AN0/C1INA/ULPWU/RP0 RA1/AN1/C2INA/RP1 RA2/AN2/VREF-/CVREF/C2INB RA3/AN3/VREF+/C1INB VDDCORE/VCAP(2) RA5/AN4/SS1/HLVDIN/RP2 VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI/RP11 RC1/T1OSI/RP12 RC2/AN11/CTPLS/RP13 RC3/SCK1/SCL1/RP14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 = Pins are up to 5V tolerant RB7/KBI3/PGD/RP10 RB6/KBI2/PGC/RP9 RB5/KBI1/RP8 RB4/KBI0/RP7 RB3/AN9/CTEDG2/RP6 RB2/AN8/CTEDG1/REFO/RP5 RB1/AN10/RTCC/RP4 RB0/AN12/INT0/RP3 VDD VSS RC7/RX1/DT1/RP18 RC6/TX1/CK1/RP17 RC5/SDO1/RP16 RC4/SDI1/SDA1/RP15 28-Pin QFN(1,3) RA1/AN1/C2INA/RP0 RA0/AN0/C1INA/ULPWU/RP1 MCLR RB7/KBI3/PGD/RP10 RB6/KBI2/PGC/RP9 RB5/KBI1/RP8 RB4/KBI0/RP7 PIC18F2XJ11 = Pins are up to 5V tolerant 28 27 26 25 24 23 22 RA2/AN2/VREF-/CVREF/C2INB RA3/AN3/VREF+/C1INB VDDCORE/VCAP(2) RA5/AN4/SS1/HLVDIN/RP2 VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 1 2 3 4 5 6 7 21 20 19 18 17 16 15 RB3/AN9/CTEDG2/RP6 RB2/AN8/CTEDG1/REFO/RP5 RB1/AN10/RTCC/RP4 RB0/AN12/INT0/RP3 VDD VSS RC7/RX1/DT1/RP18 PIC18F2XJ11 8 9 1011 12 13 14 Legend: RPn represents remappable pins. Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 9-13 and Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 "Peripheral Pin Select (PPS)". 2: See Section 25.3 "On-Chip Voltage Regulator" for details on how to connect the VDDCORE/VCAP pin. 3: For the QFN package, it is recommended that the bottom pad be connected to VSS. (c) 2009 Microchip Technology Inc. RC0/T1OSO/T1CKI/RP11 RC1/T1OSI/RP12 RC2/AN11/CTPLS/RP13 RC3\SCK1\SCL1\RP14 RC4/SDA1RP15 RC5/SDO1/RP16 RC6/TX1/CK1/RP17 DS39932C-page 5 PIC18F46J11 FAMILY Pin Diagrams (Continued) 44-Pin QFN(1,3) RC6/PMA5/TX1/CK1/RP17 RC5/SDO1/RP16 RC4/SDI1/SDA1\RP15 RD3/PMD3/RP20 RD2/PMD2/RP19 RD1/PMD1/SDA2 RD0/PMD0/SCL2 RC3\SCK1/SCL1/RP14 RC2/AN11/CTPLS/RP13 RC1/T1OSI/RP12 RC0/T1OSO/T1CKI/RP11 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 Legend: RPn represents remappable pins. Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 9-13 and Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 "Peripheral Pin Select (PPS)". 2: See Section 25.3 "On-Chip Voltage Regulator" for details on how to connect the VDDCORE/VCAP pin. 3: For the QFN package, it is recommended that the bottom pad be connected to VSS. RB3/AN9/CTEDG2/PMA2/RP6 NC RB4/PMA1/KBI0/RP7 RB5/PMA0/KBI1/RP8 RB6/KBI2/PGC/RP9 RB7/KBI3/PGD/RP10 MCLR RA0/AN0/C1INA/ULPWU/PMA6/RP0 RA1/AN1/C2INA/PMA7/RP1 RA2/AN2/VREF-/CVREF-/C2INB RA3/AN3/VREF+/C1INB 12 13 14 15 16 17 18 19 20 21 22 RC7/PMA4/RX1/DT1/RP18 RD4/PMD4/RP21 RD5/PMD5/RP22 RD6/PMD6/RP23 RD7/PMD7/RP24 VSS AVDD VDD RB0/AN12/INT0/RP3 RB1/AN10/PMBE/RTCC/RP4 RB2/AN8/CTEDG1/PMA3/REFO/RP5 1 2 3 4 5 6 7 8 9 10 11 PIC18F4XJ11 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS AVSS VDD AVDD RE2/AN7/PMCS RE1/AN6/PMWR RE0/AN5/PMRD RA5/AN4/SS1/HLVDIN/RP2 VDDCORE/VCAP(2) DS39932C-page 6 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Diagrams (Continued) RC6/PMA5/TX1/CK1/RP17 RC5/SDO1/RP16 RC4/SDI1/SDA1/RP15 RD3/PMD3/RP20 RD2/PMD2/RP19 RD1/PMD1/SDA2 RD0/PMD0/SCL2 RC3/SCK1/SCL1/RP14 RC2/AN11/CTPLS/RP13 RC1/T1OSI/RP12 NC 44-Pin TQFP(1) = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 Legend: RPn represents remappable pins. Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 9-13 and Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 "Peripheral Pin Select (PPS)". 2: See Section 25.3 "On-Chip Voltage Regulator" for details on how to connect the VDDCORE/VCAP pin. (c) 2009 Microchip Technology Inc. NC NC RB4/PMA1/KBI0/RP7 RB5/PMA0/KBI1/RP8 RB6/KBI2/PGC/RP9 RB7/KBI3/PGD/RP10 MCLR RA0/AN0/C1INA/ULPWU/PMA6/RP0 RA1/AN1/C2INA/PMA7/RP1 RA2/AN2/VREF-/CVREF-/C2INB RA3/AN3/VREF+/C1INB 12 13 14 15 16 17 18 19 20 21 22 RC7/PMA4/RX1/DT1/RP18 RD4/PMD4/RP21 RD5/PMD5/RP22 RD6/PMD6/RP23 RD7/PMD7/RP24 VSS VDD RB0/AN12/INT0/RP3 RB1/AN10/PMBE/RTCC/RP4 RB2/AN8/CTEDG1/PMA3/REFO/RP5 RB3/AN9/CTEDG2/PMA2/RP6 1 2 3 4 5 6 7 8 9 10 11 PIC18F4XJ11 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI/RP11 OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VDD RE2/AN7/PMCS RE1/AN6/PMWR RE0/AN5/PMRD RA5/AN4/SS1/HLVDIN/RP2 VDDCORE/VCAP(2) DS39932C-page 7 PIC18F46J11 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Oscillator Configurations ............................................................................................................................................................ 31 3.0 Low-Power Modes...................................................................................................................................................................... 41 4.0 Reset .......................................................................................................................................................................................... 57 5.0 Memory Organization ................................................................................................................................................................. 71 6.0 Flash Program Memory .............................................................................................................................................................. 97 7.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 107 8.0 Interrupts .................................................................................................................................................................................. 109 9.0 I/O Ports ................................................................................................................................................................................... 125 10.0 Parallel Master Port (PMP)....................................................................................................................................................... 165 11.0 Timer0 Module ......................................................................................................................................................................... 191 12.0 Timer1 Module ......................................................................................................................................................................... 195 13.0 Timer2 Module ......................................................................................................................................................................... 207 14.0 Timer3 Module ......................................................................................................................................................................... 209 15.0 Timer4 Module ......................................................................................................................................................................... 219 16.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 221 17.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 241 18.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 265 19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 321 20.0 10-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 345 21.0 Comparator Module.................................................................................................................................................................. 355 22.0 Comparator Voltage Reference Module ................................................................................................................................... 363 23.0 High/Low Voltage Detect (HLVD) ............................................................................................................................................. 367 24.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 373 25.0 Special Features of the CPU .................................................................................................................................................... 389 26.0 Instruction Set Summary .......................................................................................................................................................... 407 27.0 Development Support............................................................................................................................................................... 457 28.0 Electrical Characteristics .......................................................................................................................................................... 461 29.0 Packaging Information.............................................................................................................................................................. 499 Appendix A: Revision History............................................................................................................................................................. 511 Appendix B: Device Differences......................................................................................................................................................... 511 The Microchip Web Site ..................................................................................................................................................................... 525 Customer Change Notification Service .............................................................................................................................................. 525 Customer Support .............................................................................................................................................................................. 525 Reader Response .............................................................................................................................................................................. 526 Product Identification System............................................................................................................................................................. 527 DS39932C-page 8 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. (c) 2009 Microchip Technology Inc. DS39932C-page 9 PIC18F46J11 FAMILY NOTES: DS39932C-page 10 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 1.0 DEVICE OVERVIEW 1.1.2 This document contains device-specific information for the following devices: * PIC18F24J11 * PIC18F25J11 * PIC18F26J11 * PIC18F44J11 * PIC18F45J11 * PIC18F46J11 * PIC18LF24J11 * PIC18LF25J11 * PIC18LF26J11 * PIC18LF44J11 * PIC18LF45J11 * PIC18LF46J11 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F46J11 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: * Two Crystal modes using crystals or ceramic resonators. * Two External Clock modes offering the option of a divide-by-4 clock output. * An internal oscillator block, which provides an 8 MHz clock and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of six user-selectable clock frequencies, between 125 kHz to 4 MHz, for a total of eight clock frequencies. This option frees an oscillator pin for use as an additional general purpose I/O. * A Phase Lock Loop (PLL) frequency multiplier, available to the high-speed crystal, and external and internal oscillators, providing a clock speed up to 48 MHz. The internal oscillator block provides a stable reference source that gives the PIC18F46J11 family additional features for robust operation: * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset (POR), or wake-up from Sleep mode, until the primary clock source is available. 1.1 1.1.1 Core Features nanoWatt TECHNOLOGY All of the devices in the PIC18F46J11 family incorporate a range of features that can significantly reduce power consumption during operation. Key features are: * Alternate Run Modes: By clocking the controller from the Timer1 source or the internal RC oscillator, power consumption during code execution can be reduced by as much as 90%. * Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operational requirements. * On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the users to incorporate power-saving ideas into their application's software design. 1.1.3 EXPANDED MEMORY The PIC18F46J11 family provides ample room for application code, from 16 Kbytes to 64 Kbytes of code space. The Flash cells for program memory are rated to last in excess of 10000 erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 20 years. The Flash program memory is readable and writable during normal operation. The PIC18F46J11 family also provides plenty of room for dynamic application data with up to 3.8 Kbytes of data RAM. (c) 2009 Microchip Technology Inc. DS39932C-page 11 PIC18F46J11 FAMILY 1.1.4 EXTENDED INSTRUCTION SET The PIC18F46J11 family implements the optional extension to the PIC18 instruction set, adding eight new instructions and an Indexed Addressing mode. Enabled as a device configuration option, the extension has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. * 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and thus, reducing code overhead. * Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 28.0 "Electrical Characteristics" for time-out periods. 1.1.5 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. The PIC18F46J11 family is also pin compatible with other PIC18 families, such as the PIC18F4620, PIC18F4520 and PIC18F45J10. This allows a new dimension to the evolution of applications, allowing developers to select different price points within Microchip's PIC18 portfolio, while maintaining the same feature set. 1.3 Details on Individual Family Devices Devices in the PIC18F46J11 family are available in 28-pin and 44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in two ways: * Flash program memory (three sizes: 16 Kbytes for the PIC18FX4J11, 32 Kbytes for PIC18FX5J11 devices and 64 Kbytes for PIC18FX6J11) * I/O ports (three bidirectional ports on 28-pin devices, five bidirectional ports on 44-pin devices) All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. The pinouts for the PIC18F2XJ11 devices are listed in Table 1-3 and the pinouts for the PIC18F4XJ11 devices are listed in Table 1-4. The PIC18F46J11 family of devices provides an on-chip voltage regulator to supply the correct voltage levels to the core. Parts designated with an "F" part number (such as PIC18F46J11) have the voltage regulator enabled. These parts can run from 2.15V-3.6V on VDD, but should have the VDDCORE pin connected to VSS through a low-ESR capacitor. Parts designated with an "LF" part number (such as PIC18LF46J11) do not enable the voltage regulator. For "LF" parts, an external supply of 2.0V-2.7V has to be supplied to the VDDCORE pin with 2.0V-3.6V supplied to VDD (VDDCORE should never exceed VDD). For more details about the internal voltage regulator, see Section 25.3 "On-Chip Voltage Regulator". 1.2 Other Special Features * Communications: The PIC18F46J11 family incorporates a range of serial and parallel communication peripherals. This device also includes two independent Enhanced USARTs and two Master Synchronous Serial Port (MSSP) modules, capable of both Serial Peripheral Interface (SPI) and I2CTM (Master and Slave) modes of operation. The device also has a parallel port and can be configured to serve as either a Parallel Master Port (PMP) or as a Parallel Slave Port (PSP). * ECCP Modules: All devices in the family incorporate three Enhanced Capture/Compare/PWM (ECCP) modules to maximize flexibility in control applications. Up to four different time bases may be used to perform several different operations at once. Each of the ECCPs offers up to four PWM outputs, allowing for a total of eight PWMs. The ECCPs also offer many beneficial features, including polarity selection, programmable dead time, auto-shutdown and restart and Half-Bridge and Full-Bridge Output modes. DS39932C-page 12 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XJ11 (28-PIN DEVICES) Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Timers Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PMP/PSP) 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages PIC18F24J11 DC - 48 MHz 16K 8,192 3.8K PIC18F25J11 DC - 48 MHz 32K 16,384 3.8K 30 Ports A, B, C 5 2 MSSP (2), Enhanced USART (2) No 10 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 28-Pin QFN, SOIC, SSOP and SPDIP (300 mil) PIC18F26J11 DC - 48 MHz 64K 32,768 3.8K TABLE 1-2: DEVICE FEATURES FOR THE PIC18F4XJ11 (44-PIN DEVICES) Features PIC18F44J11 DC - 48 MHz 16K 8,192 3.8K PIC18F45J11 DC - 48 MHz 32K 16,384 3.8K 30 Ports A, B, C, D, E 5 2 MSSP (2), Enhanced USART (2) Yes 13 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 44-Pin QFN and TQFP PIC18F46J11 DC - 48 MHz 64K 32,768 3.8K Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Timers Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PMP/PSP) 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages (c) 2009 Microchip Technology Inc. DS39932C-page 13 PIC18F46J11 FAMILY FIGURE 1-1: PIC18F2XJ11 (28-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 8 PCLATU PCLATH Data Bus<8> Data Latch Data Memory (3.8 Kbytes) Address Latch 12 Data Address<12> 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank 12 PORTC RC0:RC7(1) PORTB RB0:RB7(1) PORTA RA0:RA7(1) 8 PCU PCH PCL Program Counter 31-Level Stack Address Latch Program Memory (16 Kbytes-64 Kbytes) Data Latch 8 STKPTR Table Latch Instruction Bus <16> ROM Latch Address Decode IR 8 Instruction Decode and Control State Machine Control Signals PRODH PRODL 3 BITOP 8 8 ALU<8> 8 8 x 8 Multiply 8 W 8 8 OSC2/CLKO OSC1/CLKI Timing Generation 8 MHz INTOSC INTRC Oscillator Power-up Timer Oscillator Start-up Timer Power-on Reset 8 Precision Band Gap Reference Voltage Regulator Watchdog Timer Brown-out Reset(2) VDDCORE/VCAP ADC 10-Bit VDD, VSS MCLR RTCC LVD Timer0 Timer1 Timer2 Timer3 Timer4 Comparators CTMU ECCP1 ECCP2 EUSART1 EUSART2 MSSP1 MSSP2 Note 1: 2: See Table 1-3 for I/O port pin descriptions. BOR functionality is provided when the on-chip voltage regulator is enabled. DS39932C-page 14 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 1-2: PIC18F4XJ11 (44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> inc/dec logic 21 20 Data Latch Data Memory (3.8 Kbytes) Address Latch 12 Data Address<12> 4 BSR PORTA RA0:RA7(1) 8 PCLATU PCLATH 8 PCU PCH PCL Program Counter 31-Level Stack PORTB RB0:RB7(1) System Bus Interface Address Latch Program Memory (16 Kbytes-64 Kbytes) Data Latch 8 Table Latch 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank STKPTR PORTC RC0:RC7(1) 12 PORTD RD0:RD7(1) ROM Latch Instruction Bus <16> IR Address Decode PORTE RE0:RE2(1) 8 AD<15:0>, A<19:16> (Multiplexed with PORTD and PORTE) Instruction Decode and Control State Machine Control Signals PRODH PRODL 3 BITOP 8 8 8 x 8 Multiply 8 W 8 8 8 OSC2/CLKO OSC1/CLKI Timing Generation 8 MHz INTOSC INTRC Oscillator Power-up Timer Oscillator Start-up Timer Power-on Reset ALU<8> 8 Precision Band Gap Reference Voltage Regulator Watchdog Timer Brown-out Reset(2) VDDCORE/VCAP ADC 10-Bit VDD, VSS MCLR RTCC LVD Timer0 Timer1 Timer2 Timer3 Timer4 Comparators PMP CTMU ECCP1 ECCP2 EUSART1 EUSART2 MSSP1 MSSP2 Note 1: 2: See Table 1-4 for I/O port pin descriptions. BOR functionality is provided when the on-chip voltage regulator is enabled. (c) 2009 Microchip Technology Inc. DS39932C-page 15 PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS Pin Number Pin Name 28-SPDIP/ SSOP/ 28-QFN SOIC 1 9 26 6 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. Main oscillator input connection. External clock source input; always associated with pin function OSC1 (see related OSC1/CLKI pins). Digital I/O. Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Main oscillator feedback output connection. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Digital I/O. Pin Buffer Type Type I ST Description MCLR OSC1/CLKI/RA7 OSC1 Master Clear (Reset) input. This pin is an active-low Reset to the device. CLKI RA7(1) OSC2/CLKO/RA6 OSC2 CLKO 10 7 I CMOS I/O O O TTL -- -- RA6(1) I/O TTL Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932C-page 16 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 28-SPDIP/ SSOP/ 28-QFN SOIC Pin Buffer Type Type Description PORTA is a bidirectional I/O port. RA0/AN0/C1INA/ULPWU/RP0 RA0 AN0 C1INA ULPWU RP0 RA1/AN1/C2INA/RP1 RA1 AN1 C2INA RP1 RA2/AN2/VREF-/CVREF/C2INB RA2 AN2 VREFCVREF C2INB RA3/AN3/VREF+/C1INB RA3 AN3 VREF+ C1INB RA5/AN4/SS1/HLVDIN/ RP2 RA5 AN4 SS1 HLVDIN RP2 RA6(1) RA7(1) 2 27 I/O I I I I/O 3 28 I O I I/O 4 1 I/O I O I I 5 2 I/O I I I 7 4 I/O I I I I/O DIG Analog TTL Analog DIG Digital I/O. Analog input 4. SPI slave select input. High/low-voltage detect input. Remappable peripheral pin 2. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. DIG Analog Analog Analog Digital I/O Analog input 3 A/D reference voltage (high) input Comparator 1 input B DIG Analog Analog Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. Comparator reference voltage output. Comparator 2 input B. DIG Analog Analog DIG Digital I/O. Analog input 1. Comparator 2 input A. Remappable peripheral pin 1. DIG Analog Analog Analog DIG Digital I/O. Analog input 0. Comparator 1 input A. Ultra low-power wake-up input. Remappable peripheral pin 0. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. (c) 2009 Microchip Technology Inc. DS39932C-page 17 PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 28-SPDIP/ SSOP/ 28-QFN SOIC Pin Buffer Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0/RP3 RB0 AN12 INT0 RP3 RB1/AN10/RTCC/RP4 RB1 AN10 RTCC RP4 RB2/AN8/CTEDG1/ REFO/RP5 RB2 AN8 CTEDG1 REFO RP5 RB3/AN9/CTEDG2/RP6 RB3 AN9 CTEDG2 RP6 RB4/KBI0/RP7 RB4 KBI0 RP7 RB5/KBI1/RP8 RB5 KBI1 RP8 21 18 I/O I I I/O 22 19 I/O I O I/O 23 20 I/O I I O I/O 24 21 I/O I I/O I 25 22 I/O I I/O 26 23 I/O I/O I/O DIG DIG DIG Digital I/O. Parallel Master Port address. Remappable peripheral pin 8. DIG TTL DIG Digital I/O. Interrupt-on-change pin. Remappable peripheral pin 7. DIG Analog ST DIG Digital I/O. Analog input 9. CTMU edge 2 input. Remappable peripheral pin 6. DIG Analog ST DIG DIG Digital I/O. Analog input 8. CTMU edge 1 input. Reference output clock. Remappable peripheral pin 5. DIG Analog DIG DIG Digital I/O. Analog input 10. Asynchronous serial transmit data output. Remappable peripheral pin 4. DIG Analog ST DIG Digital I/O. Analog input 12. External interrupt 0. Remappable peripheral pin 3. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932C-page 18 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 28-SPDIP/ SSOP/ 28-QFN SOIC Pin Buffer Type Type Description PORTB (continued) RB6/KBI2/PGC/RP9 RB6 KBI2 PGC RP9 RB7/KBI3/PGD/RP10 RB7 KBI3 PGD RP10 27 24 I/O I I I/O 28 25 I/O I I/O I/O DIG TTL ST DIG Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. Remappable peripheral pin 10. DIG TTL ST DIG Digital I/O. Interrupt-on-change pin. ICSPTM clock input. Remappable peripheral pin 9. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. (c) 2009 Microchip Technology Inc. DS39932C-page 19 PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 28-SPDIP/ SSOP/ 28-QFN SOIC Pin Buffer Type Type Description PORTC is a bidirectional I/O port RC0/T1OSO/T1CKI/RP11 RC0 T1OSO T1CKI RP11 RC1/T1OSI/RP12 RC1 T1OSI RP12 RC2/AN11/CTPLS/RP13 RC2 AN11 CTPLS RP13 RC3/SCK1/SCL1/RP14 RC3 SCK1 SCL1 RP14 RC4/SDI1/SDA1/RP15 RC4 SDI1 SDA1 RP15 RC5/SDO1/RP16 RC5 SDO1 RP16 RC6/TX1/CK1/RP17 RC6 TX1 CK1 RP17 RC7/RX1/DT1/RP18 RC7 RX1 DT1 RP18 18 15 I/O I I/O I/O ST ST ST DIG Digital I/O. Asynchronous serial receive data input. Synchronous serial data output/input. Remappable peripheral pin 18. 15 12 I/O I I/O I/O 16 13 I/O O I/O 17 14 I/O O I/O I/O ST DIG ST DIG Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). Remappable peripheral pin 17. ST DIG DIG Digital I/O. SPI data output. Remappable peripheral pin 16. ST ST I2C DIG Digital I/O. SPI data input. I2C data I/O. Remappable peripheral pin 15. 11 8 I/O O I I/O 12 9 I/O I I/O 13 10 I/O I O I/O 14 11 I/O I/O I/O I/O ST DIG I2C DIG Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. Remappable peripheral pin 14. ST Analog DIG DIG Digital I/O. Analog input 11. CTMU pulse generator output. Remappable peripheral pin 13. ST Analog DIG Digital I/O. Timer1 oscillator input. Remappable peripheral pin 12. ST Analog ST DIG Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Remappable peripheral pin 11. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932C-page 20 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 28-SPDIP/ SSOP/ 28-QFN SOIC 8 19 20 6 5 16 17 3 P P -- -- Pin Buffer Type Type P -- P -- -- -- Positive supply for peripheral digital logic and I/O pins. Core logic power or external filter capacitor connection. Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled). Description VSS1 VSS2 VDD VDDCORE/VCAP VDDCORE VCAP Ground reference for logic and I/O pins. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. (c) 2009 Microchip Technology Inc. DS39932C-page 21 PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS Pin Number Pin Name MCLR OSC1/CLKI/RA7 OSC1 Pin Buffer 4444- Type Type QFN TQFP 18 32 18 30 I ST I ST Description Master Clear (Reset) input; this is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. Main oscillator input connection. External clock source input; always associated with pin function OSC1 (see related OSC1/CLKI pins). Digital I/O. Oscillator crystal or clock output Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Main oscillator feedback output connection in RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Digital I/O. CLKI RA7(1) OSC2/CLKO/RA6 OSC2 CLKO 33 31 I CMOS I/O O O TTL -- -- RA6(1) I/O TTL Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932C-page 22 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 4444- Type Type QFN TQFP Description PORTA is a bidirectional I/O port. RA0/AN0/C1INA/ULPWU/PMA6/ RP0 RA0 AN0 C1INA ULPWU PMA6 RP0 RA1/AN1/C2INA/PMA7/RP1 RA1 AN1 C2INA PMA7 RP1 RA2/AN2/VREF-/CVREF/C2INB RA2 AN2 VREFCVREF C2INB RA3/AN3/VREF+/C1INB RA3 AN3 VREF+ C1INB RA5/AN4/SS1/HLVDIN/RP2 RA5 AN4 SS1 HLVDIN RP2 RA6(1) RA7(1) 19 19 I/O I I I I/O I/O 20 20 I O I I/O I/O 21 21 I/O I O I I 22 22 I/O I I I 24 24 I/O I I I I/O DIG Analog TTL Analog DIG Digital I/O. Analog input 4. SPI slave select input. High/low-voltage detect input. Remappable peripheral pin 2. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. DIG Analog Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. Comparator 1 input B. DIG Analog Analog Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. Comparator reference voltage output. Comparator 2 input B. DIG Analog Analog DIG DIG Digital I/O. Analog input 1. Comparator 2 input A. Parallel Master Port digital I/O. Remappable peripheral pin 1. DIG Analog Analog Analog DIG DIG Digital I/O. Analog input 0. Comparator 1 input A. Ultra low-power wake-up input. Parallel Master Port digital I/O. Remappable peripheral pin 0. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. (c) 2009 Microchip Technology Inc. DS39932C-page 23 PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 4444- Type Type QFN TQFP Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0/RP3 RB0 AN12 INT0 RP3 RB1/AN10/PMBE/RTCC/RP4 RB1 AN10 PMBE RTCC RP4 RB2/AN8/CTEDG1/PMA3/REFO/ RP5 RB2 AN8 CTEDG1 PMA3 REFO RP5 RB3/AN9/CTEDG2/PMA2/RP6 RB3 AN9 CTEDG2 PMA2 RP6 9 8 I/O I I I/O 10 9 I/O I O O I/O 11 10 I/O I I O O I/O 12 11 I/O I I O I/O DIG Analog ST DIG DIG Digital I/O. Analog input 9. CTMU edge 2 input. Parallel Master Port address. Remappable peripheral pin 6. DIG Analog ST DIG DIG DIG Digital I/O. Analog input 8. CTMU edge 1 input. Parallel Master Port address. Reference output clock. Remappable peripheral pin 5. DIG Analog DIG DIG DIG Digital I/O. Analog input 10. Parallel Master Port byte enable. Asynchronous serial transmit data output. Remappable peripheral pin 4. DIG Analog ST DIG Digital I/O. Analog input 12. External interrupt 0. Remappable peripheral pin 3. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932C-page 24 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 4444- Type Type QFN TQFP Description PORTB (continued) RB4/PMA1/KBI0/RP7 RB4 PMA1 KBI0 RP7 RB5/PMA0/KBI1/RP8 RB5 PMA0 KBI1 RP8 RB6/KBI2/PGC/RP9 RB6 KBI2 PGC RP9 RB7/KBI3/PGD/RP10 RB7 KBI3 PGD RP10 14 14 I/O I/O I I/O 15 15 I/O I/O I I/O 16 16 I/O I I I/O 17 17 I/O I I/O I/O DIG TTL ST DIG Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. Remappable peripheral pin 10. DIG TTL ST DIG Digital I/O. Interrupt-on-change pin. ICSPTM clock input. Remappable peripheral pin 9. DIG DIG TTL DIG Digital I/O. Parallel Master Port address. Interrupt-on-change pin. Remappable peripheral pin 8. DIG DIG TTL DIG Digital I/O. Parallel Master Port address. Interrupt-on-change pin. Remappable peripheral pin 7 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. (c) 2009 Microchip Technology Inc. DS39932C-page 25 PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 4444- Type Type QFN TQFP Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI/RP11 RC0 T1OSO T1CKI RP11 RC1/T1OSI/RP12 RC1 T1OSI RP12 RC2/AN11/CTPLS/RP13 RC2 AN11 CTPLS RP13 RC3/SCK1/SCL1/RP14 RC3 SCK1 SCL1 RP14 RC4/SDI1/SDA1/RP15 RC4 SDI1 SDA1 RP15 RC5/SDO1/RP16 RC5 SDO1 RP16 42 42 I/O I I/O I/O 43 43 I/O O I/O ST DIG DIG Digital /O. SPI data output. Remappable peripheral pin 16. ST ST I2C DIG Digital I/O. SPI data input. I2C data I/O. Remappable peripheral pin 15. 34 32 I/O O I I/O 35 35 I/O I I/O 36 36 I/O I O I/O 37 37 I/O I/O I/O I/O ST DIG I2C DIG Digital I/0. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. Remappable peripheral pin 14. ST Analog DIG DIG Digital I/O. Analog input 11. CTMU pulse generator output. Remappable peripheral pin 13. ST Analog DIG Digital I/O. Timer1 oscillator input. Remappable peripheral pin 12. ST Analog ST DIG Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Remappable peripheral pin 11. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932C-page 26 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 4444- Type Type QFN TQFP 44 44 I/O I/O O I/O I/O 1 1 I/O I/O I I/O I/O ST DIG ST ST DIG EUSART1 asynchronous receive. Parallel Master Port address. EUSART1 synchronous data (see related TX1/CK1). Synchronous serial data output/input. Remappable peripheral pin 18. ST DIG DIG ST DIG Digital I/O. Parallel Master Port address. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). Remappable peripheral pin 17. Description PORTC (continued) RC6/PMA5/TX1/CK1/RP17 RC6 PMA5 TX1 CK1 RP17 RC7/PMA4/RX1/DT1/RP18 RC7 PMA4 RX1 DT1 RP18 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. (c) 2009 Microchip Technology Inc. DS39932C-page 27 PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 4444- Type Type QFN TQFP Description PORTD is a bidirectional I/O port. RD0/PMD0/SCL2 RD0 PMD0 SCL2 RD1/PMD1/SDA2 RD1 PMD1 SDA2 RD2/PMD2/RP19 RD2 PMD2 RP19 RD3/PMD3/RP20 RD3 PMD3 RP20 RD4/PMD4/RP21 RD4 PMD4 RP21 RD5/PMD5/RP22 RD5 PMD5 RP22 RD6/PMD6/RP23 RD6 PMD6 RP23 RD7/PMD7/RP24 RD7 PMD7 RP24 38 38 I/O I/O I/O 39 39 I/O I/O I/O 40 40 I/O I/O I/O 41 41 I/O I/O I/O 2 2 I/O I/O I/O 3 3 I/O I/O I/O 4 4 I/O I/O I/O 5 5 I/O I/O I/O ST DIG DIG Digital I/O. Parallel Master Port data. Remappable peripheral pin 24. ST DIG DIG Digital I/O. Parallel Master Port data. Remappable peripheral pin 23. ST DIG DIG Digital I/O. Parallel Master Port data. Remappable peripheral pin 22. ST DIG DIG Digital I/O. Parallel Master Port data. Remappable peripheral pin 21. ST DIG DIG Digital I/O. Parallel Master Port data. Remappable peripheral pin 20. ST DIG DIG Digital I/O. Parallel Master Port data. Remappable peripheral pin 19. ST DIG I2C Digital I/O. Parallel Master Port data. I2C data input/output. ST DIG I2C Digital I/O. Parallel Master Port data. I2CTM data input/output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932C-page 28 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 4444- Type Type QFN TQFP Description PORTE is a bidirectional I/O port. RE0/AN5/PMRD RE0 AN5 PMRD RE1/AN6/PMWR RE1 AN6 PMWR RE2/AN7/PMCS RE2 AN7 PMCS VSS1 VSS2 AVSS1 VDD1 VDD2 VDDCORE/VCAP VDDCORE VCAP AVDD1 AVDD2 7 28 -- -- 25 25 I/O I I/O 26 26 I/O I I/O 27 27 I/O I O 6 31 30 8 29 23 6 29 -- 7 28 23 P P P -- -- -- -- -- P -- P P P ST Analog -- -- -- -- -- -- Ground reference for analog modules. Positive supply for peripheral digital logic and I/O pins. Core logic power or external filter capacitor connection. Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled). Positive supply for analog modules. Positive supply for analog modules. Digital I/O. Analog input 7. Parallel Master Port byte enable. Ground reference for logic and I/O pins. ST Analog DIG Digital I/O. Analog input 6. Parallel Master Port write strobe. ST Analog DIG Digital I/O. Analog input 5. Parallel Master Port input/output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. (c) 2009 Microchip Technology Inc. DS39932C-page 29 PIC18F46J11 FAMILY NOTES: DS39932C-page 30 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 2.0 2.1 OSCILLATOR CONFIGURATIONS Overview TABLE 2-1: Mode ECPLL OSCILLATOR MODES Description External Clock Input mode, the PLL can be enabled or disabled in software, CLKO on RA6, apply external clock signal to RA7. External Clock Input mode, the PLL is always disabled, CLKO on RA6, apply external clock signal to RA7. High-Speed Crystal/Resonator mode, PLL can be enabled or disabled in software, crystal/resonator connected between RA6 and RA7. High-Speed Crystal/Resonator mode, PLL always disabled, crystal/resonator connected between RA6 and RA7. Devices in the PIC18F46J11 family incorporate a different oscillator and microcontroller clock system than general purpose PIC18F devices. The PIC18F46J11 family has additional prescalers and postscalers, which have been added to accommodate a wide range of oscillator frequencies. Figure 2-1 provides an overview of the oscillator structure. Other oscillator features used in PIC18 enhanced microcontrollers, such as the internal oscillator block and clock switching, remain the same. They are discussed later in this chapter. EC HSPLL HS 2.1.1 OSCILLATOR CONTROL The operation of the oscillator in PIC18F46J11 family devices is controlled through three Configuration registers and two control registers. Configuration registers, CONFIG1L, CONFIG1H and CONFIG2L, select the oscillator mode, PLL prescaler and CPU divider options. As Configuration bits, these are set when the device is programmed and left in that configuration until the device is reprogrammed. The OSCCON register (Register 2-2) selects the Active Clock mode; it is primarily used in controlling clock switching in power-managed modes. Its use is discussed in Section 2.3.1 "Oscillator Control Register". The OSCTUNE register (Register 2-1) is used to trim the INTOSC frequency source and select the low-frequency clock source that drives several special features. The OSCTUNE register is also used to activate or disable the Phase Locked Loop (PLL). Its use is described in Section 2.2.5.1 "OSCTUNE Register". INTOSCPLLO Internal Oscillator mode, PLL can be enabled or disabled in software, CLKO on RA6, port function on RA7, the internal oscillator block is used to derive both the primary clock source and the postscaled internal clock. INTOSCPLL Internal Oscillator mode, PLL can be enabled or disabled in software, port function on RA6 and RA7, the internal oscillator block is used to derive both the primary clock source and the postscaled internal clock. INTOSCO Internal Oscillator mode, PLL is always disabled, CLKO on RA6, port function on RA7, the output of the INTOSC postscaler serves as both the postscaled internal clock and the primary clock source. Internal Oscillator mode, PLL is always disabled, port function on RA6 and RA7, the output of the INTOSC postscaler serves as both the postscaled internal clock and the primary clock source. INTOSC 2.2 Oscillator Types PIC18F46J11 family devices can be operated in eight distinct oscillator modes. Users can program the FOSC<2:0> Configuration bits to select one of the modes listed in Table 2-1. For oscillator modes which produce a clock output (CLKO) on pin RA6, the output frequency will be one fourth of the peripheral clock frequency. The clock output stops when in Sleep mode, but will continue during Idle mode (see Figure 2-1). (c) 2009 Microchip Technology Inc. DS39932C-page 31 PIC18F46J11 FAMILY 2.2.1 OSCILLATOR MODES Figure 2-1 helps in understanding the oscillator structure of the PIC18F46J11 family of devices. FIGURE 2-1: PIC18F46J11 FAMILY CLOCK DIAGRAM PIC18F46J11 Family Primary Oscillator OSC2 Sleep OSC1 T1OSO Secondary Oscillator T1OSCEN Enable Oscillator OSCCON<6:4> Internal Oscillator Block 8 MHz Source 8 MHz (INTOSC) OSCTUNE<7> 4 x PLL(1) HS, EC HSPLL, ECPLL, INTPLL T1OSC Peripherals T1OSI OSCCON<6:4> 8 MHz 4 MHz 2 MHz Postscaler 1 MHz 500 kHz 250 kHz 125 kHz Internal Oscillator 111 110 101 011 010 001 MUX 100 Clock Control FOSC<2:0> OSCCON<1:0> IDLEN CPU 1 31 kHz 000 0 INTRC Source 31 kHz (INTRC) OSCTUNE<7> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up Note 1: 8 MHz and 4 MHz are valid INTOSC postscaler settings for the PLL. Selecting other INTOSC postscaler settings will operate the PLL outside of the specification. DS39932C-page 32 (c) 2009 Microchip Technology Inc. MUX PIC18F46J11 FAMILY 2.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS TABLE 2-3: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq 4 MHz 8 MHz 20 MHz Typical Capacitor Values Tested: C1 27 pF 22 pF 15 pF C2 27 pF 22 pF 15 pF In HS and HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-2 displays the pin connections. The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer's specifications. Osc Type HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 4 MHz 8 MHz 20 MHz Note 1: Higher capacitance not only increases the stability of oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: Rs may be required to avoid overdriving crystals with low drive level specification. 4: Always verify oscillator performance over the VDD and temperature range that is expected for the application. An internal postscaler allows users to select a clock frequency other than that of the crystal or resonator. Frequency division is determined by the CPDIV Configuration bits. Users may select a clock frequency of the oscillator frequency, or 1/2, 1/3 or 1/6 of the frequency. FIGURE 2-2: CRYSTAL/CERAMIC RESONATOR OPERATION (HS OR HSPLL CONFIGURATION) OSC1 To Internal Logic Sleep C1(1) XTAL RS(2) C2(1) Note 1: 2: 3: OSC2 RF(3) PIC18F46J11 See Table 2-2 and Table 2-3 for initial values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the selected oscillator mode. TABLE 2-2: CAPACITOR SELECTION FOR CERAMIC RESONATORS Freq 8.0 MHz 16.0 MHz OSC1 27 pF 22 pF OSC2 27 pF 22 pF Typical Capacitor Values Used: Mode HS Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table 2-3 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz (c) 2009 Microchip Technology Inc. DS39932C-page 33 PIC18F46J11 FAMILY 2.2.3 EXTERNAL CLOCK INPUT 2.2.5 INTERNAL OSCILLATOR BLOCK The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset (POR) or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided-by-4 is available on the OSC2 pin. In the ECPLL Oscillator mode, the PLL output divided-by-4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 displays the pin connections for the EC Oscillator mode. The PIC18F46J11 family devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller's clock source. The internal oscillator may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source which can be used to directly drive the device clock. It also drives the INTOSC postscaler, which can provide a range of clock frequencies from 31 kHz to 8 MHz. Additionally, the INTOSC may be used in conjunction with the PLL to generate clock frequencies up to 32 MHz. The other clock source is the internal RC oscillator (INTRC), which provides a nominal 31 kHz output. INTRC is enabled if it is selected as the device clock source. It is also enabled automatically when any of the following are enabled: * * * * Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (EC AND ECPLL CONFIGURATION) OSC1/CLKI Clock from Ext. System FOSC/4 PIC18F46J11 OSC2/CLKO 2.2.4 PLL FREQUENCY MULTIPLIER A Phase Locked Loop (PLL) circuit is provided as an option for users who want to use a lower frequency oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator. These features are discussed in more detail in Section 25.0 "Special Features of the CPU". The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 38). DS39932C-page 34 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 2.2.5.1 OSCTUNE Register 2.2.5.3 Compensating for INTOSC Drift The internal oscillator's output has been calibrated at the factory but can be adjusted in the user's application. This is done by writing to the OSCTUNE register (Register 2-1). The tuning sensitivity is constant throughout the tuning range. When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. The INTOSC clock will stabilize, typically within 1 s. Code execution continues during this shift. There is no indication that the shift has occurred. The OSCTUNE register also contains the INTSRC bit. The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31 kHz frequency option is selected. This is covered in more detail in Section 2.3.1 "Oscillator Control Register". The 4x Phase Locked Loop (PLL) can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with the internal oscillator sources. When enabled, the PLL produces a clock speed up to 32 MHz. PLL operation is controlled through software. The control bit, PLLEN (OSCTUNE<6>), is used to enable or disable its operation. The PLL is available only to INTOSC when the device is configured to use one of the INTPLL modes as the primary clock source, SCS<1:0> = 00 (FOSC<2:0> = 011 or 010). Additionally, the PLL will only function when the selected output frequency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111 or 110). When configured for one of the PLL enabled modes, setting the PLLEN bit does not immediately switch the device clock to the PLL output. The PLL requires up to two milliseconds to start-up and lock, during which time, the device continues to be clocked. Once the PLL output is ready, the microcontroller core will automatically switch to the PLL derived frequency. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency. Tuning the INTOSC source requires knowing when to make the adjustment, in which direction it should be made, and in some cases, how large a change is needed. When using the EUSART, for example, an adjustment may be required when it begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high; to adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment OSCTUNE to increase the clock frequency. It is also possible to verify device clock speed against a reference clock. Two timers may be used: one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. Finally, an ECCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is greater than the calculated time, the internal oscillator block is running too fast; to compensate, decrement the OSCTUNE register. If the measured time is less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the OSCTUNE register. 2.2.5.2 Internal Oscillator Output Frequency and Drift The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. The low-frequency INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. (c) 2009 Microchip Technology Inc. DS39932C-page 35 PIC18F46J11 FAMILY REGISTER 2-1: R/W-0 INTSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown OSCTUNE: OSCILLATOR TUNING REGISTER (ACCESS F9Bh) R/W-0 PLLEN R/W-0 TUN5 R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled) 0 = 31 kHz device clock derived directly from INTRC internal oscillator PLLEN: Frequency Multiplier Enable bit 1 = PLL enabled 0 = PLL disabled TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 * * * 000001 000000 = Center frequency; oscillator module is running at the calibrated frequency 111111 * * * 100000 = Minimum frequency bit 6 bit 5-0 2.3 Clock Sources and Oscillator Switching Like previous PIC18 enhanced devices, the PIC18F46J11 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate, low-frequency clock source. PIC18F46J11 family devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available. Essentially, there are three clock sources for these devices: * Primary Oscillators * Secondary Oscillators * Internal Oscillator Block The Primary Oscillators include the External Crystal and Resonator modes, the External Clock modes and the internal oscillator block. The particular mode is defined by the FOSC<2:0> Configuration bits. The details of these modes are covered earlier in this chapter. The Secondary Oscillators are external sources that are not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F46J11 family devices offer the Timer1 oscillator as a secondary oscillator. This oscillator, in all power-managed modes, is often the time base for functions such as a Real-Time Clock (RTC). Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/T1CKI/RP11 and RC1/T1OSI/RP12 pins. Like the HS Oscillator mode circuits, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in more detail in Section 12.5 "Timer1 Oscillator". In addition to being a primary clock source, the postscaled internal clock is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor (FSCM). DS39932C-page 36 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 2.3.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-2) controls several aspects of the device clock's operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS<1:0>, select the clock source. The available clock sources are the primary clock (defined by the FOSC<2:0> Configuration bits), the secondary clock (Timer1 oscillator) and the postscaled internal clock.The clock source changes immediately, after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared on all forms of Reset. The Internal Oscillator Frequency Select bits, IRCF<2:0>, select the frequency output provided on the postscaled internal clock line. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the frequencies derived from the INTOSC postscaler (31 kHz to 4 MHz). If the postscaled internal clock is supplying the device clock, changing the states of these bits will have an immediate change on the internal oscillator's output. On device Resets, the default output frequency of the INTOSC postscaler is set at 4 MHz. When an output frequency of 31 kHz is selected (IRCF<2:0> = 000), users may choose the internal oscillator, which acts as the source. This is done with the INTSRC bit in the OSCTUNE register (OSCTUNE<7>). Setting this bit selects INTOSC as a 31.25 kHz clock source by enabling the divide-by-256 output of the INTOSC postscaler. Clearing INTSRC selects INTRC (nominally 31 kHz) as the clock source. This option allows users to select the tunable and more precise INTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the WDT and the FSCM. The OSTS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer (OST) has timed out and the primary clock is providing the device clock in primary clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. The IDLEN bit determines if the device goes into Sleep mode, or one of the Idle modes, when the SLEEP instruction is executed. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 3.0 "Low-Power Modes". Note 1: The Timer1 crystal driver is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select the Timer1 clock source will be ignored, unless the CONFIG2L register's T1DIG bit is set. 2: If Timer1 is driving a crystal, it is recommended that the Timer1 oscillator be operating and stable prior to switching to it as the clock source; otherwise, a very long delay may occur while the Timer1 oscillator starts. 2.3.2 OSCILLATOR TRANSITIONS PIC18F46J11 family devices contain circuitry to prevent clock "glitches" when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in more detail in Section 3.1.2 "Entering Power-Managed Modes". (c) 2009 Microchip Technology Inc. DS39932C-page 37 PIC18F46J11 FAMILY REGISTER 2-2: R/W-0 IDLEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown OSCCON: OSCILLATOR CONTROL REGISTER (ACCESS FD3h) R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 R-1(1) OSTS U-1 -- R/W-0 SCS1 R/W-0 SCS0 bit 0 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8 MHz (INTOSC drives clock directly) 110 = 4 MHz(2) 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (from either INTOSC/256 or INTRC directly)(3) OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready Unimplemented: Read as `1' SCS<1:0>: System Clock Select bits 11 = Postscaled internal clock (INTRC/INTOSC derived) 10 = Reserved 01 = Timer1 oscillator 00 = Primary clock source (INTOSC postscaler output when FOSC<2:0> = 001 or 000) 00 = Primary clock source (CPU divider output for other values of FOSC<2:0>) Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. Default output frequency of INTOSC on Reset (4 MHz). Source selected by the INTSRC bit (OSCTUNE<7>). bit 6-4 bit 3 bit 2 bit 1-0 Note 1: 2: 3: DS39932C-page 38 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 2.4 Reference Clock Output In addition to the peripheral clock/4 output in certain oscillator modes, the device clock in the PIC18F46J11 family can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 2-3). Setting the ROON bit (REFOCON<7>) makes the clock signal available on the REFO (RB2) pin. The RODIV<3:0> bits enable the selection of 16 different clock divider options. The ROSSLP and ROSEL bits (REFOCON<5:4>) control the availability of the reference output during Sleep mode. The ROSEL bit determines if the oscillator is on OSC1 and OSC2, or the current system clock source is used for the reference clock output. The ROSSLP bit determines if the reference source is available on RB2 when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for an EC or HS mode; otherwise, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. REGISTER 2-3: R/W-0 ROON bit 7 Legend: R = Readable bit -n = Value at POR bit 7 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (BANKED F3Dh) U-0 -- R/W-0 ROSSLP R/W-0 ROSEL R/W-0 RODIV3 R/W-0 RODIV2 R/W-0 RODIV1 R/W-0 RODIV0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator enabled on REFO pin 0 = Reference oscillator disabled Unimplemented: Read as `0' ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator used as the base clock(1) 0 = System clock used as the base clock; base clock reflects any clock switching of the device RODIV<3:0>: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode. bit 6 bit 5 bit 4 bit 3-0 Note 1: (c) 2009 Microchip Technology Inc. DS39932C-page 39 PIC18F46J11 FAMILY 2.5 Effects of Power-Managed Modes on Various Clock Sources 2.6 Power-up Delays Power-up delays are controlled by two timers so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 4.6 "Power-up Timer (PWRT)". The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 28-13). The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS mode). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. There is a delay of interval, TCSD (parameter 38, Table 28-13), following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the internal oscillator or EC modes are used as the primary clock source. When the PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1 or Timer3. In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features regardless of the power-managed mode (see Section 25.2 "Watchdog Timer (WDT)", Section 25.4 "Two-Speed Start-up" and Section 25.5 "Fail-Safe Clock Monitor" for more information on WDT, FSCM and Two-Speed Start-up). The INTOSC output at 8 MHz may be used directly to clock the device or may be divided down by the postscaler. The INTOSC output is disabled if the clock is provided directly from the INTRC output. If Sleep mode is selected, all clock sources, which are no longer required, are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents) outside of Deep Sleep mode. Enabling any on-chip feature that will operate during Sleep mode increases the current consumed during Sleep mode. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support an RTC. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PMP, INTx pins, etc.). Peripherals that may add significant current consumption are listed in Section 28.2 "DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial)". DS39932C-page 40 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 3.0 LOW-POWER MODES The PIC18F46J11 family devices can manage power consumption through clocking to the CPU and the peripherals. In general, reducing the clock frequency and the amount of circuitry being clocked reduces power consumption. For managing power in an application, the primary modes of operation are: * * * * Run Mode Idle Mode Sleep Mode Deep Sleep Mode The IDLEN bit (OSCCON<7>) controls CPU clocking and the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1. 3.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: * Primary clock source - Defined by the FOSC<2:0> Configuration bits * Timer1 clock - Provided by the secondary oscillator * Postscaled internal clock - Derived from the internal oscillator block Additionally, there is an Ultra Low-Power Wake-up (ULPWU) mode for generating an interrupt-on-change on RA0. These modes define which portions of the device are clocked and at what speed. * The Run and Idle modes can use any of the three available clock sources (primary, secondary or internal oscillator blocks). * The Sleep mode does not use a clock source. The ULPWU mode on RA0 allows a slow falling voltage to generate an interrupt-on-change on RA0 without excess current consumption. See Section 3.7 "Ultra Low-Power Wake-up". The power-managed modes include several power-saving features offered on previous PIC(R) devices, such as clock switching, ULPWU and Sleep mode. In addition, the PIC18F46J11 family devices add a new power-managed Deep Sleep mode. 3.1.2 ENTERING POWER-MANAGED MODES Switching from one clock source to another begins by loading the OSCCON register. The SCS<1:0> bits select the clock source. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch also may be subject to clock transition delays. These delays are discussed in Section 3.1.3 "Clock Transitions and Status Indicators" and subsequent sections. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, the IDLEN bit or the DSEN bit prior to issuing a SLEEP instruction. If the IDLEN and DSEN bits are already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. 3.1 Selecting Power-Managed Modes Selecting a power-managed mode requires these decisions: * Will the CPU be clocked? * If so, which clock source will be used? (c) 2009 Microchip Technology Inc. DS39932C-page 41 PIC18F46J11 FAMILY TABLE 3-1: Mode Sleep Deep Sleep(2) PRI_RUN SEC_RUN RC_RUN PRI_IDLE LOW-POWER MODES OSCCON<7,1:0> IDLEN 0 0 N/A N/A N/A 1 (1) DSCONH<7> DSEN(1) 0 1 0 0 0 0 Module Clocking CPU Off Off Clocked Clocked Clocked Off Peripherals Off -- Clocked Clocked Clocked Clocked SCS<1:0> N/A N/A 00 01 11 00 Available Clock and Oscillator Source Timer1 oscillator and/or RTCC optionally enabled RTCC can run uninterrupted using the Timer1 or internal low-power RC oscillator The normal, full-power execution mode. Primary clock source (defined by FOSC<2:0>) Secondary - Timer1 oscillator Postscaled internal clock Primary clock source (defined by FOSC<2:0>) SEC_IDLE 0 1 01 Off Clocked Secondary - Timer1 oscillator RC_IDLE 0 1 11 Off Clocked Postscaled internal clock Note 1: IDLEN and DSEN reflect their values when the SLEEP instruction is executed. 2: Deep Sleep entirely shuts off the voltage regulator for ultra low-power consumption. See Section 3.6 "Deep Sleep Mode" for more information. 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS 3.2.1 PRI_RUN MODE The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status: OSTS (OSCCON<3>) and T1RUN (T1CON<6>). In general, only one of these bits will be set in a given power-managed mode. When the OSTS bit is set, the primary clock would be providing the device clock. When the T1RUN bit is set, the Timer1 oscillator would be providing the clock. If neither of these bits is set, INTRC would be clocking the device. Note: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep or Deep Sleep mode, or one of the Idle modes, depending on the setting of the IDLEN bit. The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section 25.4 "Two-Speed Start-up" for details). In this mode, the OSTS bit is set (see Section 2.3.1 "Oscillator Control Register"). 3.2.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of low-power consumption while still using a high-accuracy clock source. SEC_RUN mode is entered by setting the SCS<1:0> bits to `01'. The device clock source is switched to the Timer1 oscillator (see Figure 3-1), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS<1:0> bits are set to `01', entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. 3.1.4 MULTIPLE SLEEP COMMANDS The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN and DSEN bits at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN and DSEN at that time. If IDLEN or DSEN have changed, the device will enter the new power-managed mode specified by the new setting. 3.2 Run Modes In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. DS39932C-page 42 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock would be providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 2 3 Clock Transition n-1 n Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS<1:0> Bits Changed PC OSTS Bit Set Clock Transition PC + 2 PC + 4 Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. (c) 2009 Microchip Technology Inc. DS39932C-page 43 PIC18F46J11 FAMILY 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conservation of all the Run modes while still executing code. It works well for user applications, which are not highly timing-sensitive or do not require high-speed clocks at all times. This mode is entered by setting the SCS<1:0> bits (OSCCON<1:0>) to `11'. When the clock source is switched to the internal oscillator block (see Figure 3-3), the primary oscillator is shut down and the OSTS bit is cleared. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC block while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-4). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC clock source will continue to run if either the WDT or the FSCM is enabled. FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 2 3 Clock Transition n-1 n Q3 Q4 Q1 Q2 Q3 INTRC OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS<1:0> Bits Changed PC OSTS Bit Set Clock Transition PC + 2 PC + 4 Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39932C-page 44 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 3.3 Sleep Mode The power-managed Sleep mode is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 3-6), or it will be clocked from the internal oscillator if either the Two-Speed Start-up or the FSCM is enabled (see Section 25.0 "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. FIGURE 3-5: OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 PC + 2 FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 PLL Clock Output CPU Clock Peripheral Clock Program Counter Wake Event PC OSTS Bit Set PC + 2 PC + 4 PC + 6 TOST(1) TPLL(1) Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. (c) 2009 Microchip Technology Inc. DS39932C-page 45 PIC18F46J11 FAMILY 3.4 Idle Modes The Idle modes allow the controller's CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS<1:0> bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (parameter 38, Table 28-13) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle or Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, TCSD, is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-8). 3.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS<1:0> to `01' and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 3-8). Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to "warm up" or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set the SCS bits to `00' and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC<1:0> Configuration bits. The OSTS bit remains set (see Figure 3-7). DS39932C-page 46 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 Q2 Q3 Q4 Q1 FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 CPU Clock Peripheral Clock Program Counter Wake Event PC TCSD (c) 2009 Microchip Technology Inc. DS39932C-page 47 PIC18F46J11 FAMILY 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP. When the clock source is switched to the INTOSC block, the primary oscillator is shut down and the OSTS bit is cleared. When a wake event occurs, the peripherals continue to be clocked from the internal oscillator block. After a delay of TCSD following the wake event, the CPU begins executing code being clocked by the INTRC. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the FSCM is enabled. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 3.2 "Run Modes" and Section 3.3 "Sleep Mode"). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 25.2 "Watchdog Timer (WDT)"). The WDT and postscaler are cleared by one of the following events: * Executing a SLEEP or CLRWDT instruction * The loss of a currently selected clock source (if the FSCM is enabled) 3.5.3 EXIT BY RESET Exiting an Idle or Sleep mode by Reset automatically forces the device to run from the INTRC. 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY 3.5 Exiting Idle and Sleep Modes An exit from Sleep mode, or any of the Idle modes, is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes sections (see Section 3.2 "Run Modes", Section 3.3 "Sleep Mode" and Section 3.4 "Idle Modes"). Certain exits from power-managed modes do not invoke the OST at all. There are two cases: * PRI_IDLE mode (where the primary clock source is not stopped) and the primary clock source is the EC mode * PRI_IDLE mode and the primary clock source is the ECPLL mode In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (EC). However, a fixed delay of interval, TCSD, following the wake event, is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 3.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode, or the Sleep mode, to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 8.0 "Interrupts"). A fixed delay of interval, TCSD, following the wake event, is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 3.6 Deep Sleep Mode Deep Sleep mode brings the device into its lowest power consumption state without requiring the use of external switches to remove power from the device. During deep sleep, the on-chip VDDCORE voltage regulator is powered down, effectively disconnecting power to the core logic of the microcontroller. Note: Since Deep Sleep mode powers down the microcontroller by turning off the on-chip VDDCORE voltage regulator, Deep Sleep capability is available only on PIC18FXXJ members in the device family. The on-chip voltage regulator is not available in PIC18LFXXJ members of the device family, and therefore, they do not support Deep Sleep. 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. DS39932C-page 48 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY On devices that support it, the Deep Sleep mode is entered by: * Setting the REGSLP (WDTCON<7>) bit (the default state on device Reset) * Clearing the IDLEN bit (the default state on device Reset) * Setting the DSEN bit (DSCONH<7>) * Executing the SLEEP instruction immediately after setting DSEN (no delay in between) In order to minimize the possibility of inadvertently entering Deep Sleep, the DSEN bit is cleared in hardware two instruction cycles after having been set. Therefore, in order to enter Deep Sleep, the SLEEP instruction must be executed in the immediate instruction cycle after setting DSEN. If DSEN is not set when Sleep is executed, the device will enter conventional Sleep mode instead. During Deep Sleep, the core logic circuitry of the microcontroller is powered down to reduce leakage current. Therefore, most peripherals and functions of the microcontroller become unavailable during Deep Sleep. However, a few specific peripherals and functions are powered directly from the VDD supply rail of the microcontroller, and therefore, can continue to function in Deep Sleep. Entering Deep Sleep mode clears the DSWAKEL register. However, if the Real-Time Clock and Calendar (RTCC) is enabled prior to entering Deep Sleep, it will continue to operate uninterrupted. The device has dedicated low-power Brown-out Reset (DSBOR) and Watchdog Timer Reset (DSWDT) for monitoring voltage and time-out events in Deep Sleep. The DSBOR and DSWDT are independent of the standard BOR and WDT used with other power-managed modes (Run, Idle and Sleep). When a wake event occurs in Deep Sleep mode (by MCLR Reset, RTCC alarm, INT0 interrupt, ULPWU or DSWDT), the device will exit Deep Sleep mode and perform a Power-on Reset (POR). When the device is released from Reset, code execution will resume at the device's Reset vector. 3.6.2 I/O PINS DURING DEEP SLEEP During Deep Sleep, the general purpose I/O pins will retain their previous states. Pins that are configured as inputs (TRIS bit set) prior to entry into Deep Sleep will remain high-impedance during Deep Sleep. Pins that are configured as outputs (TRIS bit clear) prior to entry into Deep Sleep will remain as output pins during Deep Sleep. While in this mode, they will drive the output level determined by their corresponding LAT bit at the time of entry into Deep Sleep. When the device wakes back up, the I/O pin behavior depends on the type of wake-up source. If the device wakes back up by an RTCC alarm, INT0 interrupt, DSWDT or ULPWU event, all I/O pins will continue to maintain their previous states, even after the device has finished the POR sequence and is executing application code again. Pins configured as inputs during Deep Sleep will remain high-impedance, and pins configured as outputs will continue to drive their previous value. After waking up, the TRIS and LAT registers will be reset, but the I/O pins will still maintain their previous states. If firmware modifies the TRIS and LAT values for the I/O pins, they will not immediately go to the newly configured states. Once the firmware clears the RELEASE bit (DSCONL<0>), the I/O pins will be "released". This causes the I/O pins to take the states configured by their respective TRIS and LAT bit values. If the Deep Sleep BOR (DSBOR) circuit is enabled, and VDD drops below the DSBOR and VDD rail POR thresholds, the I/O pins will be immediately released similar to clearing the RELEASE bit. All previous state information will be lost, including the general purpose DSGPR0 and DSGPR1 contents. See Section 3.6.5 "Deep Sleep Brown Out Reset (DSBOR)" for additional details about this scenario. If a MCLR Reset event occurs during Deep Sleep, the I/O pins will also be released automatically, but in this case, the DSGPR0 and DSGPR1 contents will remain valid. In all other Deep Sleep wake-up cases, application firmware needs to clear the RELEASE bit in order to reconfigure the I/O pins. 3.6.1 PREPARING FOR DEEP SLEEP Because VDDCORE could fall below the SRAM retention voltage while in Deep Sleep mode, SRAM data could be lost in Deep Sleep. Exiting Deep Sleep mode causes a POR; as a result, most Special Function Registers will reset to their default POR values. Applications needing to save a small amount of data throughout a Deep Sleep cycle can save the data to the general purpose DSGPR0 and DSGPR1 registers. The contents of these registers are preserved while the device is in Deep Sleep, and will remain valid throughout an entire Deep Sleep entry and wake-up sequence. (c) 2009 Microchip Technology Inc. DS39932C-page 49 PIC18F46J11 FAMILY 3.6.3 DEEP SLEEP WAKE-UP SOURCES 3.6.4 While in Deep Sleep mode, the device can be awakened by a MCLR, POR, RTCC, INT0 I/O pin interrupt, DSWDT or ULPWU event. After waking, the device performs a POR. When the device is released from Reset, code execution will begin at the device's Reset vector. The software can determine if the wake-up was caused from an exit from Deep Sleep mode by reading the DS bit (WDTCON<3>). If this bit is set, the POR was caused by a Deep Sleep exit. The DS bit must be manually cleared by the software. The software can determine the wake event source by reading the DSWAKEH and DSWAKEL registers. When the application firmware is done using the DSWAKEH and DSWAKEL status registers, individual bits do not need to be manually cleared before entering Deep Sleep again. When entering Deep Sleep mode, these registers are automatically cleared. DEEP SLEEP WATCHDOG TIMER (DSWDT) Deep Sleep has its own dedicated WDT (DSWDT) with a postscaler for time-outs of 2.1 ms to 25.7 days, configurable through the bits, DSWDTPS<3:0> (CONFIG3L<7:4>). The DSWDT can be clocked from either the INTRC or the T1OSC/T1CKI input. If the T1OSC/T1CKI source will be used with a crystal, the T1OSCEN bit in the T1CON register needs to be set prior to entering Deep Sleep. The reference clock source is configured through the DSWDTOSC bit (CONFIG3L<0>). DSWDT is enabled through the DSWDTEN bit (CONFIG3L<3>). Entering Deep Sleep mode automatically clears the DSWDT. See Section 25.0 "Special Features of the CPU" for more information. 3.6.5 3.6.3.1 Wake-up Event Considerations DEEP SLEEP BROWN OUT RESET (DSBOR) Deep Sleep wake-up events are only monitored while the processor is fully in Deep Sleep mode. If a wake-up event occurs before Deep Sleep mode is entered, the event status will not be reflected in the DSWAKE registers. If the wake-up source asserts prior to entering Deep Sleep, the CPU may go to the interrupt vector (if the wake source has an interrupt bit and the interrupt is fully enabled), and may abort the Deep Sleep entry sequence by executing past the SLEEP instruction. In this case, a wake-up event handler should be placed after the SLEEP instruction to process the event and re-attempt entry into Deep Sleep if desired. When the device is in Deep Sleep with more than one wake-up source simultaneously enabled, only the first wake-up source to assert will be detected and logged in the DSWAKEH/DSWAKEL status registers. The Deep Sleep module contains a dedicated Deep Sleep BOR (DSBOR) circuit. This circuit may be optionally enabled through the DSBOREN Configuration bit (CONFIG3L<2>). The DSBOR circuit monitors the VDD supply rail voltage. The behavior of the DSBOR circuit is described in Section 4.4 "Brown-out Reset (BOR)". 3.6.6 RTCC PERIPHERAL AND DEEP SLEEP The RTCC can operate uninterrupted during Deep Sleep mode. It can wake the device from Deep Sleep by configuring an alarm. The RTCC clock source is configured with the RTCOSC bit (CONFIG3L<1>). The available reference clock sources are the INTRC and T1OSC/T1CKI. If the INTRC is used, the RTCC accuracy will directly depend on the INTRC tolerance. For more information on configuring the RTCC peripheral, see Section 16.0 "Real-Time Clock and Calendar (RTCC)". DS39932C-page 50 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 3.6.7 TYPICAL DEEP SLEEP SEQUENCE 3.6.8 DEEP SLEEP FAULT DETECTION This section gives the typical sequence for using the Deep Sleep mode. Optional steps are indicated, and additional information is given in notes at the end of the procedure. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Enable DSWDT (optional).(1) Configure DSWDT clock source (optional).(2) Enable DSBOR (optional).(1) Enable RTCC (optional).(3) Configure the RTCC peripheral (optional).(3) Configure the ULPWU peripheral (optional).(4) Enable the INT0 Interrupt (optional).(4) Context save SRAM data by writing to the DSGPR0 and DSGPR1 registers (optional). Set the REGSLP bit (WDTCON<7>) and clear the IDLEN bit (OSCCON<7>). If using an RTCC alarm for wake-up, wait until the RTCSYNC (RTCCFG<4>) bit is clear. Enter Deep Sleep mode by setting the DSEN bit (DSCONH<7>) and issuing a SLEEP instruction. These two instructions must be executed back to back. Once a wake-up event occurs, the device will perform a POR reset sequence. Code execution resumes at the device's Reset vector. Determine if the device exited Deep Sleep by reading the Deep Sleep bit, DS (WDTCON<3>). This bit will be set if there was an exit from Deep Sleep mode. Clear the Deep Sleep bit, DS (WDTCON<3>). Determine the wake-up source by reading the DSWAKEH and DSWAKEL registers. Determine if a DSBOR event occurred during Deep Sleep mode by reading the DSBOR bit (DSCONL<1>). Read the DSGPR0 and DSGPR1 context save registers (optional). Clear the RELEASE bit (DSCONL<0>). If during Deep Sleep the device is subjected to unusual operating conditions, such as an Electrostatic Discharge (ESD) event, it is possible that the internal circuit states used by the Deep Sleep module could become corrupted. If this were to happen, the device may exhibit unexpected behavior, such as a failure to wake back up. In order to prevent this type of scenario from occurring, the Deep Sleep module includes automatic self-monitoring capability. During Deep Sleep, critical internal nodes are continuously monitored in order to detect possible Fault conditions (which would not ordinarily occur). If a Fault condition is detected, the circuitry will set the DSFLT status bit (DSWAKEL<7>) and automatically wake the microcontroller from Deep Sleep, causing a POR Reset. During Deep Sleep, the Fault detection circuitry is always enabled and does not require any specific configuration prior to entering Deep Sleep. 12. 13. 14. 15. 16. 17. 18. Note 1: DSWDT and DSBOR are enabled through the devices' Configuration bits. For more information, see Section 25.1 "Configuration Bits". 2: The DSWDT and RTCC clock sources are selected through the devices' Configuration bits. For more information, see Section 25.1 "Configuration Bits". 3: For more information, see Section 16.0 "Real-Time Clock and Calendar (RTCC)". 4: For more information on configuring this peripheral, see Section 3.7 "Ultra Low-Power Wake-up". (c) 2009 Microchip Technology Inc. DS39932C-page 51 PIC18F46J11 FAMILY 3.6.9 DEEP SLEEP MODE REGISTERS provided in Deep Sleep mode registers are Register 3-1 through Register 3-6. REGISTER 3-1: R/W-0 DSEN(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh) U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 (Reserved) R/W-0 DSULPEN R/W-0 RTCWDIS bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DSEN: Deep Sleep Enable bit(1) 1 = Deep Sleep mode is entered on a SLEEP command 0 = Sleep mode is entered on a SLEEP command Unimplemented: Read as `0' (Reserved): Always write `0' to this bit DSULPEN: Ultra Low-Power Wake-up Module Enable bit 1 = ULPWU module is enabled in Deep Sleep 0 = ULPWU module is disabled in Deep Sleep RTCWDIS: RTCC Wake-up Disable bit 1 = Wake-up from RTCC is disabled 0 = Wake-up from RTCC is enabled In order to enter Deep Sleep, Sleep must be executed immediately after setting DSEN. bit 6-3 bit 2 bit 1 bit 0 Note 1: REGISTER 3-2: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2 DSCONL: DEEP SLEEP CONTROL LOW BYTE REGISTER (BANKED F4Ch) U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 ULPWDIS R/W-0(1) DSBOR R/W-0(1) RELEASE bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' ULPWDIS: Ultra Low-Power Wake-up Disable bit 1 = ULPWU wake-up source is disabled 0 = ULPWU wake-up source is enabled (must also set DSULPEN = 1) DSBOR: Deep Sleep BOR Event Status bit 1 = DSBOREN was enabled and VDD dropped below the DSBOR arming voltage during Deep Sleep, but did not fall below VDSBOR 0 = DSBOREN was disabled or VDD did not drop below the DSBOR arming voltage during Deep Sleep RELEASE: I/O Pin State Release bit Upon waking from Deep Sleep, the I/O pins maintain their previous states. Clearing this bit will release the I/O pins and allow their respective TRIS and LAT bits to control their states. This is the value when VDD is initially applied. bit 1 bit 0 Note 1: DS39932C-page 52 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 3-3: DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0 (BANKED F4Eh) R/W-xxxx(1) Deep Sleep Persistent General Purpose bits bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 0 Deep Sleep Persistent General Purpose bits Contents are retained even in Deep Sleep mode. All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep Sleep, or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS. Note 1: REGISTER 3-4: DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1 (BANKED F4Fh) R/W-xxxx(1) Deep Sleep Persistent General Purpose bits bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 0 Deep Sleep Persistent General Purpose bits Contents are retained even in Deep Sleep mode. All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep Sleep, or, the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS. Note 1: (c) 2009 Microchip Technology Inc. DS39932C-page 53 PIC18F46J11 FAMILY REGISTER 3-5: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DSWAKEH: DEEP SLEEP WAKE HIGH BYTE REGISTER (BANKED F4Bh) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DSINT0 bit 0 Unimplemented: Read as `0' DSINT0: Interrupt-on-Change bit 1 = Interrupt-on-change was asserted during Deep Sleep 0 = Interrupt-on-change was not asserted during Deep Sleep REGISTER 3-6: R/W-0 DSFLT bit 7 Legend: R = Readable bit -n = Value at POR bit 7 DSWAKEL: DEEP SLEEP WAKE LOW BYTE REGISTER (BANKED F4Ah) U-0 -- R/W-0 DSULP(2) R/W-0 DSWDT(2) R/W-0 DSRTC(2) R/W-0 DSMCLR(2) U-0 -- R/W-1 DSPOR bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DSFLT: Deep Sleep Fault Detected bit 1 = A Deep Sleep Fault was detected during Deep Sleep 0 = A Deep Sleep fault was not detected during Deep Sleep Unimplemented: Read as `0' DSULP: Ultra Low-Power Wake-up status bit(2) 1 = An Ultra Low-Power Wake-up event occurred during Deep Sleep 0 = An Ultra Low-Power Wake-up event did not occur during Deep Sleep DSWDT: Deep Sleep Watchdog Timer Time-out bit(2) 1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep 0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep DSRTC: Real-Time Clock and Calendar Alarm bit(2) 1 = The Real-Time Clock/Calendar triggered an alarm during Deep Sleep 0 = The Real-Time Clock /Calendar did not trigger an alarm during Deep Sleep DSMCLR: MCLR Event bit(2) 1 = The MCLR pin was asserted during Deep Sleep 0 = The MCLR pin was not asserted during Deep Sleep Unimplemented: Read as `0' DSPOR: Power-on Reset Event bit 1 = The VDD supply POR circuit was active and a POR event was detected(1) 0 = The VDD supply POR circuit was not active, or was active, but did not detect a POR event Unlike the other bits in this register, this bit can be set outside of Deep Sleep. If multiple wake-up triggers are fired around the same time, only the first wake-up event triggered will have its wake-up status bit set. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: DS39932C-page 54 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 3.7 Ultra Low-Power Wake-up See Example 3-1 for initializing the ULPWU module. Note: For module-related bit definitions, see the WDTCON register in Section 25.2 "Watchdog Timer (WDT)" and the DSWAKEL register (Register 3-6). The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt without excess current consumption. Follow these steps to use this feature: 1. 2. Configure a remappable output pin to output the ULPOUT signal. Map an INTx interrupt-on-change input function to the same pin as used for the ULPOUT output function. Alternatively, in step 1, configure ULPOUT to output onto a PORTB interrupt-on-change pin. Charge the capacitor on RA0 by configuring the RA0 pin to an output and setting it to `1'. Enable interrupt for the corresponding pin selected in step 2. Stop charging the capacitor by configuring RA0 as an input. Discharge the capacitor by setting the ULPEN and ULPSINK bits in the WDTCON register. Configure Sleep mode. Enter Sleep mode. A series resistor between RA0 and the external capacitor provides overcurrent protection for the RA0/AN0/C1INA/ULPWU/RP0 pin and can allow for software calibration of the time-out (see Figure 3-9). FIGURE 3-9: RA0 SERIAL RESISTOR R1 3. 4. 5. 6. 7. 8. C1 When the voltage on RA0 drops below VIL, an interrupt will be generated, which will cause the device to wake-up and execute the next instruction. This feature provides a low-power technique for periodically waking up the device from Sleep mode. The time-out is dependent on the discharge time of the RC circuit on RA0. When the ULPWU module causes the device to wake-up from Sleep mode, the WDTCON A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired interrupt delay. This technique will compensate for the affects of temperature, voltage and component accuracy. The peripheral can also be configured as a simple Programmable Low-Voltage Detect (LVD) or temperature sensor. Note: For more information, refer to AN879, "Using the Microchip Ultra Low-Power Wake-up Module" application note (DS00879). (c) 2009 Microchip Technology Inc. DS39932C-page 55 PIC18F46J11 FAMILY EXAMPLE 3-1: ULTRA LOW-POWER WAKE-UP INITIALIZATION //********************************************************************************* //Configure a remappable output pin with interrupt capability //for ULPWU function (RP21 => RD4/INT1 in this example) //********************************************************************************* RPOR21 = 13;// ULPWU function mapped to RP21/RD4 RPINR1 = 21;// INT1 mapped to RP21 (RD4) //*************************** //Charge the capacitor on RA0 //*************************** TRISAbits.TRISA0 = 0; PORTAbits.RA0 = 1; for(i = 0; i < 10000; i++) Nop(); //********************************** //Stop Charging the capacitor on RA0 //********************************** TRISAbits.TRISA0 = 1; //***************************************** //Enable the Ultra Low Power Wakeup module //and allow capacitor discharge //***************************************** WDTCONbits.ULPEN = 1; WDTCONbits.ULPSINK = 1; //****************************************** //For Sleep, Enable Interrupt for ULPW. //****************************************** INTCON3bits.INT1IF = 0; INTCON3bits.INT1IE = 1; //******************** //Configure Sleep Mode //******************** //For Sleep OSCCONbits.IDLEN = 0; //For Deep Sleep OSCCONbits.IDLEN = 0;// enable deep sleep DSCONHbits.DSEN = 1;// Note: must be set just before executing Sleep(); //**************** //Enter Sleep Mode //**************** Sleep(); // for sleep, execution will resume here // for deep sleep, execution will restart at reset vector (use WDTCONbits.DS to detect) DS39932C-page 56 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 4.0 RESET The PIC18F46J11 family of devices differentiates among various kinds of Reset: a) b) c) d) e) f) g) h) i) j) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Configuration Mismatch (CM) Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset Deep Sleep Reset Figure 4-1 provides a simplified block diagram of the on-chip Reset circuit. 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be set by the event and must be cleared by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 4.7 "Reset State of Registers". The ECON register also has a control bit for setting interrupt priority (IPEN). Interrupt priority is discussed in Section 8.0 "Interrupts". This section discusses Resets generated by MCLR, POR and BOR, and covers the operation of the various start-up timers. For information on WDT Resets, see Section 25.2 "Watchdog Timer (WDT)". For Stack Reset events, see Section 5.1.4.4 "Stack Full and Underflow Resets" and for Deep Sleep mode, see Section 3.6 "Deep Sleep Mode". FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Configuration Word Mismatch Stack Full/Underflow Reset Stack Pointer External Reset MCLR ( )_IDLE Deep Sleep Reset Sleep WDT Time-out VDD Rise Detect VDD Brown-out Reset(1) S POR Pulse PWRT 32 ms INTRC PWRT 66 ms R Q Chip_Reset 11-Bit Ripple Counter Note 1: The Brown-out Reset is not available in PIC18LF2XJ11 and PIC18LF4XJ11 devices. (c) 2009 Microchip Technology Inc. DS39932C-page 57 PIC18F46J11 FAMILY REGISTER 4-1: R/W-0 IPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RCON: RESET CONTROL REGISTER (ACCESS FD0h) U-0 -- R/W-1 CM R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) Unimplemented: Read as `0' CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration Mismatch Reset occurs) RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. 2: If the on-chip voltage regulator is disabled, BOR remains `0' at all times. See Section 4.4.1 "Detecting BOR" for more information. 3: Brown-out Reset is said to have occurred when BOR is `0' and POR is `1' (assuming that POR was set to `1' by software immediately after a Power-on Reset). DS39932C-page 58 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 4.2 Master Clear (MCLR) The Master Clear Reset (MCLR) pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path, which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. Additionally, if any I/O pins had been configured as outputs during Deep Sleep, these pins will be tri-stated and the device will no longer be held in Deep Sleep. Once the VDD voltage recovers back above the VDSBOR threshold, and once the core voltage regulator achieves a VDDCORE voltage above VBOR, the device will begin executing code again normally, but the DS bit in the WDTCON register will not be set. The device behavior will be similar to hard cycling all power to the device. On "LF" devices, the VDDCORE BOR circuit is always disabled because the internal core voltage regulator is disabled. Instead of monitoring VDDCORE, PIC18LF devices in this family can use the VDD BOR circuit to monitor VDD excursions below the VDSBOR threshold. The VDD BOR circuit can be disabled by setting the DSBOREN bit = 0. The VDD BOR circuit is enabled when DSBOREN = 1 on "LF" devices, or on "F" devices while in Deep Sleep with DSBOREN = 1. When enabled, the VDD BOR circuit is extremely low power (typ. 200 nA) during normal operation above ~2.3V on VDD. If VDD drops below this DSBOR arming level when the VDD BOR circuit is enabled, the device may begin to consume additional current (typ. 50 A) as internal features of the circuit power up. The higher current is necessary to achieve more accurate sensing of the VDD level. However, the device will not enter Reset until VDD falls below the VDSBOR threshold. 4.3 Power-on Reset (POR) A POR condition is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 k to 10 k) to VDD. This will eliminate external RC components usually needed to create a POR delay. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to `0' whenever a Power-on Reset occurs; it does not change for any other Reset event. POR is not reset to `1' by any hardware event. To capture multiple events, the user manually resets the bit to `1' in software following any POR. 4.4.1 DETECTING BOR 4.4 Brown-out Reset (BOR) "F" devices incorporate two types of BOR circuits: one which monitors VDDCORE and one which monitors VDD. Only one BOR circuit can be active at a time. When in normal Run mode, Idle or normal Sleep modes, the BOR circuit that monitors VDDCORE is active and will cause the device to be held in BOR if VDDCORE drops below VBOR (parameter D005). Once VDDCORE rises back above VBOR, the device will be held in Reset until the expiration of the Power-up Timer, with period, TPWRT (parameter 33). During Deep Sleep operation, the on-chip core voltage regulator is disabled and VDDCORE is allowed to drop to ground levels. If the Deep Sleep BOR circuit is enabled by the DSBOREN Configuration bit (CONFIG3L<2> = 1), it will monitor VDD. If VDD drops below the VDSBOR threshold, the device will be held in a Reset state similar to POR. All registers will be set back to their POR Reset values and the contents of the DSGPR0 and DSGPR1 holding registers will be lost. The BOR bit always resets to `0' on any VDDCORE, BOR or POR event. This makes it difficult to determine if a Brown-out Reset event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to `1' in software immediately after any Power-on Reset event. If BOR is `0' while POR is `1', it can be reliably assumed that a Brown-out Reset event has occurred. If the voltage regulator is disabled (LF devices), the VDDCORE BOR functionality is disabled. In this case, the BOR bit cannot be used to determine a Brown-out Reset event. The BOR bit is still cleared by a Power-on Reset event. (c) 2009 Microchip Technology Inc. DS39932C-page 59 PIC18F46J11 FAMILY 4.5 Configuration Mismatch (CM) 4.6 Power-up Timer (PWRT) The Configuration Mismatch (CM) Reset is designed to detect, and attempt to recover from, random memory corrupting events. These include Electrostatic Discharge (ESD) events, which can cause widespread single bit changes throughout the device and result in catastrophic failure. In PIC18FXXJ Flash devices, the device Configuration registers (located in the configuration memory space) are continuously monitored during operation by comparing their values to complimentary shadow registers. If a mismatch is detected between the two sets of registers, a CM Reset automatically occurs. These events are captured by the CM bit (RCON<5>). The state of the bit is set to `0' whenever a CM event occurs; it does not change for any other Reset event. A CM Reset behaves similarly to a MCLR, RESET instruction, WDT time-out or Stack Event Resets. As with all hard and power Reset events, the device Configuration Words are reloaded from the Flash Configuration Words in program memory as the device restarts. PIC18F46J11 family devices incorporate an on-chip PWRT to help regulate the POR process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F46J11 family devices is a 5-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 32 x 32 s = 1 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip-to-chip due to temperature and process variation. See DC parameter 33 (TPWRT) for details. 4.6.1 TIME-OUT SEQUENCE The PWRT time-out is invoked after the POR pulse has cleared. The total time-out will vary based on the status of the PWRT. Figure 4-2, Figure 4-3, Figure 4-4 and Figure 4-5 all depict time-out sequences on power-up with the PWRT. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the PWRT will expire. Bringing MCLR high will begin execution immediately if a clock source is available (Figure 4-4). This is useful for testing purposes, or to synchronize more than one PIC18FXXXX device operating in parallel. FIGURE 4-2: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET DS39932C-page 60 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 4-5: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD MCLR 0V 1V INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET (c) 2009 Microchip Technology Inc. DS39932C-page 61 PIC18F46J11 FAMILY 4.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a "Reset state" depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register (CM, RI, TO, PD, POR and BOR) are set or cleared differently in different Reset situations, as indicated in Table 4-1. These bits are used in software to determine the nature of the Reset. Table 4-2 describes the Reset states for all of the Special Function Registers. These are categorized by POR and BOR, MCLR and WDT Resets, and WDT wake-ups. TABLE 4-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program Counter(1) 0000h 0000h 0000h 0000h 0000h 0000h RCON Register CM 1 u 1 0 u u RI 1 0 1 u u u TO 1 u 1 u 1 1 PD 1 u 1 u u 0 POR 0 u u u u u BOR 0 u 0 u u u STKPTR Register STKFUL STKUNF 0 u u u u u 0 u u u u u Condition Power-on Reset RESET instruction Brown-out Reset Configuration Mismatch Reset MCLR Reset during power-managed Run modes MCLR Reset during power-managed Idle modes and Sleep mode MCLR Reset during full-power execution Stack Full Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) Stack Underflow Error (not an actual Reset, STVREN = 0) WDT time-out during full-power or power-managed Run modes WDT time-out during power-managed Idle or Sleep modes Interrupt exit from power-managed modes 0000h 0000h 0000h 0000h 0000h PC + 2 u u u u u u u u u u u u u u u u 0 0 u u u u u 0 u u u u u u u u u u u u u 1 u u u u u u 1 1 u u PC + 2 u u u 0 u u u u Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). DS39932C-page 62 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, Brown-out Reset, Wake From Deep Sleep ---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 1111 1100 0000 N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx ---- 0000 N/A MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets ---0 0000 0000 0000 0000 0000 uu-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 1111 1100 0000 N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---- 0000 N/A Wake-up via WDT or Interrupt ---0 0000(1) uuuu uuuu(1) uuuu uuuu(1) uu-u uuuu(1) ---u uuuu uuuu uuuu PC + 2(2) --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(3) uuuu uuuu(3) uuuu uuuu(3) N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---- uuuu N/A Register Applicable Devices TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. (c) 2009 Microchip Technology Inc. DS39932C-page 63 PIC18F46J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep N/A N/A N/A N/A ---- xxxx xxxx xxxx ---x xxxx 0000 0000 xxxx xxxx 1111 1111 0110 q000 0001 1111 0001 1111 0-11 1100 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1qq- 0000 00-0 0001 0000 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu 0000 0000 uuuu uuuu 1111 1111 0110 q000 uuuu uuuu uuuu uuuu 0-qq qquu uuuu uuuu uuuu uuuu u0uu uuuu 0000 0000 1111 1111 -000 0000 uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0qq- 0000 00-0 0001 0000 0000 Wake-up via WDT or Interrupt Register Applicable Devices POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON CM1CON CM2CON RCON (4) PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0110 q00u uuuu uuuu uuuu uuuu u-qq qquu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uqq- uuuu uu-u uuuu uuuu uuuu TMR1H TMR1L T1CON TMR2 PR2 T2CON SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 ADRESH ADRESL ADCON0 ADCON1 WDTCON PSTR1CON ECCP1AS Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. DS39932C-page 64 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 00-0 0001 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 0-00 0000000 00xx 0000 0000 0000 0000 0000 0000 xxxx xxxx 0000 0010 0000 000x 0000 0000 0000 0000 0000 0000 0000 0010 ---- -----00 x001111 1111 0000 0000 0000 0000 1111 1111 000- 0000 000- 0000 1111 1111 0000 0000 0000 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 00-0 0001 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0-00 0000000 00xx 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0010 0000 000x 0000 0000 0000 0000 0000 0000 0000 0010 ---- -----00 u001111 1111 0000 0000 0000 0000 1111 1111 000- 0000 000- 0000 1111 1111 0000 0000 0000 0000 Wake-up via WDT or Interrupt Register Applicable Devices ECCP1DEL CCPR1H CCPR1L CCP1CON PSTR2CON ECCP2AS ECCP2DEL CCPR2H CCPR2L CCP2CON CTMUCONH CTMUCONL CTMUICON SPBRG1 RCREG1 TXREG1 TXSTA1 RCSTA1 SPBRG2 RCREG2 TXREG2 TXSTA2 EECON2 EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -----00 u00uuuu uuuu uuuu uuuu(3) uuuu uuuu uuuu uuuu uuu- uuuu(3) uuu- uuuu uuuu uuuu uuuu uuuu(3) uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. (c) 2009 Microchip Technology Inc. DS39932C-page 65 PIC18F46J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep 0000 000x 0000 0000 0000 0x00 0xxx xxxx 0xxx xxx 0000 0x00 ---- -111 1111 1111 1111 1111 1111 1111 111- 1111 0000 0000 0000 0000 xxxx xxxx xxxx xxxx ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx 0000 0000 0000 0000 0000 0000 00-- -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx 0000 0000 0100 0-00 0000 0000 0100 0-00 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets 0000 000x 0000 0000 0000 0x00 0uuu uuuu 0uuu uuuu uuuu uxuu ---- -111 1111 1111 1111 1111 1111 1111 111- 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu 0000 0000 0000 0000 0000 0000 uu-- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu 0000 0000 0100 0-00 0000 0000 0100 0-00 Wake-up via WDT or Interrupt Register Applicable Devices RCSTA2 OSCTUNE T1GCON RTCVALH RTCVALL T3GCON TRISE(5) TRISD TRISC TRISB TRISA ALRMCFG ALRMRPT ALRMVALH ALRMVALL LATE (5) (5) PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 uuuu uuuu uuuu uuuu uuuu uuuu 0uuu uuuu 0uuu uuuu uuuu uxuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu u-uu LATD(5) LATC LATB LATA DMACON1 DMACON2 HLVDCON PORTE (5) PORTD(5) PORTC PORTB PORTA SPBRGH1 BAUDCON1 SPBRGH2 BAUDCON2 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. DS39932C-page 66 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep xxxx xxxx xxxx xxxx 0000 -000 0000 0000 1111 1111 -000 0000 xxxx xxxx 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 ---- --11 -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 0000 0000 ---- 0000 0000 0000 ---- --00 0-00 0000 000- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu 1111 1111 -000 0000 uuuu uuuu 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 ---- --11 -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 0000 0000 ---- 0000 0000 0000 ---- --00 0-00 0000 000- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Wake-up via WDT or Interrupt Register Applicable Devices TMR3H TMR3L T3CON TMR4 PR4 T4CON SSP2BUF SSP2ADD SSP2MASK SSP2STAT SSP2CON1 SSP2CON2 CMSTAT PMADDRH PMADDRL PMDOUT1L PMDIN1H PMDIN1L TXADDRL TXADDRH RXADDRL RXADDRH DMABCL DMABCH PMCONH PMCONL PMMODEH PMMODEL PMDOUT2H PMDOUT2L PMDIN2H PMDIN2L (5) PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu ---- uuuu uuuu uuuu ---- --uu u-uu uuuu uuu- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PMDOUT1H(5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. (c) 2009 Microchip Technology Inc. DS39932C-page 67 PIC18F46J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep 0000 0000 0000 0000 00-- 0000 10-- 1111 0000 0000 00-0 0000 0000 0000 ---- --00 ---- --00 ---- --00 0-00 0000 0000 0000 0-00 0000 ---- -000 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---0 0000 ---0 0000 ---0 0000 ---0 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets 0000 0000 0000 0000 00-- 0000 10-- 1111 0000 0000 uu-u uuuu uuuu uuuu ---- --uu ---- --uu ---- --uu u-uu uuuu uuuu uuuu u-uu uuuu ---- -uuu ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---0 0000 ---0 0000 ---0 0000 ---0 0000 Wake-up via WDT or Interrupt Register Applicable Devices PMEH PMEL PMSTATH PMSTATL CVRCON(5) ANCON1 ANCON0 ODCON1 ODCON2 ODCON3 RTCCFG RTCCAL REFOCON PADCFG1 RPINR24 RPINR23 RPINR22 RPINR21 RPINR17 RPINR16 RPINR13 RPINR12 RPINR8 RPINR7 RPINR6 RPINR4 RPINR3 RPINR2 RPINR1 RPOR24 RPOR23 RPOR22 RPOR21 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 uuuu uuuu uuuu uuuu uu-- uuuu uu-- uuuu uuuu uuuu uu-u uuuu uuuu uuuu ---- --uu ---- --uu ---- --uu u-uu uuuu uuuu uuuu u-uu uuuu ---- -uuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. DS39932C-page 68 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 Wake-up via WDT or Interrupt Register Applicable Devices RPOR20 RPOR19 RPOR18 RPOR17 RPOR16 RPOR15 RPOR14 RPOR13 RPOR12 RPOR11 RPOR10 RPOR9 RPOR8 RPOR7 RPOR6 RPOR5 RPOR4 RPOR3 RPOR2 RPOR1 RPOR0 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F2XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 PIC18F4XJ11 ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. (c) 2009 Microchip Technology Inc. DS39932C-page 69 PIC18F46J11 FAMILY NOTES: DS39932C-page 70 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.0 MEMORY ORGANIZATION 5.1 Program Memory Organization There are two types of memory in PIC18 Flash microcontrollers: * Program Memory * Data RAM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. Section 6.0 "Flash Program Memory" provides additional information on the operation of the Flash program memory. PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address returns all `0's (a NOP instruction). The PIC18F46J11 family offers a range of on-chip Flash program memory sizes, from 16 Kbytes (up to 8,192 single-word instructions) to 64 Kbytes (32,768 single-word instructions). Figure 5-1 provides the program memory maps for individual family devices. FIGURE 5-1: MEMORY MAPS FOR PIC18F46J11 FAMILY DEVICES PC<20:0> 21 CALL, CALLW, RCALL, RETURN, RETFIE, RETLW, ADDULNK, SUBULNK Stack Level 1 * * * Stack Level 31 PIC18FX4J11 On-Chip Memory Config. Words PIC18FX5J50 On-Chip Memory PIC18FX6J11 On-Chip Memory 000000h 003FFFh Config. Words 007FFFh 00FFFFh Unimplemented Read as `0' Unimplemented Read as `0' Unimplemented Read as `0' 1FFFFFF Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. (c) 2009 Microchip Technology Inc. User Memory Space Config. Words DS39932C-page 71 PIC18F46J11 FAMILY 5.1.1 HARD MEMORY VECTORS 5.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the program counter returns on all device Resets; it is located at 0000h. PIC18 devices also have two interrupt vector addresses for handling high-priority and low-priority interrupts. The high-priority interrupt vector is located at 0008h and the low-priority interrupt vector at 0018h. Figure 5-2 provides their locations in relation to the program memory map. Because PIC18F46J11 family devices do not have persistent configuration memory, the top four words of on-chip program memory are reserved for configuration information. On Reset, the configuration information is copied into the Configuration registers. The Configuration Words are stored in their program memory location in numerical order, starting with the lower byte of CONFIG1 at the lowest address and ending with the upper byte of CONFIG4. Table 5-1 provides the actual addresses of the Flash Configuration Word for devices in the PIC18F46J11 family. Figure 5-2 displays their location in the memory map with other memory vectors. Additional details on the device Configuration Words are provided in Section 25.1 "Configuration Bits". FIGURE 5-2: HARD VECTOR AND CONFIGURATION WORD LOCATIONS FOR PIC18F46J11 FAMILY DEVICES 0000h 0008h 0018h TABLE 5-1: Reset Vector High-Priority Interrupt Vector Low-Priority Interrupt Vector FLASH CONFIGURATION WORD FOR PIC18F46J11 FAMILY DEVICES Program Memory (Kbytes) 16 32 64 Configuration Word Addresses 3FF8h to 3FFFh 7FF8h to 7FFFh FFF8h to FFFFh Device PIC18F24J11 PIC18F44J11 On-Chip Program Memory PIC18F25J11 PIC18F45J11 PIC18F26J11 PIC18F46J11 Flash Configuration Words (Top of Memory-7) (Top of Memory) Read as `0' 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure 5-1 for device-specific values). Shaded area represents unimplemented memory. Areas are not shown to scale. DS39932C-page 72 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.1.3 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes to PCL. Similarly, the upper 2 bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.1.6.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit (LSb) of PCL is fixed to a value of `0'. The PC increments by two to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer (SP), STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable, and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers (SFRs). Data can also be pushed to, or popped from, the stack using these registers. A CALL type instruction causes a push onto the stack. The Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack. The contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to `00000' after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of `00000'; this is only a Reset value. Status bits indicate if the stack is full, has overflowed or has underflowed. 5.1.4.1 Top-of-Stack Access 5.1.4 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction (and on ADDULNK and SUBULNK instructions if the extended instruction set is enabled). PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, holds the contents of the stack location pointed to by the STKPTR register (Figure 5-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt (and ADDULNK and SUBULNK instructions if the extended instruction set is enabled), the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user-defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. FIGURE 5-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> Top-of-Stack Registers TOSU 00h TOSH 1Ah TOSL 34h 11111 11110 11101 Stack Pointer STKPTR<4:0> 00010 Top-of-Stack 001A34h 000D58h 00011 00010 00001 00000 (c) 2009 Microchip Technology Inc. DS39932C-page 73 PIC18F46J11 FAMILY 5.1.4.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a Power-on Reset (POR). The action that takes place when the stack becomes full depends on the state of the Stack Overflow Reset Enable (STVREN) Configuration bit. Refer to Section 25.1 "Configuration Bits" for device Configuration bits' description. If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and the STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return zero to the PC and set the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. 5.1.4.3 PUSH and POP Instructions Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution is necessary. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. REGISTER 5-1: R/C-0 STKFUL(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 STKPTR: STACK POINTER REGISTER (ACCESS FFCh) R/C-0 U-0 -- R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown STKUNF(1) STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as `0' SP<4:0>: Stack Pointer Location bits Bits 7 and 6 are cleared by user software or by a POR. bit 6 bit 5 bit 4-0 Note 1: DS39932C-page 74 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.1.4.4 Stack Full and Underflow Resets 5.1.6 Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration register 1L. When STVREN is set, a full or underflow condition sets the appropriate STKFUL or STKUNF bit and then causes a device Reset. When STVREN is cleared, a full or underflow condition sets the appropriate STKFUL or STKUNF bit, but does not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a POR. LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures or look-up tables in program memory. For PIC18 devices, look-up tables can be implemented in two ways: * Computed GOTO * Table Reads 5.1.6.1 Computed GOTO 5.1.5 FAST REGISTER STACK (FRS) A Fast Register Stack (FRS) is provided for the STATUS, WREG and BSR registers to provide a "fast return" option for interrupts. This stack is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources push values into the Stack registers. The values in the registers are then loaded back into the working registers if the RETFIE, FAST instruction is used to return from the interrupt. If both low-priority and high-priority interrupts are enabled, the Stack registers cannot be used reliably to return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the Stack register values stored by the low-priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the FRS for returns from interrupt. If no interrupts are used, the FRS can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the FRS. Example 5-1 provides a source code example that uses the FRS during a subroutine call and return. A computed GOTO is accomplished by adding an offset to the PC. An example is shown in Example 5-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next executed instruction will be one of the RETLW nn instructions that returns the value `nn' to the calling function. The offset value (in WREG) specifies the number of bytes that the PC should advance and should be multiples of 2 (LSb = 0). In this method, only one byte may be stored in each instruction location; room on the return address stack is required. EXAMPLE 5-2: MOVF CALL nn00h ADDWF RETLW RETLW RETLW . . . COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh ORG TABLE 5.1.6.2 Table Reads EXAMPLE 5-1: CALL SUB1, FAST * * SUB1 * * RETURN FAST FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK A better method of storing data in program memory allows two bytes to be stored in each instruction location. Look-up table data may be stored two bytes per program word while programming. The Table Pointer (TBLPTR) specifies the byte address and the Table Latch (TABLAT) contains the data that is read from the program memory. Data is transferred from program memory one byte at a time. Table read operation is discussed further Section 6.1 "Table Reads and Table Writes". in ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK (c) 2009 Microchip Technology Inc. DS39932C-page 75 PIC18F46J11 FAMILY 5.2 5.2.1 PIC18 Instruction Cycle CLOCKING SCHEME 5.2.2 INSTRUCTION FLOW/PIPELINING The microcontroller clock input, whether from an internal or external source, is internally divided by `4' to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the PC is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4. The instruction is decoded and executed during the following Q1 through Q4. Figure 5-4 illustrates the clocks and instruction execution flow. An "Instruction Cycle" consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-3). A fetch cycle begins with the PC incrementing in Q1. In the execution cycle, the fetched instruction is latched into the IR in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 5-4: OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC mode) CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Internal Phase Clock PC PC + 2 PC + 4 Execute INST (PC - 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h 2. MOVWF PORTB 3. BRA SUB_1 4. BSF Fetch 1 PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 Note: All instructions are single-cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. DS39932C-page 76 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as 2 bytes or 4 bytes in program memory. The Least Significant Byte (LSB) of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read `0' (see Section 5.1.3 "Program Counter"). Figure 5-5 provides an example of how instruction words are stored in the program memory. The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-5 displays how the instruction, GOTO 0006h, is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 26.0 "Instruction Set Summary" provides further details of the instruction set. FIGURE 5-5: INSTRUCTIONS IN PROGRAM MEMORY Program Memory Byte Locations LSB = 1 LSB = 0 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h Instruction 1: Instruction 2: Instruction 3: MOVLW GOTO MOVFF 055h 0006h 123h, 456h 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h 5.2.4 TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has `1111' as its four Most Significant bits (MSbs); the other 12 bits are literal data, usually a data memory address. The use of `1111' in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence immediately after the first word, the data in the second word is accessed and used by the instruction sequence. If the first word is skipped for some reason, and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 5-4 illustrates how this works. Note: See Section 5.5 "Program Memory and the Extended Instruction Set" for information on two-word instructions in the extended instruction set. EXAMPLE 5-4: CASE 1: Object Code TWO-WORD INSTRUCTIONS Source Code TSTFSZ MOVFF ADDWF Source Code TSTFSZ MOVFF ADDWF REG1 REG1, REG2 REG3 ; is RAM location 0? ; Yes, execute this word ; 2nd word of instruction ; continue code REG1 REG1, REG2 REG3 ; is RAM location 0? ; No, skip this word ; Execute this word as a NOP ; continue code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 CASE 2: Object Code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 (c) 2009 Microchip Technology Inc. DS39932C-page 77 PIC18F46J11 FAMILY 5.3 Note: Data Memory Organization The operation of some aspects of data memory is changed when the PIC18 extended instruction set is enabled. See Section 5.6 "Data Memory and the Extended Instruction Set" for more information. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the 4 MSbs of a location's address; the instruction itself includes the 8 LSbs. Only the four lower bits of the BSR are implemented (BSR<3:0>). The upper four bits are unused; they will always read `0' and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory. The 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank's lower boundary. The relationship between the BSR's value and the bank division in data memory is illustrated in Figure 5-7. Since, up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h while the BSR is 0Fh, will end up resetting the PC. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return `0's. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 5-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each. The PIC18F46J11 family implements all available banks and provides 3.8 Kbytes of data memory available to the user. Figure 5-6 provides the data memory organization for the devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user's application. Any read of an unimplemented location will read as `0's. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this section. To ensure that commonly used registers (select SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to select SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 "Access Bank" provides a detailed description of the Access RAM. 5.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. DS39932C-page 78 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 5-6: BSR3:BSR0 00h = 0000 Bank 0 FFh 00h FFh 00h Bank 2 FFh 00h Bank 3 FFh 00h Bank 4 FFh 00h Bank 5 FFh 00h Bank 6 FFh 00h Bank 7 FFh 00h Bank 8 FFh 00h Bank 9 FFh 00h Bank 10 FFh 00h Bank 11 GPR FFh 00h FFh 00h Bank 13 FFh 00h GPR 8FFh 900h 9FFh A00h AFFh B00h BFFh C00h CFFh D00h GPR GPR DFFh E00h EBFh EC0h EFFh F00h F5Fh Access SFRs FFh Note 1: DATA MEMORY MAP FOR PIC18F46J11 FAMILY DEVICES Data Memory Map Access RAM GPR GPR 000h 05Fh 060h 0FFh 100h 1FFh 200h GPR 2FFh 300h GPR 3FFh 400h GPR, BDT 4FFh 500h GPR 5FFh 600h GPR 6FFh 700h GPR 7FFh 800h Access Bank 5Fh Access RAM High 60h (SFRs) FFh Access RAM Low 00h When a = 0: The BSR is ignored and the Access Bank is used. The first 96 bytes are general purpose RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the bank used by the instruction. = 0001 Bank 1 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 GPR = 1010 GPR = 1011 = 1100 Bank 12 GPR = 1101 = 1110 = 1111 Bank 14 Bank 15 C0h Non-Access SFR(1) FFh 00h Non-Access SFR(1) 60h FFFh Addresses EC0h through F5Fh are not part of the Access Bank. Either the BANKED or the MOVFF instruction should be used to access these SFRs. (c) 2009 Microchip Technology Inc. DS39932C-page 79 PIC18F46J11 FAMILY FIGURE 5-7: 7 0 0 0 USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 0 0 0 1 0 0 000h 100h Bank 1 200h 300h Bank 2 Data Memory 00h Bank 0 FFh 00h FFh 00h FFh 00h 7 1 1 1 1 From Opcode(2) 1 1 1 1 1 1 1 1 0 1 Bank Select(2) Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. 5.3.2 ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of memory (60h-FFh) in Bank 15. The lower half is known as the Access RAM and is composed of GPRs. The upper half is where the device's SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 5-6). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the `a' parameter in the instruction). When `a' is equal to `1', the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When `a' is `0', however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. Using this "forced" addressing allows the instruction to operate on a data address in a single cycle without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 5.6.3 "Mapping the Access Bank in Indexed Literal Offset Mode". 5.3.3 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upward toward the bottom of the SFR area. GPRs are not initialized by a POR and are unchanged on all other Resets. DS39932C-page 80 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.3.4 SPECIAL FUNCTION REGISTERS The SFRs are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F40h to FFFh). Table 5-2, Table 5-3 and Table 5-4 provide a list of these registers. The SFRs can be classified into two sets: those associated with the "core" device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are described in their corresponding chapters, while the ALU's STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as `0's Note: The SFRs located between EC0h and F5Fh are not part of the Access Bank. Either banked instructions (using BSR) or the MOVFF instruction should be used to access these locations. When programming in MPLAB(R) C18, the compiler will automatically use the appropriate addressing mode. TABLE 5-2: Address FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEEh FEDh FECh FEBh FEAh FE9h FE8h FE7h FE6h FE5h FE4h FE3h FE2h FE1h FE0h ACCESS BANK SPECIAL FUNCTION REGISTER MAP Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL Address FDFh FDEh FDDh FDCh FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h (1) (1) Name INDF2 (1) Address FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h Name PSTR1CON ECCP1AS ECCP1DEL CCPR1H CCPR1L CCP1CON PSTR2CON ECCP2AS ECCP2DEL CCPR2H CCPR2L CCP2CON CTMUCONH CTMUCONL CTMUICON SPBRG1 RCREG1 TXREG1 TXSTA1 RCSTA1 SPBRG2 RCREG2 TXREG2 TXSTA2 EECON2 EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 Address F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h F84h F83h F82h F81h F80h Name IPR1 PIR1 PIE1 RCSTA2 OSCTUNE T1GCON RTCVALH RTCVALL T3GCON TRISE TRISD TRISC TRISB TRISA ALRMCFG ALRMRPT ALRMVALH ALRMVALL LATE (2) (2) Address F7Fh F7Eh F7Dh F7Ch F7Bh F7Ah F79h F78h F77h F76h F75h F74h F73h F72h F71h F70h F6Fh F6Eh F6Dh F6Ch F6Bh F6Ah F69h F68h F67h F66h F65h F64h F63h F62h F61h F60h Name SPBRGH1 BAUDCON1 SPBRGH2 BAUDCON2 TMR3H TMR3L T3CON TMR4 PR4 T4CON SSP2BUF SSP2ADD(3) SSP2STAT SSP2CON1 SSP2CON2 CMSTAT PMADDRH(2,4) PMADDRL(2,4) PMDIN1H(2) PMDIN1L(2) TXADDRL TXADDRH RXADDRL RXADDRH DMABCL DMABCH --(5) --(5) --(5) --(5) --(5) --(5) POSTINC2(1) POSTDEC2(1) PREINC2(1) PLUSW2(1) FSR2H FSR2L STATUS TMR0H TMR0L T0CON --(5) OSCCON CM1CON CM2CON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSP1BUF SSP1ADD(3) SSP1STAT SSP1CON1 SSP1CON2 ADRESH ADRESL ADCON0 ADCON1 WDTCON TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0(1) POSTINC0(1) POSTDEC0 PREINC0 PLUSW0 FSR0L WREG INDF1(1) POSTINC1 PREINC1 PLUSW1 FSR1L BSR FSR1H POSTDEC1(1) (1) (1) (1) LATD (1) LATC LATB LATA DMACON1 --(5) DMACON2 HLVDCON PORTE (2) (2) FSR0H FC6h FC5h FC4h FC3h FC2h FC1h FC0h PORTD PORTC PORTB PORTA Note 1: 2: 3: 4: 5: This is not a physical register. This register is not available on 28-pin devices. SSPxADD and SSPxMSK share the same address. PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address. PMADDRx is used in Master modes and PMDOUTx is used in Slave modes. Reserved: Do not write to this location. (c) 2009 Microchip Technology Inc. DS39932C-page 81 PIC18F46J11 FAMILY TABLE 5-3: Address F5Fh F5Eh F5Dh F5Ch F5Bh F5Ah F59h F58h F57h F56h F55h F54h F53h F52h F51h F50h F4Fh F4Eh F4Dh F4Ch F4Bh F4Ah F49h F48h F47h F46h F45h F44h F43h F42h F41h F40h NON-ACCESS BANK SPECIAL FUNCTION REGISTER MAP Name Address F3Fh F3Eh F3Dh F3Ch F3Bh F3Ah F39h F38h F37h F36h F35h F34h F33h F32h F31h F30h F2Fh F2Eh F2Dh F2Ch F2Bh F2Ah F29h F28h F27h F26h F25h F24h F23h F22h F21h F20h Name RTCCFG RTCCAL REFOCON PADCFG1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Address F1Fh F1Eh F1Dh F1Ch F1Bh F1Ah F19h F18h F17h F16h F15h F14h F13h F12h F11h F10h F0Fh F0Eh F0Dh F0Ch F0Bh F0Ah F09h F08h F07h F06h F05h F04h F03h F02h F01h F00h Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Address EFFh EFEh EFDh EFCh EFBh EFAh EF9h EF8h EF7h EF6h EF5h EF4h EF3h EF2h EF1h EF0h EEFh EEEh EEDh EECh EEBh EEAh EE9h EE8h EE7h EE6h EE5h EE4h EE3h EE2h EE1h EE0h Name PPSCON RPINR24 RPINR23 RPINR22 RPINR21 -- -- -- RPINR17 RPINR16 -- -- -- -- -- -- -- RPINR8 RPINR7 RPINR6 -- RPINR4 RPINR3 RPINR2 RPINR1 RPINR0 -- -- -- -- -- -- Address EDFh EDEh EDDh EDCh EDBh EDAh ED9h ED8h ED7h ED6h ED5h ED4h ED3h ED2h ED1h ED0h ECFh ECEh ECDh ECCh ECBh ECAh EC9h EC8h EC7h EC6h EC5h EC4h EC3h EC2h EC1h EC0h Name -- RPOR24(1) RPOR23(1) RPOR22(1) RPOR21(1) RPOR20(1) RPOR19(1) RPOR18 RPOR17 RPOR16 RPOR15 RPOR14 RPOR13 RPOR12 RPOR11 RPOR10 RPOR9 RPOR8 RPOR7 RPOR6 RPOR5 RPOR4 RPOR3 RPOR2 RPOR1 RPOR0 -- -- -- -- -- -- PMCONH PMCONL PMMODEH PMMODEL PMDOUT2H PMDOUT2L PMDIN2H PMDIN2L PMEH PMEL PMSTATH PMSTATL CVRCON TCLKCON -- -- DSGPR1(2) DSGPR0(2) DSCONH(2) DSCONL(2) DSWAKEH(2) DSWAKEL(2) ANCON1 ANCON0 -- -- -- -- -- ODCON1 ODCON2 ODCON3 Note 1: 2: This register is not available on 28-pin devices. Deep Sleep registers are not available on LF devices. DS39932C-page 82 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.3.4.1 Context Defined SFRs There are several registers that share the same address in the SFR space. The register's definition and usage depends on the operating mode of its associated peripheral. These registers are: * SSPxADD and SSPxMSK: These are two separate hardware registers, accessed through a single SFR address. The operating mode of the MSSP modules determines which register is being accessed. See Section 18.5.3.4 "7-Bit Address Masking Mode" for additional details. * PMADDRH/L and PMDOUT2H/L: In this case, these named buffer pairs are actually the same physical registers. The Parallel Master Port (PMP) module's operating mode determines what function the registers take on. See Section 10.1.2 "Data Registers" for additional details. TABLE 5-4: File Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 Legend: Note 1: 2: 3: 4: 5: 6: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on Page: Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 63, 75 0000 0000 63, 73 0000 0000 63, 73 Top-of-Stack High Byte (TOS<15:8>) Top-of-Stack Low Byte (TOS<7:0>) STKFUL -- STKUNF -- -- bit 21(1) SP4 SP3 SP2 SP1 SP0 Holding Register for PC<20:16> 00-0 0000 63, 74 ---0 0000 63, 73 0000 0000 63, 73 0000 0000 63, 73 Holding Register for PC<15:8> PC Low Byte (PC<7:0>) -- -- bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2IP PEIE/GIEL INTEDG0 INT1IP TMR0IE INTEDG1 INT3IE INT0IE INTEDG2 INT2IE RBIE INTEDG3 INT1IE TMR0IF TMR0IP INT3IF INT0IF INT3IP INT2IF RBIF RBIP INT1IF --00 0000 63, 106 0000 0000 63, 106 0000 0000 63, 106 0000 0000 63, 106 xxxx xxxx 63, 63 xxxx xxxx 63, 107 0000 000x 63, 111 1111 1111 63, 112 1100 0000 63, 113 N/A N/A N/A N/A N/A 63, 91 63, 92 63, 92 63, 92 63, 92 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value of FSR0 offset by W -- Working Register Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value of FSR1 offset by W -- -- -- Indirect Data Memory Address Pointer 0 High Byte Indirect Data Memory Address Pointer 0 Low Byte ---- xxxx 63, 91 xxxx xxxx 63, 91 xxxx xxxx 63, 75 N/A N/A N/A N/A N/A 63, 91 63, 92 63, 92 63, 92 63, 92 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Bit 21 of the PC is only available in Serial Programming (SP) modes. Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. See Section 18.5.3.2 "Address Masking Modes" for details. These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as `0'. Reset values are shown for 44-pin devices. The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module's operating mode. See Section 10.1.2 "Data Registers" for more information. (c) 2009 Microchip Technology Inc. DS39932C-page 83 PIC18F46J11 FAMILY TABLE 5-4: File Name FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON CM1CON CM2CON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSP1BUF SSP1ADD SSP1MSK(4) SSP1STAT SSP1CON1 SSP1CON2 ADRESH ADRESL ADCON0 ADCON1 WDTCON PSTR1CON ECCP1AS ECCP1DEL CCPR1H CCPR1L CCP1CON Legend: Note 1: 2: 3: 4: 5: 6: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED) Bit 7 -- -- Bit 6 -- -- Bit 5 -- -- Bit 4 -- -- Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on Page: Indirect Data Memory Address Pointer 1 High Byte Bank Select Register ---- xxxx 63, 91 xxxx xxxx 63, 91 ---- 0000 63, 78 N/A N/A N/A N/A N/A 63, 91 64, 92 64, 92 64, 92 64, 92 Indirect Data Memory Address Pointer 1 Low Byte Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR2 offset by W -- -- -- -- -- -- -- N Indirect Data Memory Address Pointer 2 High Byte OV Z DC C Indirect Data Memory Address Pointer 2 Low Byte Timer0 Register High Byte Timer0 Register Low Byte TMR0ON IDLEN CON CON IPEN T08BIT IRCF2 COE COE -- T0CS IRCF1 CPOL CPOL CM T0SE IRCF0 EVPOL1 EVPOL1 RI PSA OSTS(2) EVPOL0 EVPOL0 TO T0PS2 -- CREF CREF PD T0PS1 SCS1 CCH1 CCH1 POR T0PS0 SCS0 CCH0 CCH0 BOR ---- xxxx 64, 91 xxxx xxxx 64, 91 ---x xxxx 64, 89 0000 0000 xxxx xxxx 64 64 1111 1111 64, 191 0110 q-00 64, 38 0001 1111 64, 356 0001 1111 64, 356 0-11 1100 64, 123 xxxx xxxx xxxx xxxx 64 64 64 64 64 64 Timer1 Register High Byte Timer1 Register Low Byte TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON Timer2 Register Timer2 Period Register -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 MSSP1 Receive Buffer/Transmit Register MSSP1 Address Register (I2CTM Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) MSK7 SMP WCOL GCEN GCEN MSK6 CKE SSPOV ACKSTAT ACKSTAT MSK5 D/A SSPEN ACKDT MSK4 P CKP ACKEN MSK3 S SSPM3 RCEN ADMSK3(4) MSK2 R/W SSPM2 PEN ADMSK2(4) MSK1 UA SSPM1 RSEN ADMSK1(4) MSK0 BF SSPM0 SEN SEN 0000 0000 64, 195 0000 0000 1111 1111 xxxx xxxx 0000 0000 T2CKPS0 -000 0000 64, 207 1111 1111 64, 289 0000 0000 64, 286 0000 0000 64, 287 0000 0000 64, 288 xxxx xxxx xxxx xxxx 64 64 ADMSK5(4) ADMSK4(4) A/D Result Register High Byte A/D Result Register Low Byte VCFG1 ADFM REGSLP CMPL1 P1RSEN VCFG0 ADCAL LVDSTAT CMPL0 P1DC6 CHS3 ACQT2 ULPLVL -- P1DC5 CHS2 ACQT1 -- STRSYNC P1DC4 CHS1 ACQT0 DS STRD PSS1AC1 P1DC3 CHS0 ADCS2 ULPEN STRC PSS1AC0 P1DC2 GO/DONE ADCS1 ULPSINK STRB PSS1BD1 P1DC1 ADON ADCS0 SWDTEN STRA P1DC0 0000 0000 64, 345 0000 0000 64, 346 1xx- 0000 64, 400 00-0 0001 64, 261 64 65 65 65 65 0000 0000 xxxx xxxx xxxx xxxx ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 Capture/Compare/PWM Register 1 HIgh Byte Capture/Compare/PWM Register 1 Low Byte P1M1 P1M0 DC1B1 DC1B0 PSS1BD0 0000 0000 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Bit 21 of the PC is only available in Serial Programming (SP) modes. Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. See Section 18.5.3.2 "Address Masking Modes" for details. These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as `0'. Reset values are shown for 44-pin devices. The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module's operating mode. See Section 10.1.2 "Data Registers" for more information. DS39932C-page 84 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 5-4: File Name PSTR2CON ECCP2AS ECCP2DEL CCPR2H CCPR2L CCP2CON CTMUCONH CTMUCONL CTMUICON SPBRG1 RCREG1 TXREG1 TXSTA1 RCSTA1 SPBRG2 RCREG2 TXREG2 TXSTA2 EECON2 EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 RCSTA2 OSCTUNE T1GCON RTCVALH RTCVALL T3GCON TRISE TRISD TRISC TRISB TRISA ALRMCFG Legend: Note 1: 2: 3: 4: 5: 6: EUSART2 Receive Register EUSART2 Transmit Register CSRC -- SSP2IP SSP2IF SSP2IE OSCFIP OSCFIF OSCFIE PMPIP(5) PMPIF(5) PMPIE(5) SPEN INTSRC TMR1GE TX9 -- BCL2IP BCL2IF BCL2IE CM2IP CM2IF CM2IE ADIP ADIF ADIE RX9 PLLEN T1GPOL TXEN WPROG RC2IP RC2IF RC2IE CM1IP CM1IF CM1IE RC1IP RC1IF RC1IE SREN TUN5 T1GTM SYNC FREE TX2IP TX2IF TX2IE -- -- -- TX1IP TX1IF TX1IE CREN TUN4 T1GSPM SENDB WRERR TMR4IP TMR4IF TMR4IE BCL1IP BCL1IF BCL1IE SSP1IP SSP1IF SSP1IE ADDEN TUN3 T1GGO/ T1DONE BRGH WREN CTMUIP CTMUIF CTMUIE LVDIP LVDIF LVDIE CCP1IP CCP1IF CCP1IE FERR TUN2 T1GVAL TRMT WR TMR3GIP TMR3GIF TMR3GIE TMR3IP TMR3IF TMR3IE TMR2IP TMR2IF TMR2IE OERR TUN1 T1GSS1 TX9D -- RTCCIP RTCCIF RTCCIE CCP2IP CCP2IF CCP2IE TMR1IP TMR1IF TMR1IE RX9D TUN0 T1GSS0 Program Memory Control Register 2 (not a physical register) REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED) Bit 7 CMPL1 P2RSEN Bit 6 CMPL0 P2DC6 Bit 5 -- P2DC5 Bit 4 STRSYNC P2DC4 Bit 3 STRD PSS2AC1 P2DC3 Bit 2 STRC PSS2AC0 P2DC2 Bit 1 STRB PSS2BD1 P2DC1 Bit 0 STRA P2DC0 Value on POR, BOR Details on Page: 00-0 0001 65, 261 65 65 65 65 65 65 65 65 65 65 65 0000 0000 xxxx xxxx xxxx xxxx ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 Capture/Compare/PWM Register 2 High Byte Capture/Compare/PWM Register 2 Low Byte P2M1 CTMUEN EDG2POL ITRIM5 P2M0 -- ITRIM4 DC2B1 CTMUSIDL ITRIM3 DC2B0 TGEN EDG1POL ITRIM2 PSS2BD0 0000 0000 CCP2M3 EDGEN EDG1SEL1 ITRIM1 CCP2M2 EDGSEQEN EDG1SEL0 ITRIM0 CCP2M1 IDISSEN EDG2STAT IRNG1 CCP2M0 -- IRNG0 0000 0000 0-00 0000000 0000 0000 0000 0000 0000 xxxx xxxx EDG2SEL1 EDG2SEL0 EDG1STAT 0000 0000 EUSART1 Baud Rate Generator Register Low Byte EUSART1 Receive Register EUSART1 Transmit Register CSRC SPEN TX9 RX9 TXEN SREN SYNC CREN SENDB ADDEN BRGH FERR TRMT OERR TX9D RX9D 0000 0010 65, 322 0000 000x 65, 323 0000 0000 0000 0000 0000 0000 ---- ---65 65 65 65 EUSART2 Baud Rate Generator Register Low Byte 0000 0010 65, 322 --00 x00- 65, 99 1111 1111 65, 122 0000 0000 65, 116 0000 0000 65, 119 111- 1111 65, 121 000- 0000 65, 115 000- 0000 65, 118 1111 1111 65, 120 0000 0000 65, 114 0000 0000 65, 117 0000 000x 66, 323 0000 0000 66, 36 0000 0x00 66, 196 0xxx xxxx 0xxx xxxx 66 66 RTCC Value Register Window High Byte, Based on RTCPTR<1:0> RTCC Value Register Window Low Byte, Based on RTCPTR<1:0> TMR3GE -- TRISD7 TRISC7 TRISB7 TRISA7 ALRMEN T3GPOL -- TRISD6 TRISC6 TRISB6 TRISA6 CHIME T3GTM -- TRISD5 TRISC5 TRISB5 TRISA5 AMASK3 T3GSPM -- TRISD4 TRISC4 TRISB4 -- AMASK2 T3GGO/ T3DONE -- TRISD3 TRISC3 TRISB3 TRISA3 AMASK1 T3GVAL TRISE2 TRISD2 TRISC2 TRISB2 TRISA2 AMASK0 T3GSS1 TRISE1 TRISD1 TRISC1 TRISB1 TRISA1 T3GSS0 TRISE0 TRISD0 TRISC0 TRISB0 TRISA0 0000 0x00 66, 210 ---- -111 1111 1111 1111 1111 1111 1111 111- 1111 66 66 66 66 66 ALRMPTR1 ALRMPTR0 0000 0000 66, 225 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Bit 21 of the PC is only available in Serial Programming (SP) modes. Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. See Section 18.5.3.2 "Address Masking Modes" for details. These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as `0'. Reset values are shown for 44-pin devices. The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module's operating mode. See Section 10.1.2 "Data Registers" for more information. (c) 2009 Microchip Technology Inc. DS39932C-page 85 PIC18F46J11 FAMILY TABLE 5-4: File Name ALRMRPT ALRMVALH ALRMVALL LATE LATD LATC LATB LATA DMACON1 DMATXBUF DMACON2 HLVDCON PORTE PORTD PORTC PORTB PORTA SPBRGH1 BAUDCON1 SPBRGH2 BAUDCON2 TMR3H TMR3L T3CON TMR4 PR4 T4CON SSP2BUF SSP2ADD/ SSP2MSK(4) SSP2STAT SSP2CON1 SSP2CON2 CMSTAT PMADDRH/ PMDOUT1H(5) PMADDRL/ PMDOUT1L(5) PMDIN1H(5) PMDIN1L(5) TXADDRL Legend: Note 1: 2: 3: 4: 5: 6: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED) Bit 7 ARPT7 Bit 6 ARPT6 Bit 5 ARPT5 Bit 4 ARPT4 Bit 3 ARPT3 Bit 2 ARPT2 Bit 1 ARPT1 Bit 0 ARPT0 Value on POR, BOR Details on Page: 0000 0000 66, 226 xxxx xxxx xxxx xxxx 66 66 66 66 66 66 66 66 66 66 66 66 66 66 66 66 67 67 67 67 67 Alarm Value Register Window High Byte, Based on ALRMPTR<1:0> Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0> -- LATD7 LATC7 LATB7 LATA7 SSCON1 DLYCYC3 VDIRMAG RDPU RD7 RC7 RB7 RA7 ABDOVF ABDOVF -- LATD6 LATC6 LATB6 LATA6 SSCON0 DLYCYC2 BGVST REPU RD6 RC6 RB6 RA6 RCIDL RCIDL -- LATD5 LATC5 LATB5 LATA5 TXINC DLYCYC1 IRVST -- RD5 RC5 RB5 RA5 RXDTP RXDTP -- LATD4 LATC4 LATB4 -- RXINC DLYCYC0 HLVDEN -- RD4 RC4 RB4 -- TXCKP TXCKP -- LATD3 LATC3 LATB3 LATA3 DUPLEX1 INTLVL3 HLVDL3 -- RD3 RC4 RB3 RA3 BRG16 BRG16 LATE2 LATD2 LATC2 LATB2 LATA2 DUPLEX0 INTLVL2 HLVDL2 RE2 RD2 RC2 RB2 RA2 -- -- LATE1 LATD1 LATC1 LATB1 LATA1 DLYINTEN INTLVL1 HLVDL1 RE1 RD1 RC1 RB1 RA1 WUE WUE LATE0 LATD0 LATC0 LATB0 LATA0 DMAEN INTLVL0 HLVDL0 RE0 RD0 RC0 RB0 RA0 ABDEN ABDEN ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx xxxx xxxx 0000 0000 00-- -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 66, 278 0000 0000 66, 279 SPI DMA Transmit Buffer EUSART1 Baud Rate Generator Register High Byte EUSART2 Baud Rate Generator Register High Byte Timer3 Register High Byte Timer3 Register Low Byte TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 -- T3SYNC RD16 TMR3ON Timer4 Register Timer4 Period Register -- T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 MSSP2 Receive Buffer/Transmit Register MSSP2 Address Register (I2CTM Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) MSK7 SMP WCOL GCEN GCEN -- -- MSK6 CKE SSPOV ACKSTAT ACKSTAT -- CS1 MSK5 D/A SSPEN ACKDT -- MSK4 P CKP ACKEN -- MSK3 S SSPM3 RCEN ADMSK3(4) -- MSK2 R/W SSPM2 PEN ADMSK2(4) -- MSK1 UA SSPM1 RSEN ADMSK1(4) COUT2 MSK0 BF SSPM0 SEN SEN COUT1 0100 0-00 66, 324 0100 0-00 66, 324 0000 -000 67, 209 0000 0000 1111 1111 xxxx xxxx T4CKPS0 -000 0000 67, 219 0000 0000 67, 289 0000 0000 67, 289 1111 1111 67, 267 0000 0000 67, 287 0000 0000 67, 288 ---- --11 67, 357 -000 0000 67, 173 0000 0000 67, 173 0000 0000 67, 173 0000 0000 67, 173 0000 0000 0000 0000 xxxx xxxx 67 67 67 ADMSK5(4) ADMSK4(4) Parallel Master Port Address High Byte Parallel Port Out Data High Byte (Buffer 1) Parallel Master Port Address Low Byte Parallel Port Out Data Low Byte (Buffer 0) Parallel Port In Data High Byte (Buffer 1) Parallel Port In Data Low Byte (Buffer 0) SPI DMA Transit Data Pointer Low Byte x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Bit 21 of the PC is only available in Serial Programming (SP) modes. Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. See Section 18.5.3.2 "Address Masking Modes" for details. These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as `0'. Reset values are shown for 44-pin devices. The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module's operating mode. See Section 10.1.2 "Data Registers" for more information. DS39932C-page 86 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 5-4: File Name TXADDRH RXADDRL RXADDRH DMABCL DMABCH PMCONH(5) PMCONL(5) PMMODEH(5) PMMODEL(5) PMDOUT2H(5) PMDOUT2L(5) PMDIN2H(5) PMDIN2L(5) PMEH(5) PMEL(5) PMSTATH(5) PMSTATL(5) CVRCON(5) TCLKCON DSGPR1 DSGPR0 DSCONH DSCONL DSWAKEH DSWAKEL ANCON1 ANCON0 ODCON1 ODCON2 ODCON3 RTCCFG RTCCAL REFOCON PADCFG1 PPSCON RPINR24 RPINR23 RPINR22 RPINR21 RPINR17 RPINR16 RPINR13 Legend: Note 1: 2: 3: 4: 5: 6: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED) Bit 7 -- -- -- PMPEN CSF1 BUSY WAITB1 Bit 6 -- -- -- -- CSF0 IRQM1 WAITB0 Bit 5 -- -- -- PSIDL ALP IRQM0 WAITM3 Bit 4 -- -- -- ADRMUX1 -- INCM1 WAITM2 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ---- xxxx xxxx xxxx SPI DMA Receive Data Pointer High Byte -- ADRMUX0 CS1P INCM0 WAITM1 -- PTBEEN BEP MODE16 WAITM0 SPI DMA Receive Data Pointer High Byte PTWREN WRSP MODE1 WAITE1 PTRDEN RDSP MODE0 WAITE0 ---- xxxx xxxx xxxx ---- --xx Details on Page: 67 67 67 67 67 SPI DMA Transit Data Pointer High Byte SPI DMA Receive Data Pointer Low Byte SPI DMA Byte Count Low Byte 0-00 0000 67, 166 000- 0000 67, 167 0000 0000 67, 168 0000 0000 67, 169 0000 0000 0000 0000 0000 0000 0000 0000 67 67 67 67 Parallel Port Out Data High Byte (Buffer 3) Parallel Port Out Data Low Byte (Buffer 2) Parallel Port In Data High Byte (Buffer 3) Parallel Port In Data Low Byte (Buffer 2) PTEN15 PTEN7 IBF OBE CVREN -- PTEN14 PTEN6 IBOV OBUF CVROE -- PTEN13 PTEN5 -- -- CVRR -- PTEN12 PTEN4 -- -- CVRSS T1RUN PTEN11 PTEN3 IB3F OB3E CVR3 -- PTEN10 PTEN2 IB2F OB2E CVR2 -- PTEN9 PTEN1 IB1F OB1E CVR1 T3CCP2 PTEN8 PTEN0 IB0F OB0E CVR0 T3CCP1 0000 0000 67, 170 0000 0000 67, 170 00-- 0000 67, 171 10-- 1111 67, 171 0000 0000 67, 364 ---0 --00 xxxx xxxx xxxx xxxx 197 53 53 52 52 54 54 Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) DSEN -- -- DSFLT VBGEN PCFG7(5) -- -- -- RTCEN CAL7 ROON -- -- -- -- -- -- -- -- -- -- -- -- -- r PCFG6(5) -- -- -- -- CAL6 -- -- -- -- -- -- -- -- -- -- -- -- -- DSULP -- PCFG5(5) -- -- -- RTCWREN CAL5 ROSSLP -- -- -- -- -- -- -- -- -- -- -- -- DSWDT PCFG12 PCFG4 -- -- -- RTCSYNC CAL4 ROSEL -- -- -- -- -- DSRTC PCFG11 PCFG3 -- -- -- HALFSEC CAL3 RODIV3 -- -- (Reserved) ULPWDIS -- DSMCLR PCFG10 PCFG2 -- -- -- RTCOE CAL2 RODIV2 -- DSULPEN DSBOR -- -- PCFG9 PCFG1 ECCP20D U2OD SPI2OD RTCPTR1 CAL1 RODIV1 -- RTCWDIS 0--- -000 RELEASE ---- -000 DSINT0 DSPOR PCFG8 PCFG0 U1OD SPI1OD CAL0 RODIV0 PMPTTL IOLOCK ---- ---0 0-00 00-1 00-0 0000 67, 347 0000 0000 67, 347 ---- --00 67, 127 ---- --00 67, 128 0000 0000 67, 224 0-00 0000 67, 39 ---- -000 67, 128 ---- ---0 149 ---1 1111 68, 154 ---1 1111 68, 154 ---1 1111 68, 154 ---1 1111 68, 153 ---1 1111 68, 153 ---1 1111 153 ---1 1111 68, 152 ECCP10D ---- --00 67, 127 RTCPTR0 0-00 0000 67, 223 RTSECSEL1 RTSECSEL0 Input Function FLT0 to Input Pin Mapping Bits Input Function SS2 to Input Pin Mapping Bits Input Function SCK2 to Input Pin Mapping Bits Input Function SDI2 to Input Pin Mapping Bits Input Function CK2 to Input Pin Mapping Bits Input Function RX2DT2 to Input Pin Mapping Bits Input Function T3G to Input Pin Mapping Bits x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Bit 21 of the PC is only available in Serial Programming (SP) modes. Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. See Section 18.5.3.2 "Address Masking Modes" for details. These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as `0'. Reset values are shown for 44-pin devices. The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module's operating mode. See Section 10.1.2 "Data Registers" for more information. (c) 2009 Microchip Technology Inc. DS39932C-page 87 PIC18F46J11 FAMILY TABLE 5-4: File Name RPINR12 RPINR8 RPINR7 RPINR6 RPINR4 RPINR3 RPINR2 RPINR1 RPOR24(5) RPOR23(5) RPOR22(5) RPOR21(5) RPOR20(5) RPOR19(5) RPOR18 RPOR17 RPOR16 RPOR15 RPOR14 RPOR13 RPOR12 RPOR11 RPOR10 RPOR9 RPOR8 RPOR7 RPOR6 RPOR5 RPOR4 RPOR3 RPOR2 RPOR1 RPOR0 Legend: Note 1: 2: 3: 4: 5: 6: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED) Bit 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on Page: Input Function T1G to Input Pin Mapping Bits Input Function IC2 to Input Pin Mapping Bits Input Function IC1 to Input Pin Mapping Bits Input Function T3CKI to Input Pin Mapping Bits Input Function T0CKI to Input Pin Mapping Bits Input Function INT3 to Input Pin Mapping Bits Input Function INT2 to Input Pin Mapping Bits Input Function INT1 to Input Pin Mapping Bits Remappable Pin RP24 Output Signal Select Bits Remappable Pin RP23 Output Signal Select Bits Remappable Pin RP22 Output Signal Select Bits Remappable Pin RP21 Output Signal Select Bits Remappable Pin RP20 Output Signal Select Bits Remappable Pin RP19 Output Signal Select Bits Remappable Pin RP18 Output Signal Select Bits Remappable Pin RP17 Output Signal Select Bits Remappable Pin RP13 Output Signal Select Bits Remappable Pin RP13 Output Signal Select Bits Remappable Pin RP13 Output Signal Select Bits Remappable Pin RP13 Output Signal Select Bits Remappable Pin RP12 Output Signal Select Bits Remappable Pin RP11 Output Signal Select Bits Remappable Pin RP10 Output Signal Select Bits Remappable Pin RP9 Output Signal Select Bits Remappable Pin RP8 Output Signal Select Bits Remappable Pin RP7 Output Signal Select Bits Remappable Pin RP6 Output Signal Select Bits Remappable Pin RP5 Output Signal Select Bits Remappable Pin RP4 Output Signal Select Bits Remappable Pin RP3 Output Signal Select Bits Remappable Pin RP2 Output Signal Select Bits Remappable Pin RP1 Output Signal Select Bits Remappable Pin RP0 Output Signal Select Bits ---1 1111 69, 152 ---1 1111 68, 152 ---1 1111 68, 151 ---1 1111 68, 151 ---1 1111 68, 151 ---1 1111 68, 150 ---1 1111 68 ---1 1111 68, 150 ---0 0000 68, 163 ---0 0000 68, 163 ---0 0000 68, 162 ---0 0000 68, 162 ---0 0000 68, 162 ---0 0000 68, 161 ---0 0000 68, 161 ---0 0000 69, 161 ---0 0000 69, 160 ---0 0000 69, 160 ---0 0000 69, 160 ---0 0000 69, 159 ---0 0000 69, 159 ---0 0000 69, 159 ---0 0000 69, 158 ---0 0000 69, 158 ---0 0000 69, 157 ---0 0000 69, 157 ---0 0000 69, 157 ---0 0000 69, 156 ---0 0000 69, 156 ---0 0000 69, 156 ---0 0000 69, 155 ---0 0000 69, 155 ---0 0000 69, 155 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Bit 21 of the PC is only available in Serial Programming (SP) modes. Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. See Section 18.5.3.2 "Address Masking Modes" for details. These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as `0'. Reset values are shown for 44-pin devices. The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module's operating mode. See Section 10.1.2 "Data Registers" for more information. DS39932C-page 88 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.3.5 STATUS REGISTER The STATUS register in Register 5-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will set the Z bit but leave the other bits unchanged. The STATUS register then reads back as `000u u1uu'. It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions not affecting any Status bits, see the instruction set summary in Table 26-2 and Table 26-3. Note: The C and DC bits operate as a borrow and digit borrow bits respectively, in subtraction. REGISTER 5-2: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 STATUS REGISTER (ACCESS FD8h) U-0 -- U-0 -- R/W-x N R/W-x OV R/W-x Z R/W-x DC(1) R/W-x C(2) bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the MSb of the result occurred 0 = No carry-out from the MSb of the result occurred For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. bit 3 bit 2 bit 1 bit 0 Note 1: 2: (c) 2009 Microchip Technology Inc. DS39932C-page 89 PIC18F46J11 FAMILY 5.4 Note: Data Addressing Modes The execution of some instructions in the core PIC18 instruction set is changed when the PIC18 extended instruction set is enabled. See Section 5.6 "Data Memory and the Extended Instruction Set" for more information. Register File"), or a location in the Access Bank (Section 5.3.2 "Access Bank") as the data source for the instruction. The Access RAM bit, `a', determines how the address is interpreted. When `a' is `1', the contents of the BSR (Section 5.3.1 "Bank Select Register") are used with the address to determine the complete 12-bit address of the register. When `a' is `0', the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation's results is determined by the destination bit, `d'. When `d' is `1', the results are stored back in the source register, overwriting its original contents. When `d' is `0', the results are stored in the W register. Instructions without the `d' argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register. While the program memory can be addressed in only one way, through the PC, information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: * * * * Inherent Literal Direct Indirect An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in more detail in Section 5.6.1 "Indexed Addressing with Literal Offset". 5.4.3 INDIRECT ADDRESSING 5.4.1 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device, or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way, but require an additional explicit argument in the opcode. This is known as Literal Addressing mode, because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as SFRs, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code using loops, such as the example of clearing an entire RAM bank in Example 5-5. It also enables users to perform Indexed Addressing and other Stack Pointer operations for program memory in data memory. 5.4.2 DIRECT ADDRESSING EXAMPLE 5-5: Direct Addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byte-oriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit Literal Address as their LSB. This address specifies either a register address in one of the banks of data RAM (Section 5.3.3 "General Purpose HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 100h ; POSTINC0 ; Clear INDF ; register then ; inc pointer FSR0H, 1 ; All done with ; Bank1? NEXT ; NO, clear next ; YES, continue NEXT LFSR CLRF BTFSS BRA CONTINUE DS39932C-page 90 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.4.3.1 FSR Registers and the INDF Operand (INDF) At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Indirect Addressing is accomplished with a set of INDF operands, INDF0 through INDF2. These can be presumed to be "virtual" registers: they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction's target. The INDF operand is just a convenient way of using the pointer. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. FIGURE 5-8: INDIRECT ADDRESSING 000h Bank 0 100h Bank 1 200h Bank 2 Using an instruction with one of the Indirect Addressing registers as the operand.... ADDWF, INDF1, 1 ...uses the 12-bit address stored in the FSR pair associated with that register.... FSR1H:FSR1L 7 0 7 0 300h xxxx1111 11001100 Bank 3 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. E00h Bank 14 F00h FFFh Bank 15 Data Memory (c) 2009 Microchip Technology Inc. DS39932C-page 91 PIC18F46J11 FAMILY 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are "virtual" registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: * POSTDEC: accesses the FSR value, then automatically decrements it by `1' thereafter * POSTINC: accesses the FSR value, then automatically increments it by `1' thereafter * PREINC: increments the FSR value by `1', then uses it in the operation * PLUSW: adds the signed value of the W register (range of 127 to 128) to that of the FSR and uses the new value in the operation In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by the value in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses Indirect Addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 5.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 5.2.4 "Two-Word Instructions". 5.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. 5.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1, using INDF0 as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as the operand, will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to FSR2H:FSR2L. DS39932C-page 92 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.6.1 INDEXED ADDRESSING WITH LITERAL OFFSET 5.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair and its associated file operands. Under proper conditions, instructions that use the Access Bank, that is, most bit and byte-oriented instructions, can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: * The use of the Access Bank is forced (`a' = 0); and * The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing) or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte and bit-oriented instructions are not affected if they use the Access Bank (Access RAM bit is `1') or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled is provided in Figure 5-9. Those who desire to use byte or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 26.2.1 "Extended Instruction Syntax". (c) 2009 Microchip Technology Inc. DS39932C-page 93 PIC18F46J11 FAMILY FIGURE 5-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f 60h: The instruction executes in Direct Forced mode. `f' is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 060h are not available in this addressing mode. 000h 060h Bank 0 100h Bank 1 through Bank 14 00h 60h Valid range for `f' Access RAM Bank 15 F60h SFRs FFFh Data Memory FFh F00h When a = 0 and f 5Fh: The instruction executes in Indexed Literal Offset mode. `f' is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is: ADDWF [k], d where `k' is same as `f'. 000h Bank 0 060h 100h Bank 1 through Bank 14 FSR2H F00h Bank 15 F60h SFRs FFFh Data Memory FSR2L 001001da ffffffff When a = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). `f' is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 000h Bank 0 060h 100h Bank 1 through Bank 14 BSR 00000000 001001da ffffffff F00h Bank 15 F60h SFRs FFFh Data Memory DS39932C-page 94 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined "window" that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped to the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 5.3.2 "Access Bank"). Figure 5-10 provides an example of Access Bank remapping in this addressing mode. Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is `1') will continue to use Direct Addressing as before. Any Indirect or Indexed Addressing operation that explicitly uses any of the indirect file operands (including FSR2) will continue to operate as standard Indirect Addressing. Any instruction that uses the Access Bank, but includes a register address of greater than 05Fh, will use Direct Addressing and the normal Access Bank map. 5.6.4 BSR IN INDEXED LITERAL OFFSET MODE Although the Access Bank is remapped when the extended instruction set is enabled, the operation of the BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. FIGURE 5-10: Example Situation: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING 000h 05Fh Not Accessible Bank 0 100h 120h 17Fh 200h ADDWF f, d, a FSR2H:FSR2L = 120h Locations in the region from the FSR2 Pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). Special Function Registers at F60h through FFFh are mapped to 60h through FFh, as usual. Bank 0 addresses below 5Fh are not available in this mode. They can still be addressed by using the BSR. Window Bank 1 Bank 1 "Window" 00h 5Fh 60h Bank 2 through Bank 14 SFRs FFh Access Bank F00h Bank 15 F60h FFFh SFRs Data Memory (c) 2009 Microchip Technology Inc. DS39932C-page 95 PIC18F46J11 FAMILY NOTES: DS39932C-page 96 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on 1 byte at a time. A write to program memory is executed on blocks of 64 bytes at a time or 2 bytes at a time. Program memory is erased in blocks of 1024 bytes at a time. A bulk erase operation may not be issued from user code. Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD) * Table Write (TBLWT) The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into the data RAM space. Figure 6-1 illustrates the operation of a table read with program memory and data RAM. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 "Writing to Flash Program Memory". Figure 6-2 illustrates the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Program Memory Table Latch (8-bit) TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. (c) 2009 Microchip Technology Inc. DS39932C-page 97 PIC18F46J11 FAMILY FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 "Writing to Flash Program Memory". 6.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. Those are: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set, and cleared when the internal programming timer expires and the write operation is complete. Note: During normal operation, the WRERR is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. 6.2.1 EECON1 AND EECON2 REGISTERS The EECON1 register (Register 6-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. The WPROG bit, when set, will allow programming two bytes per word on the execution of the WR command. If this bit is cleared, the WR command will result in programming on a block of 64 bytes. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software. It is cleared in hardware at the completion of the write operation. DS39932C-page 98 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 6-1: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5 S = Settable bit (cannot be cleared in software) W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EECON1: EEPROM CONTROL REGISTER 1 (ACCESS FA6h) U-0 -- R/W-0 WPROG R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR U-0 -- bit 0 Unimplemented: Read as `0' WPROG: One Word-Wide Program bit 1 = Program 2 bytes on the next WR command 0 = Program 64 bytes on the next WR command FREE: Flash Erase Enable bit 1 = Perform an erase operation on the next WR command (cleared by hardware after completion of erase) 0 = Perform write only WRERR: Flash Program Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed WREN: Flash Program Write Enable bit 1 = Allows write cycles to Flash program memory 0 = Inhibits write cycles to Flash program memory WR: Write Control bit 1 = Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is complete Unimplemented: Read as `0' bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2009 Microchip Technology Inc. DS39932C-page 99 PIC18F46J11 FAMILY 6.2.2 TABLE LATCH REGISTER (TABLAT) 6.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped into the Special Function Register (SFR) space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. When a TBLWT is executed, the seven Least Significant bits (LSbs) of the Table Pointer register (TBLPTR<6:0>) determine which of the 64 program memory holding registers is written to. When the timed write to program memory begins (via the WR bit), the 12 Most Significant bits (MSbs) of the TBLPTR (TBLPTR<21:10>) determine which program memory block of 1024 bytes is written to. For more information, see Section 6.5 "Writing to Flash Program Memory". When an erase of program memory is executed, the 12 MSbs of the Table Pointer register point to the 1024-byte block that will be erased. The LSbs are ignored. Figure 6-3 illustrates the relevant boundaries of TBLPTR based on Flash program memory operations. 6.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device ID, the user ID and the Configuration bits. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. Table 6-1 provides these operations. These operations on the TBLPTR only affect the low-order 21 bits. TABLE 6-1: Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+* TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write FIGURE 6-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE: TBLPTR<20:10> TABLE WRITE: TBLPTR<20:6> TABLE READ: TBLPTR<21:0> DS39932C-page 100 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 6.3 Reading the Flash Program Memory TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The LSb of the address selects between the high and low bytes of the word. Figure 6-4 illustrates the interface between the internal program memory and the TABLAT. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register (IR) FETCH TBLRD TABLAT Read Register EXAMPLE 6-1: MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD READING A FLASH PROGRAM MEMORY WORD CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word TBLRD*+ MOVF MOVWF TBLRD*+ MOVF MOVWF TABLAT, W WORD_EVEN TABLAT, W WORD_ODD ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data (c) 2009 Microchip Technology Inc. DS39932C-page 101 PIC18F46J11 FAMILY 6.4 Erasing Flash Program Memory 6.4.1 The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program memory is erased. The Most Significant 12 bits of the TBLPTR<21:10> point to the block being erased. TBLPTR<9:0> are ignored. The EECON1 register commands the erase operation. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is: 1. 2. 3. 4. 5. 6. 7. 8. Load Table Pointer register with address of row being erased. Set the WREN and FREE bits (EECON1<2,4>) to enable the erase operation. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit; this will begin the erase cycle. The CPU will stall for the duration of the erase for TIE (see parameter D133B). Re-enable interrupts. EXAMPLE 6-2: ERASING FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, WREN FREE GIE ; load TBLPTR with the base ; address of the memory block ERASE_ROW BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Required Sequence WR GIE DS39932C-page 102 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 6.5 Writing to Flash Program Memory The programming block is 32 words or 64 bytes. Programming one word or 2 bytes at a time is also supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 64 times for each programming operation (if WPROG = 0). All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 64 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note 1: Unlike previous PIC(R) devices, devices of the PIC18F46J11 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten before a programming sequence. 2: To maintain the endurance of the program memory cells, each Flash byte should not be programmed more than once between erase operations. Before attempting to modify the contents of the target cell a second time, an erase of the target page, or a bulk erase of the entire memory, must be performed. FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 8 TBLPTR = xxxxx2 8 TBLPTR = xxxx3F 8 Holding Register Holding Register Holding Register Holding Register Program Memory 6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 1024 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer register with address being erased. Execute the erase procedure. Load Table Pointer register with address of first byte being written, minus 1. Write the 64 bytes into the holding registers with auto-increment. Set the WREN bit (EECON1<2>) to enable byte writes. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for the duration of the write for TIW (see parameter D133A). 13. Re-enable interrupts. 14. Repeat steps 6 through 13 until all 1024 bytes are written to program memory. 15. Verify the memory (table read). An example of the required code is provided in Example 6-3 on the following page. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the 64 bytes in the holding register. 8. 9. 10. 11. 12. (c) 2009 Microchip Technology Inc. DS39932C-page 103 PIC18F46J11 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF ERASE_BLOCK BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF MOVLW MOVWF RESTART_BUFFER MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF FILL_BUFFER ... WRITE_BUFFER MOVLW MOVWF WRITE_BYTE_TO_HREGS MOVFF MOVWF TBLWT+* D'64 COUNTER POSTINC0, WREG TABLAT ; number of bytes in holding register ; read the new data from I2C, SPI, ; PSP, USART, etc. D'64' COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE D'16' WRITE_COUNTER ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts ; Need to write 16 blocks of 64 to write ; one erase block of 1024 CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base address ; of the memory block, minus 1 ; point to buffer DECFSZ COUNTER BRA WRITE_BYTE_TO_HREGS PROGRAM_MEMORY BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, WREN GIE ; ; ; ; ; get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; ; ; ; write 0AAh start program (CPU stall) re-enable interrupts disable write to memory Required Sequence WR GIE WREN DECFSZ WRITE_COUNTER BRA RESTART_BUFFER ; done with one write cycle ; if not done replacing the erase block DS39932C-page 104 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 6.5.2 FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PRORAMMING). 3. The PIC18F46J11 family of devices has a feature that allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1. Load the Table Pointer register with the address of the data to be written. (It must be an even address.) Write the 2 bytes into the holding registers by performing table writes. (Do not post-increment on the second table write.) Set the WREN bit (EECON1<2>) to enable writes and the WPROG bit (EECON1<5>) to select Word Write mode. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit; this will begin the write cycle. The CPU will stall for the duration of the write for TIW (see parameter D133A). Re-enable interrupts. 4. 5. 6. 7. 8. 9. 2. EXAMPLE 6-4: SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF TBLWT*+ MOVLW MOVWF TBLWT* CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL DATA0 TABLAT DATA1 TABLAT ; LSB of word to be written ; Load TBLPTR with the base address ; The table pointer must be loaded with an even address ; MSB of word to be written ; The last table write must not increment the table pointer! The table pointer needs to point to the MSB before starting the write operation. PROGRAM_MEMORY BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF BCF EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EECON1, WPROG WREN GIE ; enable single word write ; enable write to memory ; disable interrupts ; write 55h ; ; ; ; ; write AAh start program (CPU stall) re-enable interrupts disable single word write disable write to memory Required Sequence WR GIE WPROG WREN (c) 2009 Microchip Technology Inc. DS39932C-page 105 PIC18F46J11 FAMILY 6.5.3 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. 6.6 6.5.4 UNEXPECTED TERMINATION OF WRITE OPERATION Flash Program Operation During Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and See Section 25.6 "Program Verification and Code Protection" for details on code protection of Flash program memory. TABLE 6-2: Name TBLPTRU REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Bit 7 -- Bit 6 -- Bit 5 bit 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: 63 63 63 63 INT0IE FREE RBIE WRERR TMR0IF WREN INT0IF WR RBIF -- 63 65 65 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT INTCON EECON2 EECON1 Program Memory Table Latch GIE/GIEH PEIE/GIEL TMR0IE -- -- WPROG Program Memory Control Register 2 (not a physical register) Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash program memory access. DS39932C-page 106 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 7.0 7.1 8 x 8 HARDWARE MULTIPLIER Introduction EXAMPLE 7-1: MOVF MULWF ARG1, W ARG2 8 x 8 UNSIGNED MULTIPLY ROUTINE ; ; ARG1 * ARG2 -> ; PRODH:PRODL All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier's operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. Table 7-1 provides a comparison of various hardware and software multiply operations, along with the savings in memory and execution time. EXAMPLE 7-2: MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF ARG1, W ARG2 ARG2, SB PRODH, F ARG2, W ARG1, SB PRODH, F 8 x 8 SIGNED MULTIPLY ROUTINE ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 7.2 Operation Example 7-1 provides the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 7-2 provides the instruction sequence for an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 7-1: Routine PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Multiply Method Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Program Memory (Words) 13 1 33 6 21 28 52 35 Cycles (Max) 69 1 91 6 242 28 254 40 Time @ 48 MHz 5.7 s 83.3 ns 7.5 s 500 ns 20.1 s 2.3 s 21.6 s 3.3 s @ 10 MHz 27.6 s 400 ns 36.4 s 2.4 s 96.8 s 11.2 s 102.6 s 16.0 s @ 4 MHz 69 s 1 s 91 s 6 s 242 s 28 s 254 s 40 s 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed (c) 2009 Microchip Technology Inc. DS39932C-page 107 PIC18F46J11 FAMILY Example 7-3 provides the instruction sequence for a 16 x 16 unsigned multiplication. Equation 7-1 provides the algorithm that is used. The 32-bit result is stored in four registers (RES<3:0>). EQUATION 7-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) + (-1 * ARG2H<7> * ARG1H:ARG1L * 216) + (-1 * ARG1H<7> * ARG2H:ARG2L * 216) RES3:RES0 EQUATION 7-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) = = RES3:RES0 = = EXAMPLE 7-4: MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF 16 x 16 SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; EXAMPLE 7-3: MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC 16 x 16 UNSIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L-> ; PRODH:PRODL ; ; ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1H * ARG2H-> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H-> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ARG1H * ARG2L -> PRODH:PRODL Add cross products ARG1H * ARG2L-> PRODH:PRODL Add cross products ; MOVF ADDWF MOVF ADDWFC CLRF ADDWFC BTFSS BRA MOVF SUBWF MOVF SUBWFB ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : Example 7-4 provides the sequence to do a 16 x 16 signed multiply. Equation 7-2 provides the algorithm used. The 32-bit result is stored in four registers (RES<3:0>). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done. ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; DS39932C-page 108 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 8.0 INTERRUPTS Devices of the PIC18F46J11 family have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. There are 13 registers, which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 0008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a low-priority interrupt. Low-priority interrupts are not processed while high-priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INTx pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. (c) 2009 Microchip Technology Inc. DS39932C-page 109 PIC18F46J11 FAMILY FIGURE 8-1: PIC18F46J11 FAMILY INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP IPEN IPEN PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> Wake-up if in Idle or Sleep modes PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> Interrupt to CPU Vector to Location 0008h GIE/GIEH TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP IPEN Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL DS39932C-page 110 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 8.1 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 8-1: R/W-0 GIE/GIEH bit 7 Legend: R = Readable bit -n = Value at POR bit 7 INTCON: INTERRUPT CONTROL REGISTER (ACCESS FF2h) R/W-0 R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF(1) bit 0 PEIE/GIEL W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 TCY will end the mismatch condition and allow the bit to be cleared. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2009 Microchip Technology Inc. DS39932C-page 111 PIC18F46J11 FAMILY REGISTER 8-2: R/W-1 RBPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown INTCON2: INTERRUPT CONTROL REGISTER 2 (ACCESS FF1h) R/W-1 R/W-1 INTEDG1 R/W-1 INTEDG2 R/W-1 INTEDG3 R/W-1 TMR0IP R/W-1 INT3IP R/W-1 RBIP bit 0 INTEDG0 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: DS39932C-page 112 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 8-3: R/W-1 INT2IP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown INTCON3: INTERRUPT CONTROL REGISTER 3 (ACCESS FF0h) R/W-1 INT1IP R/W-0 INT3IE R/W-0 INT2IE R/W-0 INT1IE R/W-0 INT3IF R/W-0 INT2IF R/W-0 INT1IF bit 0 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: (c) 2009 Microchip Technology Inc. DS39932C-page 113 PIC18F46J11 FAMILY 8.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 8-4: R/W-0 PMPIF(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ACCESS F9Eh) R/W-0 ADIF R-0 RC1IF R-0 TX1IF R/W-0 SSP1IF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PMPIF: Parallel Master Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART1 receive buffer is empty TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART1 transmit buffer is full SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow These bits are unimplemented on 28-pin devices. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39932C-page 114 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 8-5: R/W-0 OSCFIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ACCESS FA1h) R/W-0 CM2IF R/W-0 CM1IF U-0 -- R/W-0 BCL1IF R/W-0 LVDIF R/W-0 TMR3IF R/W-0 CCP2IF bit 0 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating CM2IF: Comparator 2 Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed CM1IF: Comparator 1 Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed Unimplemented: Read as `0' BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred LVDIF: High/Low-Voltage Detect (HLVD) Interrupt Flag bit 1 = A high/low-voltage condition occurred (must be cleared in software) 0 = An HLVD event has not occurred TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2009 Microchip Technology Inc. DS39932C-page 115 PIC18F46J11 FAMILY REGISTER 8-6: R/W-0 SSP2IF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (ACCESS FA4h) R/W-0 BCL2IF R-0 RC2IF R/W-0 TX2IF R/W-0 TMR4IF R/W-0 CTMUIF R/W-0 TMR3GIF R/W-0 RTCCIF bit 0 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred RC2IF: EUSART2 Receive Interrupt Flag bit 1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The EUSART2 receive buffer is empty TX2IF: EUSART2 Transmit Interrupt Flag bit 1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The EUSART2 transmit buffer is full TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred CTMUIF: Charge Time Measurement Unit Interrupt Flag bit 1 = A CTMU event has occurred (must be cleared in software) 0 = CTMU event has not occurred TMR3GIF: Timer3 Gate Event Interrupt Flag bit 1 = A Timer3 gate event completed (must be cleared in software) 0 = No Timer3 gate event completed RTCCIF: RTCC Interrupt Flag bit 1 = RTCC interrupt occurred (must be cleared in software) 0 = No RTCC interrupt occurred bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39932C-page 116 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 8.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 8-7: R/W-0 PMPIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 (1) PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ACCESS F9Dh) R/W-0 ADIE R/W-0 RC1IE R/W-0 TX1IE R/W-0 SSP1IE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PMPIE: Parallel Master Port Read/Write Interrupt Enable bit(1) 1 = Enables the PMP read/write interrupt 0 = Disables the PMP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enables the EUSART1 receive interrupt 0 = Disables the EUSART1 receive interrupt TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enables the EUSART1 transmit interrupt 0 = Disables the EUSART1 transmit interrupt SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt CCP1IE: ECCP1 Interrupt Enable bit 1 = Enables the ECCP1 interrupt 0 = Disables the ECCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt These bits are unimplemented on 28-pin devices. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2009 Microchip Technology Inc. DS39932C-page 117 PIC18F46J11 FAMILY REGISTER 8-8: R/W-0 OSCFIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ACCESS FA0h) R/W-0 CM2IE R/W-0 CM1IE U-0 -- R/W-0 BCL1IE R/W-0 LVDIE R/W-0 TMR3IE R/W-0 CCP2IE bit 0 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled CM2IE: Comparator 2 Interrupt Enable bit 1 = Enabled 0 = Disabled CM1IE: Comparator 1 Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module) 1 = Enabled 0 = Disabled LVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39932C-page 118 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 8-9: R/W-0 SSP2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 (ACCESS FA3h) R/W-0 BCL2IE R/W-0 RC2IE R/W-0 TX2IE R/W-0 TMR4IE R/W-0 CTMUIE R/W-0 TMR3GIE R/W-0 RTCCIE bit 0 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module) 1 = Enabled 0 = Disabled RC2IE: EUSART2 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled TX2IE: EUSART2 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enabled 0 = Disabled CTMUIE: Charge Time Measurement Unit (CTMU) Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2009 Microchip Technology Inc. DS39932C-page 119 PIC18F46J11 FAMILY 8.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 8-10: R/W-1 PMPIP(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 (ACCESS F9Fh) R/W-1 RC1IP R/W-1 TX1IP R/W-1 SSP1IP R/W-1 CCP1IP R/W-1 TMR2IP R/W-1 TMR1IP bit 0 ADIP R/W-1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PMPIP: Parallel Master Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority TX1IP: EUSART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 bit 3 SSP1IP: Master Synchronous Serial Port Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority These bits are unimplemented on 28-pin devices. bit 2 bit 1 bit 0 Note 1: DS39932C-page 120 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 8-11: R/W-1 OSCFIP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (ACCESS FA2h) R/W-1 CM1IP U-0 -- R/W-1 BCL1IP R/W-1 LVDIP R/W-1 TMR3IP R/W-1 CCP2IP bit 0 R/W-1 CM2IP OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority CM2IP: Comparator 2 Interrupt Priority bit 1 = High priority 0 = Low priority C12IP: Comparator 1 Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority LVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2009 Microchip Technology Inc. DS39932C-page 121 PIC18F46J11 FAMILY REGISTER 8-12: R/W-1 SSP2IP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 (ACCESS FA5h) R/W-1 RC2IP R/W-1 TX2IP R/W-1 TMR4IP R/W-1 CTMUIP R/W-1 TMR3GIP R/W-1 RTCCIP bit 0 R/W-1 BCL2IP SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module) 1 = High priority 0 = Low priority RC2IP: EUSART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority TX2IP: EUSART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority TMR4IE: TMR4 to PR4 Interrupt Priority bit 1 = High priority 0 = Low priority CTMUIP: Charge Time Measurement Unit (CTMU) Interrupt Priority bit 1 = High priority 0 = Low priority TMR3GIP: Timer3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority RTCCIP: RTCC Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39932C-page 122 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 8.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep mode. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 8-13: R/W-0 IPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 RCON: RESET CONTROL REGISTER (ACCESS FD0h) U-0 -- R/W-1 CM R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) Unimplemented: Read as `0' CM: Configuration Mismatch Flag bit For details on bit operation, see Register 4-1. RI: RESET Instruction Flag bit For details on bit operation, see Register 4-1. TO: Watchdog Timer Time-out Flag bit For details on bit operation, see Register 4-1. PD: Power-Down Detection Flag bit For details on bit operation, see Register 4-1. POR: Power-on Reset Status bit For details on bit operation, see Register 4-1. BOR: Brown-out Reset Status bit For details on bit operation, see Register 4-1. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2009 Microchip Technology Inc. DS39932C-page 123 PIC18F46J11 FAMILY 8.6 INTx Pin Interrupts External interrupts on the INT0, INT1, INT2 and INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the INTx pin, the corresponding flag bit and INTxIF are set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE. Flag bit, INTxIF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1, INT2 and INT3) can wake-up the processor from the power-managed modes if bit, INTxIE, was set prior to going into the power-managed modes. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1, INT2 and INT3 is determined by the value contained in the Interrupt Priority bits, INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and INT3IP (INTCON2<1>). There is no priority bit associated with INT0. It is always a high-priority interrupt source. pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 11.0 "Timer0 Module" for further details on the Timer0 module. 8.8 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>). 8.9 Context Saving During Interrupts 8.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack. If a fast return from interrupt is not used (see Section 5.3 "Data Memory Organization"), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 8-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 8-1: MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF SAVING STATUS, WREG AND BSR REGISTERS IN RAM ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP, STATUS ; Restore BSR ; Restore WREG ; Restore STATUS DS39932C-page 124 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 9.0 I/O PORTS 9.1 I/O Port Pin Capabilities Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (Data Direction register) * PORT register (reads the levels on the pins of the device) * LAT register (Data Latch) The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving. Figure 9-1 displays a simplified model of a generic I/O port, without the interfaces to other peripherals. When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than VDD input levels. 9.1.1 PIN OUTPUT DRIVE The output pin drive strengths vary for groups of pins intended to meet the needs for a variety of applications. PORTB and PORTC are designed to drive higher loads, such as LEDs. All other ports are designed for small loads, typically indication only. Table 9-1 summarizes the output capabilities. Refer to Section 28.0 "Electrical Characteristics" for more details. TABLE 9-1: Port PORTA PORTD PORTE PORTB PORTC OUTPUT DRIVE LEVELS Drive Description Minimum Intended for indication. Suitable for direct LED drive levels. FIGURE 9-1: GENERIC I/O PORT OPERATION High RD LAT Data Bus WR LAT or PORT 9.1.2 D CK Data Latch D Q Q I/O pin(1) INPUT PINS AND VOLTAGE CONSIDERATIONS WR TRIS CK TRIS Latch Input Buffer The voltage tolerance of pins used as device inputs is dependent on the pin's input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V; a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins should be avoided. Table 9-2 summarizes the input capabilities. Refer to Section 28.0 "Electrical Characteristics" for more details. RD TRIS TABLE 9-2: Q D EN EN INPUT VOLTAGE LEVELS Tolerated Input Description Port or Pin PORTA<7:0> PORTB<3:0> PORTC<2:0> RD PORT VDD Only VDD input levels tolerated. Note 1: I/O pins have diode protection to VDD and VSS. PORTE<2:0> PORTB<7:4> PORTC<7:3> PORTD<7:0> 5.5V Tolerates input levels above VDD, useful for most standard logic. (c) 2009 Microchip Technology Inc. DS39932C-page 125 PIC18F46J11 FAMILY 9.1.3 INTERFACING TO A 5V SYSTEM Though the VDDMAX of the PIC18F46J11 family is 3.6V, these devices are still capable of interfacing with 5V systems, even if the VIH of the target system is above 3.6V. This is accomplished by adding a pull-up resistor to the port pin (Figure 9-2), clearing the LAT bit for that pin and manipulating the corresponding TRIS bit (Figure 9-1) to either allow the line to be pulled high or to drive the pin low. Only port pins that are tolerant of voltages up to 5.5V can be used for this type of interface (refer to Section 9.1.2 "Input Pins and Voltage Considerations"). The open-drain option is implemented on port pins specifically associated with the data and clock outputs of the EUSARTs, the MSSP modules (in SPI mode) and the ECCP modules. It is selectively enabled by setting the open-drain control bit for the corresponding module in the ODCON registers (Register 9-1, Register 9-2 and Register 9-3). Their configuration is discussed in more detail with the individual port where these peripherals are multiplexed. When the open-drain option is required, the output pin must also be tied through an external pull-up resistor provided by the user to a higher voltage level, up to 5.5V (Figure 9-3). When a digital logic high signal is output, it is pulled up to the higher voltage level. FIGURE 9-2: +5V SYSTEM HARDWARE INTERFACE +5V +5V Device FIGURE 9-3: PIC18F46J11 USING THE OPEN-DRAIN OUTPUT (USART SHOWN AS EXAMPLE) +5V PIC18F46J11 3.3V RD7 VDD TXX (at logic `1') 5V EXAMPLE 9-1: BCF LATD, 7 ; ; ; ; ; COMMUNICATING WITH THE +5V SYSTEM set up LAT register so changing TRIS bit will drive line low send a 0 to the 5V system send a 1 to the 5V system 9.1.5 TTL INPUT BUFFER OPTION BCF BCF TRISD, 7 TRISD, 7 9.1.4 OPEN-DRAIN OUTPUTS The output pins for several peripherals are also equipped with a configurable open-drain output option. This allows the peripherals to communicate with external digital logic operating at a higher voltage level, without the use of level translators. Many of the digital I/O ports use Schmitt Trigger (ST) input buffers. While this form of buffering works well with many types of input, some applications may require TTL level signals to interface with external logic devices. This is particularly true for the Parallel Master Port (PMP), which is likely to be interfaced to TTL level logic or memory devices. The inputs for the PMP can be optionally configured for TTL buffers with the PMPTTL bit in the PADCFG1 register (Register 9-4). Setting this bit configures all data and control input pins for the PMP to use TTL buffers. By default, these PMP inputs use the port's ST buffers. DS39932C-page 126 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 9-1: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1 (BANKED F42h) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 ECCP2OD R/W-0 ECCP1OD bit 0 Unimplemented: Read as `0' ECCP2OD: ECCP2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled ECCP1OD: ECCP1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 0 REGISTER 9-2: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1 ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 (BANKED F41h) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 U2OD R/W-0 U1OD bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' U2OD: USART2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled U1OD: USART1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 0 (c) 2009 Microchip Technology Inc. DS39932C-page 127 PIC18F46J11 FAMILY REGISTER 9-3: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SPI2OD R/W-0 SPI1OD bit 0 Unimplemented: Read as `0' SPI2OD: SPI2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled SPI1OD: SPI1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 0 REGISTER 9-4: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2-1 U-0 -- PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1 (BANKED F3Ch) U-0 -- U-0 -- U-0 -- R/W-0 RTSECSEL1(1) R/W-0 RTSECSEL0(1) R/W-0 PMPTTL bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1) 11 = Reserved; do not use 10 = RTCC source clock is selected for the RTCC pin (can be INTRC or T1OSC, depending on the RTCOSC (CONFIG3L<1>) setting) 01 = RTCC seconds clock is selected for the RTCC pin 00 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit needs to be set. bit 0 Note 1: DS39932C-page 128 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 9.2 PORTA, TRISA and LATA Registers EXAMPLE 9-2: CLRF ; ; ; LATA ; ; ; 07h ; ADCON1 ; 07h ; CMCON ; 0CFh ; ; ; TRISA ; ; PORTA INITIALIZING PORTA Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Configure comparators for digital input Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs PORTA is a 7-bit wide, bidirectional port. It may function as a 5-bit port, depending on the oscillator mode selected. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Data Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of pins, RA<3:0> and RA5, as A/D converter inputs is selected by clearing or setting the control bits in the ADCON1 register (A/D Control Register 1). Pins, RA0 and RA3, may also be used as comparator inputs and by setting the appropriate bits in the CMCON register. To use RA<3:0> as digital inputs, it is also necessary to turn off the comparators. Note: On a Power-on Reset (POR), RA5 and RA<3:0> are configured as analog inputs and read as `0'. CLRF MOVLW MOVWF MOVWF MOVWF MOVLW MOVWF All PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. (c) 2009 Microchip Technology Inc. DS39932C-page 129 PIC18F46J11 FAMILY TABLE 9-3: Pin RA0/AN0/C1INA/ ULPWU/RP0 PORTA I/O SUMMARY Function RA0 AN0 C1INA ULPWU RP0 TRIS Setting 1 0 1 1 1 1 0 1 0 AN1 C2INA PMA7(1) 1 1 1 I/O 0 RP1 1 0 0 1 AN2 VREFCVREF C2INB 1 1 x I 0 I/O O I I I O I O O I I I I I/O I/O I I I 1/O I O I I I/O Type DIG TTL ANA ANA ANA ST DIG DIG TTL ANA ANA ST/ TTL DIG ST DIG DIG TTL ANA ANA ANA ANA ANA DIG TTL ANA ANA ANA Description PORTA<0> data input; disabled when analog input enabled. LATA<0> data output; not affected by analog input. A/D input channel 0 and Comparator C1- input. Default input configuration on POR; does not affect digital output. Comparator 1 input A. Ultra low-power wake-up input. Remappable peripheral pin 0 input. Remappable peripheral pin 0 output. PORTA<1> data input; disabled when analog input enabled. LATA<1> data output; not affected by analog input. A/D input channel 1 and Comparator C2- input. Default input configuration on POR; does not affect digital output. Comparator 1 input A. Parallel Master Port. Parallel Master Port address. Remappable peripheral pin 1 input. Remappable peripheral pin 1 output LATA<2> data output; not affected by analog input. Disabled when CVREF output enabled. PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. A/D input channel 2 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. A/D and comparator voltage reference low input. Comparator voltage reference output. Enabling this feature disables digital I/O. Comparator 2 input B. CTMU pulse generator charger for the C2INB comparator input. LATA<3> data output; not affected by analog input. PORTA<3> data input; disabled when analog input enabled. A/D input channel 3 and Comparator C1+ input. Default input configuration on POR. A/D and comparator voltage reference high input. Comparator 1 input B RA1/AN1/C2INA/ PMA7/RP1 RA1 RA2/AN2/ VREF-/CVREF/ C2INB RA2 RA3/AN3/VREF+/ C1INB RA3 AN3 VREF+ C1INB 0 1 1 1 1 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This bit is only available on 44-pin devices. DS39932C-page 130 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 9-3: Pin RA5/AN4/SS1/ HLVDIN/RP2 PORTA I/O SUMMARY (CONTINUED) Function RA5 AN4 SS1 HLVDIN RP2 TRIS Setting 0 1 1 1 1 1 0 x x 1 0 1 1 1 0 I/O O I I I I I O O O I O I I I O I/O Type DIG TTL ANA TTL ANA ST DIG ANA DIG TTL DIG ANA ANA TTL DIG Description LATA<5> data output; not affected by analog input. PORTA<5> data input; disabled when analog input enabled. A/D input channel 4. Default configuration on POR. Slave select input for MSSP1. High/Low-Voltage Detect external trip point reference input. Remappable Peripheral pin 2 input. Remappable Peripheral pin 2 output. Main oscillator feedback output connection (HS mode). System cycle clock output (FOSC/4) in RC and EC Oscillator modes. PORTA<6> data input. LATA<6> data output. Main oscillator input connection. Main clock input connection. PORTA<6> data input. LATA<6> data output. OSC2/CLKO/ RA6 OSC2 CLKO RA6 OSC1/CLKI/RA7 OSC1 CLKI RA7 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This bit is only available on 44-pin devices. TABLE 9-4: Name PORTA LATA TRISA ANCON0 CMxCON CVRCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 RA7 LAT7 TRIS7 CON CVREN Bit 6 RA6 LAT6 TRIS6 COE CVROE Bit 5 RA5 LAT5 TRISA5 CPOL CVRR Bit 4 -- -- -- PCFG4 EVPOL1 CVRSS Bit 3 RA3 LAT3 TRISA3 PCFG3 EVPOL0 CVR3 Bit 2 RA2 LAT2 TRISA2 PCFG2 CREF CVR2 Bit 1 RA1 LAT1 TRISA1 PCFG1 CCH1 CVR1 Bit 0 RA0 LAT0 TRISA0 PCFG0 CCH0 CVR0 Reset Values on page 81 81 81 82 81 82 PCFG7(1) PCFG6(1) PCFG5(1) Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTA. Note 1: These bits are only available in 44-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 131 PIC18F46J11 FAMILY 9.3 PORTB, TRISB and LATB Registers Four of the PORTB pins (RB<7:4>) have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB<7:4> pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB<7:4>) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB<7:4> are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from Sleep mode or any of the Idle modes. The user, in the Interrupt Service Routine (ISR), can clear the interrupt using the following steps: 1. 2. 3. Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). Wait one instruction cycle (such as executing a NOP instruction). Clear flag bit, RBIF. PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 9-3: CLRF PORTB INITIALIZING PORTB Initialize PORTB by clearing output data latches Alternate method to clear output data latches Configure as digital I/O pins in this example Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs ; ; ; CLRF LATB ; ; ; MOVLW 0x3F ; MOVFF WREG ADCON1 ; MOVLW 0CFh ; ; ; ; ; ; A mismatch condition continues to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared after one instruction cycle of delay. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. The RB5 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RB5/KBI1/SDI1/SDA1/RP8 pin. MOVWF TRISB Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a POR. Note: On a POR, the RB<3:0> bits are configured as analog inputs by default and read as `0'; RB<7:4> bits are configured as digital inputs. DS39932C-page 132 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 9-5: Pin RB0/AN12/ INT0/RP3 PORTB I/O SUMMARY Function RB0 TRIS Setting 1 0 AN12 INT0 RP3 1 1 1 0 1 0 AN10 RTCC RP4 1 0 1 0 1 0 AN8 CTEDG1 REFO RP5 1 1 0 1 0 0 1 AN9 CTEDG2 PMA2 (3) I/O 1 O I I I O I O I O I O I O I I O I O O I I I O I O I/O Type TTL DIG ANA ST ST DIG TTL DIG ANA DIG ST DIG TTL DIG ANA ST DIG ST DIG DIG TTL ANA ST DIG ST DIG Description PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) LATB<0> data output; not affected by analog input. A/D input channel 12.(1) External interrupt 0 input. Remappable peripheral pin 3 input. Remappable peripheral pin 3 output. PORTB<1> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) LATB<1> data output; not affected by analog input. A/D input channel 10.(1) Asynchronous serial transmit data output (USART module). Remappable peripheral pin 4 input. Remappable peripheral pin 4 output. PORTB<2> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) LATB<2> data output; not affected by analog input. A/D input channel 8.(1) CTMU Edge 1 input. Reference output clock. Remappable peripheral pin 5 input. Remappable peripheral pin 5 output. LATB<3> data output; not affected by analog input. PORTB<3> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) A/D input channel 9.(1) CTMU edge 2 input. Parallel Master Port address. Remappable peripheral pin 6 input. Remappable peripheral pin 6 output. RB1/AN10/ RTCC/RP4 RB1 RB2/AN8/ CTEDG1/ REFO/RP5 RB2 RB3/AN9/ CTEDG2/ PMA2/RP6 RB3 1 1 0 1 0 RP6 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. 2: All other pin functions are disabled when ICSPTM or ICD are enabled. 3: This bit is not available on 28-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 133 PIC18F46J11 FAMILY TABLE 9-5: Pin RB4/PMA1/ KBI0/RP7 PORTB I/O SUMMARY (CONTINUED) Function RB4 TRIS Setting 0 1 PMA1(3) KBI0 RP7 0 1 1 0 0 1 PMA0(3) KBI1 RP8 0 1 1 0 0 1 KBI2 PGC RP9 1 x 1 0 0 1 KBI3 PGD RP10 1 x x 1 0 I/O O I O I I O O I O I I O O I I I I O O I I O I I O I/O Type DIG TTL DIG TTL ST DIG DIG TTL DIG TTL ST DIG DIG TTL TTL ST ST DIG DIG TTL TTL DIG ST ST ST Description LATB<4> data output; not affected by analog input. PORTB<4> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) Parallel Master Port address. Interrupt-on-change pin. Remappable peripheral pin 7 input. Remappable peripheral pin 7 output. LATB<5> data output. PORTB<5> data input; weak pull-up when RBPU bit is cleared. Parallel Master Port address. Interrupt-on-change pin. Remappable peripheral pin 8 input. Remappable peripheral pin 8 output. LATB<6> data output. PORTB<6> data input; weak pull-up when RBPU bit is cleared. Interrupt-on-change pin. Serial execution (ICSPTM) clock input for ICSP and ICD operation.(2) Remappable peripheral pin 9 input. Remappable peripheral pin 9 output. LATB<7> data output. PORTB<7> data input; weak pull-up when RBPU bit is cleared. Interrupt-on-change pin. Serial execution data output for ICSP and ICD operation.(2) Serial execution data input for ICSP and ICD operation.(2) Remappable peripheral pin 10 input. Remappable peripheral pin 10 output. RB5/PMA0/ KBI1/RP8 RB5 RB6/KBI2/ PGC/RP9 RB6 RB7/KBI3/ PGD/RP10 RB7 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. 2: All other pin functions are disabled when ICSPTM or ICD are enabled. 3: This bit is not available on 28-pin devices. DS39932C-page 134 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 9-6: Name PORTB LATB TRISB INTCON INTCON2 INTCON3 ADCON0 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 RB7 LATB7 TRISB7 RBPU INT2IP PCFG7 Bit 6 RB6 LATB6 TRISB6 Bit 5 RB5 LATB5 TRISB5 TMR0IE INT3IE PCFG5 Bit 4 RB4 LATB4 TRISB4 INT0IE INT2IE PCFG4 Bit 3 RB3 LATB3 TRISB3 RBIE INT1IE PCFG3 Bit 2 RB2 LATB2 TRISB2 TMR0IF INT3IF PCFG2 Bit 1 RB1 LATB1 TRISB1 INT0IF INT3IP INT2IF PCFG1 Bit 0 RB0 LATB0 TRISB0 RBIF RBIP INT1IF PCFG0 Reset Values on page 81 81 81 81 81 81 81 GIE/GIEH PEIE/GIEL INT1IP PCFG6 INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTB. (c) 2009 Microchip Technology Inc. DS39932C-page 135 PIC18F46J11 FAMILY 9.4 PORTC, TRISC and LATC Registers Note: On a Power-on Reset, PORTC pins (except RC2, RC4 and RC5) are configured as digital inputs. RC2 will default as an analog input (controlled by the ANCON1 register). PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (see Table ). The pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information. Unlike other PORTC pins, RC4 and RC5 do not have TRISC bits associated with them. As digital ports, they can only function as digital inputs. If an external transceiver is used, RC4 and RC5 always function as inputs from the transceiver. If the on-chip transceiver is used, the data direction is determined by the operation being performed by the module at that time. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. EXAMPLE 9-4: CLRF PORTC ; ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTC Initialize PORTC by clearing output data latches CLRF LATC Alternate method to clear output data latches MOVLW 0x3F Value used to initialize data direction MOVWF TRISC Set RC<5:0> as inputs RC<7:6> as outputs MOVLB 0x0F ANCON register is not in Access Bank BSF ANCON1,PCFG11 ;Configure RC2/AN11 as digital input DS39932C-page 136 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 9-7: Pin RC0/T1OSO/ T1CKI/RP11 PORTC I/O SUMMARY(1) Function RC0 T1OSO T1CKI RP11 TRIS Setting 1 0 x 1 1 0 1 0 T1OSI RP12 x 1 0 1 0 AN11 CTPLS RP13 1 0 1 0 1 0 SCK1 SCL1 1 0 1 0 RP14 1 0 1 0 SDI1 SDA1 1 1 0 RP15 1 0 I/O I O O I I O I O I I O I O I O I O I O I O I O I O I O I I O I O I/O Type ST DIG ANA ST ST DIG ST DIG ANA ST DIG ST DIG ANA DIG ST DIG ST DIG DIG PORTC<0> data input. LATC<0> data output. Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. Timer1 counter input. Remappable peripheral pin 11 input. Remappable peripheral pin 11 output. PORTC<1> data input. LATC<1> data output. Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. Remappable peripheral pin 12 input. Remappable peripheral pin 12 output. PORTC<2> data input. LATC<2> data output. A/D input channel 11. CTMU pulse generator output. Remappable peripheral pin 13 input. Remappable peripheral pin 13 output. PORTC<3> data input. LATC<3> data output. Parallel Master Port address. Description RC1/T1OSI/ RP12 RC1 RC2/AN11/ CTPLS/RP13 RC2 RC3/SCK1/ SCL1/RP14 RC3 ST/TTL Parallel Master Port io_addr_in<1>. I2CTM clock input (MSSP1 module). I2C/ SMBus DIG ST DIG ST DIG ST I2C clock output (MSSP1 module). Remappable peripheral pin 14 input. Remappable peripheral pin 14 output. PORTC<4> data input. LATC<4> data output. SPI data input (MSSP1 module). RC4/SDI1/ SDA1/RP15 RC4 I2C data input (MSSP1 module). I2C/ SMBus DIG ST DIG I2C/SMBus. Remappable peripheral pin 15 input. Remappable peripheral pin 15 output. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Enhanced PWM output is available only on PIC18F4XJ11 devices. 2: This bit is only available on 44-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 137 PIC18F46J11 FAMILY TABLE 9-7: Pin RC5/SDO1/ RP16 PORTC I/O SUMMARY(1) (CONTINUED) Function RC5 SDO1 RP16 TRIS Setting 1 0 0 1 0 1 0 PMA5 (2) I/O I O O I O I O I O O I/O Type DIG DIG DIG ST DIG ST DIG DIG DIG PORTC<5> data input. LATC<5> data output. Description SPI data output (MSSP1 module). Remappable peripheral pin 16 input. Remappable peripheral pin 16 output. PORTC<6> data input. LATC<6> data output. Parallel Master Port address. Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as output. Synchronous serial clock input (EUSART module). Synchronous serial clock output (EUSART module); takes priority over port data. Remappable peripheral pin 17 input. Remappable peripheral pin 17 output. PORTC<7> data input. LATC<7> data output. Asynchronous serial receive data input (EUSART module). Synchronous serial data input (EUSART module). User must configure as an input. Synchronous serial data output (EUSART module); takes priority over port data. Remappable peripheral pin 18 input. Remappable peripheral pin 18 output. RC6/PMA5/ TX1/CK1/RP17 RC6 1 0 0 ST/TTL Parallel Master Port io_addr_in<5>. TX1 CK1 1 0 I O I O I O I 1 O I O ST DIG ST DIG ST DIG ST ST DIG ST DIG RP17 RC7/RX1/DT1/ RP18 RC7 RX1 DT1 1 0 1 0 1 1 0 RP18 1 0 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don't care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Enhanced PWM output is available only on PIC18F4XJ11 devices. 2: This bit is only available on 44-pin devices. TABLE 9-8: Name PORTC LATC TRISC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 RC7 LATC7 TRISC7 Bit 6 RC6 LATC6 TRISC6 Bit 5 RC5 LATC5 TRISC5 Bit 4 RC4 LATC4 TRISC4 Bit 3 RC3 LATC3 TRISC3 Bit 2 RC2 LATC2 TRISC2 Bit 1 RC1 LATC1 TRISC1 Bit 0 RC0 LATC0 TRISC0 Reset Values on page: 81 81 81 DS39932C-page 138 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 9.5 Note: PORTD, TRISD and LATD Registers PORTD is available only in 44-pin devices. Note: On a POR, these pins are configured as digital inputs. EXAMPLE 9-5: CLRF PORTD ; ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTD Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. CLRF LATD MOVLW 0CFh MOVWF TRISD Each of the PORTD pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by setting bit, RDPU (PORTE<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a POR. Note that the pull-ups can be used for any set of features, similar to the pull-ups found on PORTB. (c) 2009 Microchip Technology Inc. DS39932C-page 139 PIC18F46J11 FAMILY TABLE 9-9: Pin RD0/PMD0/ SCL2 PORTD I/O SUMMARY Function RD0 PMD0 SCL2 TRIS Setting 1 0 1 0 1 0 I/O I O I O I O I O I O I O II O I O I O I O I O I O I O I O I O I O I O I O I/O Type ST DIG DIG I2C/ SMB DIG ST DIG TTL DIG I2C/ SMB DIG ST DIG TTL DIG ST DIG DIG DIG DIG ST DIG ST DIG TTL DIG ST DIG ST DIG TTL DIG ST DIG PORTD<0> data input. LATD<0> data output. Parallel Master Port data out. I2CTM clock input (MSSP2 module); input type depends on module setting. I2CTM clock output (MSSP2 module); takes priority over port data. PORTD<1> data input. LATD<1> data output. Parallel Master Port data in. Parallel Master Port data out. I2C data input (MSSP2 module); input type depends on module setting. I2C data output (MSSP2 module); takes priority over port data. PORTD<2> data input. LATD<2> data output. Parallel Master Port data in. Parallel Master Port data out. Remappable peripheral pin 19 input. Remappable peripheral pin 19 output. PORTD<3> data input. LATD<3> data output. Parallel Master Port data out. Remappable peripheral pin 20 input. Remappable peripheral pin 20 output. PORTD<4> data input. LATD<4> data output. Parallel Master Port data in. Parallel Master Port data out. Remappable peripheral pin 21 input. Remappable peripheral pin 21 output. PORTD<5> data input. LATD<5> data output. Parallel Master Port data in. Parallel Master Port data out. Remappable peripheral pin 22 input. Remappable peripheral pin 22 output. Description ST/TTL Parallel Master Port data in. RD1/PMD1/ SDA2 RD1 PMD1 SDA2 1 0 1 0 1 0 RD2/PMD2/ RP19 RD2 PMD2 RP19 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 RD3/PMD3/ RP20 RD3 PMD3 RP20 ST/TTL Parallel Master Port data in. RD4/PMD4/ RP21 RD4 PMD4 RP21 RD5/PMD5/ RP22 RD5 PMD5 RP22 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C/SMB = I2C/SMBus input buffer; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). DS39932C-page 140 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 9-9: Pin RD6/PMD6/ RP23 PORTD I/O SUMMARY (CONTINUED) Function RD6 PMD6 RP23 TRIS Setting 1 0 1 0 1 0 1 0 PMD7 RP24 1 0 1 0 I/O I O I O I O I O I O I O I/O Type ST DIG TTL DIG ST DIG ST DIG TTL DIG ST DIG PORTD<6> data input. LATD<6> data output. Parallel Master Port data in. Parallel Master Port data out. Remappable peripheral pin 23 input. Remappable peripheral pin 23 output. PORTD<7> data input. LATD<7> data output. Parallel Master Port data in. Parallel Master Port data out. Remappable peripheral pin 24 input. Remappable peripheral pin 24 output. Description RD7/PMD7/ RP24 RD7 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C/SMB = I2C/SMBus input buffer; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). TABLE 9-10: Name PORTD(1) LATD(1) TRISD(1) SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 RD7 LATD7 Bit 6 RD6 LATD6 TRISD6 Bit 5 RD5 LATD5 TRISD5 Bit 4 RD4 LATD4 TRISD4 Bit 3 RD3 LATD3 TRISD3 Bit 2 RD2 LATD2 TRISD2 Bit 1 RD1 LATD1 TRISD1 Bit 0 RD0 LATD0 TRISD0 Reset Values on page 86 86 86 TRISD7 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTD. Note 1: These registers are not available in 28-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 141 PIC18F46J11 FAMILY 9.6 Note: PORTE, TRISE and LATE Registers PORTE is available only in 44-pin devices. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. Depending on the particular PIC18F46J11 family device selected, PORTE is implemented in two different ways. For 44-pin devices, PORTE is a 3-bit wide port. Three pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/ AN7/PMCS) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as analog inputs, these pins will read as `0's. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a POR, RE<2:0> are configured as analog inputs. EXAMPLE 9-6: CLRF PORTE ; ; ; ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTE Initialize PORTE by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RE<0> as inputs RE<1> as outputs RE<2> as inputs CLRF LATE MOVLW MOVWF MOVLW 0Ah ADCON1 03h MOVWF TRISE Each of the PORTE pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by setting bit, REPU (PORTE<6>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a POR. Note that the pull-ups can be used for any set of features, similar to the pull-ups found on PORTB. DS39932C-page 142 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 9-11: Pin RE0/AN5/ PMRD PORTE I/O SUMMARY Function RE0 AN5 PMRD TRIS Setting 1 0 1 1 0 1 0 AN6 PMWR 1 1 0 1 0 AN7 PMCS 1 0 -- -- -- -- -- -- I/O I O I I O I O I I O I O I O P P P P P P -- I/O Type ST DIG ANA DIG ST DIG ANA DIG ST DIG ANA DIG -- -- -- -- -- -- Description PORTE<0> data input; disabled when analog input enabled. LATE<0> data output; not affected by analog input. A/D input channel 5; default input configuration on POR. Parallel Master Port read strobe. PORTE<1> data input; disabled when analog input enabled. LATE<1> data output; not affected by analog input. A/D input channel 6; default input configuration on POR. Parallel Master Port write strobe. PORTE<2> data input; disabled when analog input enabled. LATE<2> data output; not affected by analog input. A/D input channel 7; default input configuration on POR. Parallel Master Port byte enable. Ground reference for logic and I/O pins. Ground reference for analog modules. Positive supply for peripheral digital logic and I/O pins. Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled). Positive supply for analog modules. ST/TTL Parallel Master Port io_rd_in. RE1/AN6/ PMWR RE1 ST/TTL Parallel Master Port io_wr_in. RE2/AN7/ PMCS RE2 VSS1 VSS2 AVSS1 VDD1 VDD2 VDDCORE/VCAP AVDD1 AVDD2 -- -- -- VDDCORE VCAP -- Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level I = Input; O = Output; P = Power TABLE 9-12: Name PORTE(1) LATE (1) SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Bit 7 Bit 6 REPU(4) -- -- PCFG6 (2) Bit 5 -- -- -- PCFG5 (2) Bit 4 -- -- -- PCFG4 Bit 3 -- -- -- PCFG3 Bit 2 RE2 LATE2 TRISE2 PCFG2 Bit 1 RE1 LATE1 TRISE1 PCFG1 Bit 0 RE0 LATE0 TRISE0 PCFG0 Reset Values on page 86 86 85 87 RDPU(3) -- -- PCFG7(2) TRISE(1) ANCON0 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTE. Note 1: These registers are not available in 28-pin devices. 2: These bits are only available in 44-pin devices. Note 1: PORTD Pull-up Enable bit 0 = All PORTD pull-ups are disabled 1 = PORTD pull-ups are enabled for any input pad 2: PORTE Pull-up Enable bit 0 = All PORTE pull-ups are disabled 1 = PORTE pull-ups are enabled for any input pad (c) 2009 Microchip Technology Inc. DS39932C-page 143 PIC18F46J11 FAMILY 9.7 Peripheral Pin Select (PPS) 9.7.2 AVAILABLE PERIPHERALS A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin count devices similar to the PIC18F46J11 family. In an application that needs to use more than one peripheral multiplexed on single pin, inconvenient workarounds in application code or a complete redesign may be the only option. The Peripheral Pin Select (PPS) feature provides an alternative to these choices by enabling the user's peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The PPS feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/ or output of any one of the many digital peripherals to any one of these I/O pins. PPS is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. The peripherals managed by the PPS are all digital only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer-related peripherals (input capture and output compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals. The PPS module is not applied to I2C, change notification inputs, RTCC alarm outputs or peripherals with analog inputs. Additionally, the MSSP1 and EUSART1 modules are not routed through the PPS module. A key difference between pin select and non-pin select peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non PPS peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. 9.7.2.1 Peripheral Pin Select Function Priority 9.7.1 AVAILABLE PINS The PPS feature is used with a range of up to 22 pins; the number of available pins is dependent on the particular device and its pin count. Pins that support the PPS feature include the designation "RPn" in their full pin designation, where "RP" designates a remappable peripheral and "n" is the remappable pin number. See Table 1-2 for pinout options in each package offering. When a pin selectable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Pin select peripherals never take priority over any analog functions associated with the pin. 9.7.3 CONTROLLING PERIPHERAL PIN SELECT PPS features are controlled through two sets of Special Function Registers (SFRs): one to map peripheral inputs and the other to map outputs. Because they are separately controlled, a particular peripheral's input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or an output is being mapped. DS39932C-page 144 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 9.7.3.1 Input Mapping The inputs of the PPS options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 9-6 through Register 9-20). Each register contains a 5-bit field, which is associated with one of the pin selectable peripherals. Programming a given peripheral's bit field with an appropriate 5-bit value maps the RPn pin with that value to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the maximum number of peripheral pin selections supported by the device. TABLE 9-13: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Input Name Function Name Register Configuration Bits INTR1R<4:0> INTR2R<4:0> INTR3R<4:0> T0CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> T1GR<4:0> T3GR<4:0> RX2DT2R<4:0> CK2R<4:0> SDI2R<4:0> SCK2R<4:0> SS2R<4:0> OCFAR<4:0> External Interrupt 1 INT1 RPINR1 External Interrupt 2 INT2 RPINR2 External Interrupt 3 INT3 RPINR3 Timer0 External Clock Input T0CKI RPINR4 Timer3 External Clock Input T3CKI RPINR6 Input Capture 1 CCP1 RPINR7 Input Capture 2 CCP2 RPINR8 Timer1 Gate Input T1G RPINR12 Timer3 Gate Input T3G RPINR13 EUSART2 Asynchronous Receive/Synchronous RX2/DT2 RPINR16 Receive EUSART2 Asynchronous Clock Input CK2 RPINR17 SPI2 Data Input SDI2 RPINR21 SPI2 Clock Input SCK2IN RPINR22 SPI2 Slave Select Input SS2IN RPINR23 PWM Fault Input FLT0 RPINR24 Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. (c) 2009 Microchip Technology Inc. DS39932C-page 145 PIC18F46J11 FAMILY 9.7.3.2 Output Mapping In contrast to inputs, the outputs of the PPS options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. The value of the bit field corresponds to one of the peripherals and that peripheral's output is mapped to the pin (see Table 9-14). Because of the mapping technique, the list of peripherals for output mapping also includes a null value of `00000'. This permits any given pin to remain disconnected from the output of any of the pin selectable peripherals. TABLE 9-14: Function SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Output Function Number(1) Output Name NULL 0 NULL(2) C1OUT 1 Comparator 1 Output C2OUT 2 Comparator 2 Output TX2/CK2 5 EUSART2 Asynchronous Transmit/Asynchronous Clock Output DT2 6 EUSART2 Synchronous Transmit SDO2 9 SPI2 Data Output SCK2 10 SPI2 Clock Output SSDMA 12 SPI DMA Slave Select ULPOUT 13 Ultra Low-Power Wake-up Event CCP1/P1A 14 ECCP1 Compare or PWM Output Channel A P1B 15 ECCP1 Enhanced PWM Output, Channel B P1C 16 ECCP1 Enhanced PWM Output, Channel C P1D 17 ECCP1 Enhanced PWM Output, Channel D CCP2/P2A 18 ECCP2 Compare or PWM Output P2B 19 ECCP2 Enhanced PWM Output, Channel B P2C 20 ECCP2 Enhanced PWM Output, Channel C P2D 21 ECCP2 Enhanced PWM Output, Channel D Note 1: Value assigned to the RPn<4:0> pins corresponds to the peripheral output function number. 2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. DS39932C-page 146 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 9.7.3.3 Mapping Limitations 9.7.4.3 Configuration Bit Pin Select Lock The control schema of the PPS is extremely flexible. Other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lock outs. The flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins. As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (CONFIG3H<0>) Configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the PPS control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the PPS registers. 9.7.4 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC18F devices include three features to prevent alterations to the peripheral map: * Control register lock sequence * Continuous state monitoring * Configuration bit remapping lock 9.7.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION 9.7.4.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (PPSCON<0>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear IOLOCK, a specific command sequence must be executed: 1. 2. 3. Write 55h to EECON2<7:0>. Write AAh to EECON2<7:0>. Clear (or set) IOLOCK as a single operation. The ability to control peripheral pin selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the PPS is not available on default pins in the device's default (Reset) state. Since all RPINRx registers reset to `11111' and all RPORx registers reset to `00000', all PPS inputs are tied to RP31 and all PPS outputs are disconnected. Note: In tying PPS inputs to RP31, RP31 does not have to exist on a device for the registers to be reset to it. IOLOCK remains in one state until changed. This allows all of the PPS registers to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. This situation requires the user to initialize the device with the proper peripheral configuration before any other application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of Reset. For application safety, however, it is best to set IOLOCK and lock the configuration after writing to the control registers. Because the unlock sequence is timing critical, it must be executed as an assembly language routine. If the bulk of the application is written in C or another highlevel language, the unlock sequence should be performed by writing in-line assembly. 9.7.4.2 Continuous State Monitoring In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered. (c) 2009 Microchip Technology Inc. DS39932C-page 147 PIC18F46J11 FAMILY Choosing the configuration requires the review of all PPSs and their pin assignments, especially those that will not be used in the application. In all cases, unused pin selectable peripherals should be disabled completely. Unused peripherals should have their inputs assigned to an unused RPn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output. The assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin's I/O circuitry. In theory, this means adding a pin selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is driven. Users must be familiar with the behavior of other fixed peripherals that share a remappable pin and know when to enable or disable them. To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. The peripheral must be specifically configured for operation and enabled, as if it were tied to a fixed pin. Where this happens in the application code (immediately following device Reset and peripheral configuration or inside the main application routine) depends on the peripheral and its use in the application. A final consideration is that the PPS functions neither override analog inputs nor reconfigure pins with analog functions for digital I/O. If a pin is configured as an analog input on device Reset, it must be explicitly reconfigured as digital I/O when used with a PPS. Example 9-7 provides a configuration for bidirectional communication with flow control using EUSART2. The following input and output functions are used: * Input Function RX2 * Output Function TX2 EXAMPLE 9-7: CONFIGURING EUSART2 INPUT AND OUTPUT FUNCTIONS //************************************* // Unlock Registers //************************************* _asm ; PPS registers are in BANK 14 MOVLB 0x0E MOVLW 0x55 MOVWF EECON2, 0 MOVLW 0xAA MOVWF EECON2, 0 ; PPS Write Protect off BCF PPSCON, IOLOCK, BANKED _endasm //*************************** // Configure Input Functions // (See Table 9-13) //*************************** //*************************** // Assign RX2 To Pin RP0 //*************************** _asm MOVLW 0x00 MOVWF RPINR16, BANKED _endasm //*************************** // Configure Output Functions // (See Table 9-14) //*************************** //*************************** // Assign TX2 To Pin RP1 //*************************** _asm MOVLW 0x05 MOVWF RPOR1, BANKED _endasm //************************************* // Lock Registers //************************************* _asm MOVLW 0x55 MOVWF EECON2, 0 MOVLW 0xAA MOVWF EECON2, 0 ; PPS Write Protected BSF PPSCON, IOLOCK, BANKED _endasm Note: If the Configuration bit, IOL1WAY = 1, once the IOLOCK bit is set, it cannot be cleared, preventing any future RP register changes. The IOLOCK bit is cleared back to `0' on any device Reset. DS39932C-page 148 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 9.7.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC18F46J11 family of devices implements a total of 37 registers for remappable peripheral configuration of 44-pin devices. The 28-pin devices have 31 registers for remappable peripheral configuration. Input and output register values can only be changed if PPS REGISTER 9-5: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 bit 0 PPSCON: PERIPHERAL PIN SELECT INPUT REGISTER 0 (BANKED EFFh)(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 IOLOCK bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' IOLOCK: I/O Lock Enable bit 1 = I/O lock active, RPORx and RPINRx registers are write-protected 0 = I/O lock not active, pin configurations can be changed Register values can only be changed if PPSCON Note 1: (c) 2009 Microchip Technology Inc. DS39932C-page 149 PIC18F46J11 FAMILY REGISTER 9-6: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 (BANKED EE7h) U-0 -- U-0 -- R/W-1 INTR1R4 R/W-1 INTR1R3 R/W-1 INTR1R2 R/W-1 INTR1R1 R/W-1 INTR1R0 bit 0 Unimplemented: Read as `0' INTR1R<4:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits REGISTER 9-7: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 (BANKED EE8h) U-0 -- U-0 -- R/W-1 INTR2R4 R/W-1 INTR2R3 R/W-1 INTR2R2 R/W-1 INTR2R1 R/W-1 INTR2R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' INTR2R<4:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn pin bits REGISTER 9-8: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 (BANKED EE9h) U-0 -- U-0 -- R/W-1 INTR3R4 R/W-1 INTR3R3 R/W-1 INTR3R2 R/W-1 INTR3R1 R/W-1 INTR3R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' INTR3R<4:0>: Assign External Interrupt 3 (INT3) to the Corresponding RPn Pin bits DS39932C-page 150 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 9-9: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 (BANKED EEAh) U-0 -- U-0 -- R/W-1 T0CKR4 R/W-1 T0CKR3 R/W-1 T0CKR2 R/W-1 T0CKR1 R/W-1 T0CKR0 bit 0 Unimplemented: Read as `0' T0CKR<4:0>: Timer0 External Clock Input (T0CKI) to the Corresponding RPn Pin bits REGISTER 9-10: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR6: PERIPHERAL PIN SELECT INPUT REGISTER 6 (BANKED EECh) U-0 -- U-0 -- R/W-1 T3CKR4 R/W-1 T3CKR3 R/W-1 T3CKR2 R/W-1 T3CKR1 R/W-1 T3CKR0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' T3CKR<4:0>: Timer 3 External Clock Input (T3CKI) to the Corresponding RPn Pin bits REGISTER 9-11: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 (BANKED EEDh) U-0 -- U-0 -- R/W-1 IC1R4 R/W-1 IC1R3 R/W-1 IC1R2 R/W-1 IC1R1 R/W-1 IC1R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' IC1R<4:0>: Assign Input Capture 1 (ECCP1) to the Corresponding RPn Pin bits (c) 2009 Microchip Technology Inc. DS39932C-page 151 PIC18F46J11 FAMILY REGISTER 9-12: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 (BANKED EEEh) U-0 -- U-0 -- R/W-1 IC2R4 R/W-1 IC2R3 R/W-1 IC2R2 R/W-1 IC2R1 R/W-1 IC2R0 bit 0 Unimplemented: Read as `0' IC2R<4:0>: Assign Input Capture 2 (ECCP2) to the Corresponding RPn Pin bits REGISTER 9-13: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (BANKED EF2h) U-0 -- U-0 -- R/W-1 T1GR4 R/W-1 T1GR3 R/W-1 T1GR2 R/W-1 T1GR1 R/W-1 T1GR0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' T1GR<4:0>: Timer1 Gate Input (T1G) to the Corresponding RPn Pin bits REGISTER 9-14: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 (BANKED EF3h) U-0 -- U-0 -- R/W-1 T3GR4 R/W-1 T3GR3 R/W-1 T3GR2 R/W-1 T3GR1 R/W-1 T3GR0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' T3GR<4:0>: Timer3 Gate Input (T3G) to the Corresponding RPn Pin bits DS39932C-page 152 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 9-15: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPINR16: PERIPHERAL PIN SELECT INPUT REGISTER 16 (BANKED EF6h) U-0 -- U-0 -- R/W-1 RX2DT2R4 R/W-1 RX2DT2R3 R/W-1 RX2DT2R2 R/W-1 RX2DT2R1 R/W-1 RX2DT2R0 bit 0 Unimplemented: Read as `0' RX2DT2R<4:0>: EUSART2 Synchronous/Asynchronous Receive (RX2/DT2) to the Corresponding RPn Pin bits REGISTER 9-16: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 (BANKED EF7h) U-0 -- U-0 -- R/W-1 CK2R4 R/W-1 CK2R3 R/W-1 CK2R2 R/W-1 CK2R1 R/W-1 CK2R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' CK2R<4:0>: EUSART2 Clock Input (CK2) to the Corresponding RPn Pin bits REGISTER 9-17: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 (BANKED EFBh) U-0 -- U-0 -- R/W-1 SDI2R4 R/W-1 SDI2R3 R/W-1 SDI2R2 R/W-1 SDI2R1 R/W-1 SDI2R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits (c) 2009 Microchip Technology Inc. DS39932C-page 153 PIC18F46J11 FAMILY REGISTER 9-18: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 (BANKED EFCh) U-0 -- U-0 -- R/W-1 SCK2R4 R/W-1 SCK2R3 R/W-1 SCK2R2 R/W-1 SCK2R1 R/W-1 SCK2R0 bit 0 Unimplemented: Read as `0' SCK2R<4:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits REGISTER 9-19: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 (BANKED EFDh) U-0 -- U-0 -- R/W-1 SS2R4 R/W-1 SS2R3 R/W-1 SS2R2 R/W-1 SS2R1 R/W-1 SS2R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' SS2R<4:0>: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits REGISTER 9-20: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24 (BANKED EFEh) U-0 -- U-0 -- R/W-0 OCFAR4 R/W-0 OCFAR3 R/W-0 OCFAR2 R/W-0 OCFAR1 R/W-0 OCFAR0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' OCFAR<4:0>: Assign PWM Fault Input (FLT0) to the Corresponding RPn Pin bits DS39932C-page 154 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 9-21: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 Note 1: R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 (BANKED EC6h)(1) U-0 -- U-0 -- R/W-0 RP0R4 R/W-0 RP0R3 R/W-0 RP0R2 R/W-0 RP0R1 R/W-0 RP0R0 bit 0 Unimplemented: Read as `0' RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 9-14 for peripheral function numbers) Register values can be changed only if PPSCON REGISTER 9-22: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 (BANKED EC7h) U-0 -- U-0 -- R/W-0 RP1R4 R/W-0 RP1R3 R/W-0 RP1R2 R/W-0 RP1R1 R/W-0 RP1R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-23: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 (BANKED EC8h) U-0 -- U-0 -- R/W-0 RP2R4 R/W-0 RP2R3 R/W-0 RP2R2 R/W-0 RP2R1 R/W-0 RP2R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 9-14 for peripheral function numbers) (c) 2009 Microchip Technology Inc. DS39932C-page 155 PIC18F46J11 FAMILY REGISTER 9-24: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 (BANKED EC9h) U-0 -- U-0 -- R/W-0 RP3R4 R/W-0 RP3R3 R/W-0 RP3R2 R/W-0 RP3R1 R/W-0 RP3R0 bit 0 Unimplemented: Read as `0' RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-25: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 (BANKED ECAh) U-0 -- U-0 -- R/W-0 RP4R4 R/W-0 RP4R3 R/W-0 RP4R2 R/W-0 RP4R1 R/W-0 RP4R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-26: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 (BANKED ECBh) U-0 -- U-0 -- R/W-0 RP5R4 R/W-0 RP5R3 R/W-0 RP5R2 R/W-0 RP5R1 R/W-0 RP5R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 9-14 for peripheral function numbers) DS39932C-page 156 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 9-27: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 (BANKED ECCh) U-0 -- U-0 -- R/W-0 RP6R4 R/W-0 RP6R3 R/W-0 RP6R2 R/W-0 RP6R1 R/W-0 RP6R0 bit 0 Unimplemented: Read as `0' RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-28: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 (BANKED ECDh) U-0 -- U-0 -- R/W-0 RP7R4 R/W-0 RP7R3 R/W-0 RP7R2 R/W-0 RP7R1 R/W-0 RP7R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-29: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 (BANKED ECEh) U-0 -- U-0 -- R/W-0 RP8R4 R/W-0 RP8R3 R/W-0 RP8R2 R/W-0 RP8R1 R/W-0 RP8R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 9-14 for peripheral function numbers) (c) 2009 Microchip Technology Inc. DS39932C-page 157 PIC18F46J11 FAMILY REGISTER 9-30: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 (BANKED ECFh) U-0 -- U-0 -- R/W-0 RP9R4 R/W-0 RP9R3 R/W-0 RP9R2 R/W-0 RP9R1 R/W-0 RP9R0 bit 0 Unimplemented: Read as `0' RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-31: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 (BANKED ED0h) U-0 -- U-0 -- R/W-0 RP10R4 R/W-0 RP10R3 R/W-0 RP10R2 R/W-0 RP10R1 R/W-0 RP10R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-32: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 (BANKED ED1h) U-0 -- U-0 -- R/W-0 RP11R4 R/W-0 RP11R3 R/W-0 RP11R2 R/W-0 RP11R1 R/W-0 RP11R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 9-14 for peripheral function numbers) DS39932C-page 158 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 9-33: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 (BANKED ED2h) U-0 -- U-0 -- R/W-0 RP12R4 R/W-0 RP12R3 R/W-0 RP12R2 R/W-0 RP12R1 R/W-0 RP12R0 bit 0 Unimplemented: Read as `0' RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-34: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 (BANKED ED3h) U-0 -- U-0 -- R/W-0 RP13R4 R/W-0 RP13R3 R/W-0 RP13R2 R/W-0 RP13R1 R/W-0 RP13R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-35: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 (BANKED ED4h) U-0 -- U-0 -- R/W-0 RP14R4 R/W-0 RP14R3 R/W-0 RP14R2 R/W-0 RP14R1 R/W-0 RP14R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 9-14 for peripheral function numbers) (c) 2009 Microchip Technology Inc. DS39932C-page 159 PIC18F46J11 FAMILY REGISTER 9-36: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15 (BANKED ED5h) U-0 -- U-0 -- R/W-0 RP15R4 R/W-0 RP15R3 R/W-0 RP15R2 R/W-0 RP15R1 R/W-0 RP15R0 bit 0 Unimplemented: Read as `0' RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-37: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16 (BANKED ED6h) U-0 -- U-0 -- R/W-0 RP16R4 R/W-0 RP16R3 R/W-0 RP16R2 R/W-0 RP16R1 R/W-0 RP16R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP16R<4:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-38: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17 (BANKED ED7h) U-0 -- U-0 -- R/W-0 RP17R4 R/W-0 RP17R3 R/W-0 RP17R2 R/W-0 RP17R1 R/W-0 RP17R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table 9-14 for peripheral function numbers) DS39932C-page 160 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 9-39: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPOR18: PERIPHERAL PIN SELECT OUTPUT REGISTER 18 (BANKED ED8h) U-0 -- U-0 -- R/W-0 RP18R4 R/W-0 RP18R3 R/W-0 RP18R2 R/W-0 RP18R1 R/W-0 RP18R0 bit 0 Unimplemented: Read as `0' RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table 9-14 for peripheral function numbers) REGISTER 9-40: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 Note 1: RPOR19: PERIPHERAL PIN SELECT OUTPUT REGISTER 19 (BANKED ED9h)(1) U-0 -- U-0 -- R/W-0 RP19R4 R/W-0 RP19R3 R/W-0 RP19R2 R/W-0 RP19R1 R/W-0 RP19R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table 9-14 for peripheral function numbers) RP19 pins are not available on 28-pin devices. REGISTER 9-41: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 Note 1: RPOR20: PERIPHERAL PIN SELECT OUTPUT REGISTER 20 (BANKED EDAh)(1) U-0 -- U-0 -- R/W-0 RP20R4 R/W-0 RP20R3 R/W-0 RP20R2 R/W-0 RP20R1 R/W-0 RP20R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 9-14 for peripheral function numbers) RP20 pins are not available on 28-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 161 PIC18F46J11 FAMILY REGISTER 9-42: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 Note 1: R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPOR21: PERIPHERAL PIN SELECT OUTPUT REGISTER 21 (BANKED EDBh)(1) U-0 -- U-0 -- R/W-0 RP21R4 R/W-0 RP21R3 R/W-0 RP21R2 R/W-0 RP21R1 R/W-0 RP21R0 bit 0 Unimplemented: Read as `0' RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits (see Table 9-14 for peripheral function numbers) RP21 pins are not available on 28-pin devices. REGISTER 9-43: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 Note 1: RPOR22: PERIPHERAL PIN SELECT OUTPUT REGISTER 22 (BANKED EDCh)(1) U-0 -- U-0 -- R/W-0 RP22R4 R/W-0 RP22R3 R/W-0 RP22R2 R/W-0 RP22R1 R/W-0 RP22R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 9-14 for peripheral function numbers) RP22 pins are not available on 28-pin devices. REGISTER 9-44: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 Note 1: RPOR23: PERIPHERAL PIN SELECT OUTPUT REGISTER 23 (BANKED EDDh)(1) U-0 -- U-0 -- R/W-0 RP23R4 R/W-0 RP23R3 R/W-0 RP23R2 R/W-0 RP23R1 R/W-0 RP23R0 bit 0 R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 9-14 for peripheral function numbers) RP23 pins are not available on 28-pin devices. DS39932C-page 162 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 9-45: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 Note 1: R/W = Readable, Writable if IOLOCK = 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RPOR24: PERIPHERAL PIN SELECT OUTPUT REGISTER 24 (BANKED EDEh)(1) U-0 -- U-0 -- R/W-0 RP24R4 R/W-0 RP24R3 R/W-0 RP24R2 R/W-0 RP24R1 R/W-0 RP24R0 bit 0 Unimplemented: Read as `0' RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 9-14 for peripheral function numbers) RP24 pins are not available on 28-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 163 PIC18F46J11 FAMILY NOTES: DS39932C-page 164 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 10.0 PARALLEL MASTER PORT (PMP) Key features of the PMP module are: * Up to 16 bits of Addressing when Using Data/Address Multiplexing * Up to 8 Programmable Address Lines * One Chip Select Line * Programmable Strobe Options: - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe * Address Auto-Increment/Auto-Decrement * Programmable Address/Data Multiplexing * Programmable Polarity on Control Signals * Legacy Parallel Slave Port Support * Enhanced Parallel Slave Support: - Address Support - 4-Byte Deep, Auto-Incrementing Buffer * Programmable Wait States * Selectable Input Voltage Levels The Parallel Master Port module (PMP) is an 8-bit parallel I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable. The PMP module can be configured to serve as either a PMP or as a Parallel Slave Port (PSP). FIGURE 10-1: PMP MODULE OVERVIEW Address Bus Data Bus PMA<0> PMALL PMA<1> PMALH PIC18 Parallel Master Port Control Lines Up to 8-Bit Address PMA<7:2> EEPROM PMCS PMBE PMRD PMRD/PMWR PMWR PMENB PMD<7:0> PMA<7:0> PMA<15:8> Microcontroller LCD FIFO Buffer 8-Bit Data (c) 2009 Microchip Technology Inc. DS39932C-page 165 PIC18F46J11 FAMILY 10.1 Module Registers The PMP module has a total of 14 Special Function Registers (SFRs) for its operation, plus one additional register to set configuration options. Of these, eight registers are used for control and six are used for PMP data transfer. The PMCON registers (Register 10-1 and Register 10-2) control basic module operations, including turning the module on or off. They also configure address multiplexing and control strobe configuration. The PMMODE registers (Register 10-3 and Register 10-4) configure the various Master and Slave modes, the data width and interrupt generation. The PMEH and PMEL registers (Register 10-5 and Register 10-6) configure the module's operation at the hardware (I/O pin) level. The PMSTAT registers (Register 10-5 and Register 10-6) provide status flags for the module's input and output buffers, depending on the operating mode. 10.1.1 CONTROL REGISTERS The eight PMP Control registers are: * PMCONH and PMCONL * PMMODEH and PMMODEL * PMSTATL and PMSTATH * PMEH and PMEL REGISTER 10-1: R/W-0 PMPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 PMCONH: PARALLEL PORT CONTROL REGISTER HIGH BYTE (BANKED F5Fh)(1) U-0 -- R/W-0 PSIDL R/W-0 ADRMUX1 R/W-0 ADRMUX0 R/W-0 PTBEEN R/W-0 PTWREN R/W-0 PTRDEN bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed Unimplemented: Read as `0' PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins (only eight bits of address are available in this mode) 00 = Address and data appear on separate pins (only eight bits of address are available in this mode) PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled This register is only available in 44-pin devices. bit 6 bit 5 bit 4-3 bit 2 bit 1 bit 0 Note 1: DS39932C-page 166 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 10-2: R/W-0 CSF1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE (BANKED F5Eh)(1) R/W-0(2) ALP U-0 -- R/W-0(2) CS1P R/W-0 BEP R/W-0 WRSP R/W-0 RDSP bit 0 R/W-0 CSF0 CSF<1:0>: Chip Select Function bits 11 = Reserved 10 = Chip select function is enabled and PMCS1 acts as chip select (in Master mode). Up to 13 address bits only can be generated. 01 = Reserved 00 = Chip select function is disabled (in Master mode). All 16 address bits can be generated. ALP: Address Latch Polarity bit(2) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) Unimplemented: Maintain as `0' CS1P: Chip Select Polarity bit(2) 1 = Active-high (PMCS) 0 = Active-low (PMCS) BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) WRSP: Write Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODEH<1:0> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master Mode 1 (PMMODEH<1:0> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) RDSP: Read Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODEH<1:0> = 00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master Mode 1 (PMMODEH<1:0> = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) This register is only available in 44-pin devices. These bits have no effect when their corresponding pins are used as address lines. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: (c) 2009 Microchip Technology Inc. DS39932C-page 167 PIC18F46J11 FAMILY REGISTER 10-3: R-0 BUSY bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh)(1) R/W-0 IRQM0 R/W-0 INCM1 R/W-0 INCM0 R/W-0 MODE16 R/W-0 MODE1 R/W-0 MODE0 bit 0 R/W-0 IRQM1 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy IRQM<1:0>: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated INCM<1:0>: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR<15,13:0> by 1 every read/write cycle 01 = Increment ADDR<15,13:0> by 1 every read/write cycle 00 = No increment or decrement of address MODE16: 8/16-Bit Mode bit 1 = 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers 0 = 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer MODE<1:0>: Parallel Port Mode Select bits 11 = Master Mode 1 (PMCS, PMRD/PMWR, PMENB, PMBE, PMA bit 6-5 bit 4-3 bit 2 bit 1-0 Note 1: DS39932C-page 168 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 10-4: R/W-0 WAITB1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown (2) PMMODEL: PARALLEL PORT MODE REGISTER LOW BYTE (BANKED F5Ch)(1) R/W-0 WAITM3 R/W-0 WAITM2 R/W-0 WAITM1 R/W-0 WAITM0 R/W-0 WAITE1 (2) R/W-0 WAITB0 (2) R/W-0 WAITE0(2) bit 0 WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(2) 11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY . . . 0001 = Wait of additional 1 TCY 0000 = No additional Wait cycles (operation forced into one TCY) WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(2) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY This register is only available in 44-pin devices. WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000. bit 5-2 bit 1-0 Note 1: 2: (c) 2009 Microchip Technology Inc. DS39932C-page 169 PIC18F46J11 FAMILY REGISTER 10-5: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h)(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R/W-0 PTEN14 Unimplemented: Read as `0' PTEN14: PMCS1 Port Enable bit 1 = PMCS1 chip select line 0 = PMCS1 functions as port I/O Unimplemented: Read as `0' This register is only available in 44-pin devices. bit 5-0 Note 1: REGISTER 10-6: R/W-0 PTEN7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 PMEL: PARALLEL PORT ENABLE REGISTER LOW BYTE (BANKED F56h)(1) R/W-0 PTEN5 R/W-0 PTEN4 R/W-0 PTEN3 R/W-0 PTEN2 R/W-0 PTEN1 R/W-0 PTEN0 bit 0 R/W-0 PTEN6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PTEN<7:2>: PMP Address Port Enable bits 1 = PMA<7:2> function as PMP address lines 0 = PMA<7:2> function as port I/O PTEN<1:0>: PMALH/PMALL Strobe Enable bits 1 = PMA<1:0> function as either PMA<1:0> or PMALH and PMALL 0 = PMA<1:0> pads functions as port I/O This register is only available in 44-pin devices. bit 1-0 Note 1: DS39932C-page 170 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 10-7: R-0 IBF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PMSTATH: PARALLEL PORT STATUS REGISTER HIGH BYTE (BANKED F55h)(1) U-0 -- U-0 -- R-0 IB3F R-0 IB2F R-0 IB1F R-0 IB0F bit 0 R/W-0 IBOV IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred Unimplemented: Read as `0' IB3F:IB0F: Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data This register is only available in 44-pin devices. bit 6 bit 5-4 bit 3-0 Note 1: REGISTER 10-8: R-1 OBE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 PMSTATL: PARALLEL PORT STATUS REGISTER LOW BYTE (BANKED F54h)(1) U-0 -- U-0 -- R-1 OB3E R-1 OB2E R-1 OB1E R-1 OB0E bit 0 R/W-0 OBUF W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as `0' OB3E:OB0E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted This register is only available in 44-pin devices. bit 6 bit 5-4 bit 3-0 Note 1: (c) 2009 Microchip Technology Inc. DS39932C-page 171 PIC18F46J11 FAMILY 10.1.2 DATA REGISTERS The PMP module uses eight registers for transferring data into and out of the microcontroller. They are arranged as four pairs to allow the option of 16-bit data operations: * * * * PMDIN1H and PMDIN1L PMDIN2H and PMDIN2L PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L PMDOUT2H and PMDOUT2L PMADDRH differs from PMADDRL in that it can also have limited PMP control functions. When the module is operating in select Master mode configurations, the upper two bits of the register can be used to determine the operation of chip select signals. If these are not used, PMADDR simply functions to hold the upper 8 bits of the address. Register 10-9 provides the function of the individual bits in PMADDRH. The PMDOUT2H and PMDOUT2L registers are only used in Buffered Slave modes and serve as a buffer for outgoing data. The PMDIN1 register is used for incoming data in Slave modes and both input and output data in Master modes. The PMDIN2 register is used for buffering input data in select Slave modes. The PMADDR/PMDOUT1 registers are actually a single register pair; the name and function are dictated by the module's operating mode. In Master modes, the registers function as the PMADDRH and PMADDRL registers and contain the address of any incoming or outgoing data. In Slave modes, the registers function as PMDOUT1H and PMDOUT1L and are used for outgoing data. 10.1.3 PAD CONFIGURATION CONTROL REGISTER In addition to the module level configuration options, the PMP module can also be configured at the I/O pin for electrical operation. This option allows users to select either the normal Schmitt Trigger input buffer on digital I/O pins shared with the PMP, or use TTL level compatible buffers instead. Buffer configuration is controlled by the PMPTTL bit in the PADCFG1 register. DS39932C-page 172 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 10-9: R/W-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared r = Reserved x = Bit is unknown PMADDRH: PARALLEL PORT ADDRESS REGISTER HIGH BYTE - MASTER MODES ONLY (ACCESS F6Fh)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 CS1 Parallel Master Port Address High Byte<13:8> R/W-0 Unimplemented: Read as `0' CS1: Chip Select bit If PMCON<7:6> = 10: 1 = Chip select is active 0 = Chip select is inactive If PMCON<7:6> = 11 or 00: Bit functions as ADDR<14>. Parallel Master Port Address: High Byte<13:8> bits In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers. bit 5-0 Note 1: REGISTER 10-10: PMADDRL: PARALLEL PORT ADDRESS REGISTER LOW BYTE - MASTER MODES ONLY (ACCESS F6Eh)(1) R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared r = Reserved x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 Parallel Master Port Address Low Byte<7:0> Parallel Master Port Address: Low Byte<7:0> bits In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers. (c) 2009 Microchip Technology Inc. DS39932C-page 173 PIC18F46J11 FAMILY 10.2 Slave Port Modes The primary mode of operation for the module is configured using the MODE<1:0> bits in the PMMODEH register. The setting affects whether the module acts as a slave or a master, and it determines the usage of the control pins. pins dedicated to the module. In this mode, an external device, such as another microcontroller or microprocessor, can asynchronously read and write data using the 8-bit data bus (PMD<7:0>), the read (PMRD), write (PMWR) and chip select (PMCS1) inputs. It acts as a slave on the bus and responds to the read/write control signals. Figure 10-2 displays the connection of the PSP. When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into the PMDIN1L register. 10.2.1 LEGACY MODE (PSP) In Legacy mode (PMMODEH<1:0> = 00 and PMPEN = 1), the module is configured as a Parallel Slave Port (PSP) with the associated enabled module FIGURE 10-2: Master LEGACY PARALLEL SLAVE PORT EXAMPLE PIC18 Slave PMD<7:0> PMCS PMRD PMWR Address Bus Data Bus Control Lines PMD<7:0> PMCS1 PMRD PMWR DS39932C-page 174 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 10.2.2 WRITE TO SLAVE PORT 10.2.3 READ FROM SLAVE PORT When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into the lower PMDIN1L register. The PMPIF and IBF flag bits are set when the write ends.The timing for the control signals in Write mode is displayed in Figure 10-3. The polarity of the control signals are configurable. When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from the PMDOUT1L register (PMDOUT1L<7:0>) is presented onto PMD<7:0>. Figure 10-4 provides the timing for the control signals in Read mode. FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS1 PMWR PMRD PMD<7:0> IBF OBE PMPIF FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS1 PMWR PMRD PMD<7:0> IBF OBE PMPIF (c) 2009 Microchip Technology Inc. DS39932C-page 175 PIC18F46J11 FAMILY 10.2.4 BUFFERED PARALLEL SLAVE PORT MODE 10.2.4.2 WRITE TO SLAVE PORT Buffered Parallel Slave Port mode is functionally identical to the legacy PSP mode with one exception, the implementation of 4-level read and write buffers. Buffered PSP mode is enabled by setting the INCM bits in the PMMODEH register. If the INCM<1:0> bits are set to `11', the PMP module will act as the Buffered PSP. When the Buffered mode is active, the PMDIN1L, PMDIN1H, PMDIN2L and PMDIN2H registers become the write buffers and the PMDOUT1L, PMDOUT1H, PMDOUT2L and PMDOUT2H registers become the read buffers. Buffers are numbered 0 through 3, starting with the lower byte of PMDIN1L to PMDIN2H as the read buffers and PMDOUT1L to PMDOUT2H as the write buffers. For write operations, the data has to be stored sequentially, starting with Buffer 0 (PMDIN1L<7:0>) and ending with Buffer 3 (PMDIN2H<7:0>). As with read operations, the module maintains an internal pointer to the buffer that is to be written next. The input buffers have their own write status bits, IBxF in the PMSTATH register. The bit is set when the buffer contains unread incoming data, and cleared when the data has been read. The flag bit is set on the write strobe. If a write occurs on a buffer when its associated IBxF bit is set, the Buffer Overflow flag, IBOV, is set; any incoming data in the buffer will be lost. If all four IBxF flags are set, the Input Buffer Full Flag (IBF) is set. In Buffered Slave mode, the module can be configured to generate an interrupt on every read or write strobe (IRQM<1:0> = 01). It can be configured to generate an interrupt on a read from Read Buffer 3 or a write to Write Buffer 3, which is essentially an interrupt every fourth read or write strobe (RQM<1:0> = 11). When interrupting every fourth byte for input data, all input buffer registers should be read to clear the IBxF flags. If these flags are not cleared, then there is a risk of hitting an overflow condition. 10.2.4.1 READ FROM SLAVE PORT For read operations, the bytes will be sent out sequentially, starting with Buffer 0 (PMDOUT1L<7:0>) and ending with Buffer 3 (PMDOUT2H<7:0>) for every read strobe. The module maintains an internal pointer to keep track of which buffer is to be read. Each buffer has a corresponding read status bit, OBxE, in the PMSTATL register. This bit is cleared when a buffer contains data that has not been written to the bus, and is set when data is written to the bus. If the current buffer location being read from is empty, a buffer underflow is generated, and the Buffer Overflow flag bit, OBUF, is set. If all four OBxE status bits are set, then the Output Buffer Empty flag (OBE) will also be set. FIGURE 10-5: PARALLEL MASTER/SLAVE CONNECTION BUFFERED EXAMPLE Master PMD<7:0> PMD<7:0> Write Address Pointer PIC18 Slave Read Address Pointer PMDOUT1L (0) PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) PMCS1 PMRD PMWR PMCS PMRD PMWR PMDOUT1H (1) PMDOUT2L (2) PMDOUT2H (3) Data Bus Control Lines DS39932C-page 176 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 10.2.5 In the ADDRESSABLE PARALLEL SLAVE PORT MODE Addressable Parallel Slave Port mode TABLE 10-1: SLAVE MODE BUFFER ADDRESSING Output Register (Buffer) PMDOUT1L (0) PMDOUT1H (1) PMDOUT2L (2) PMDOUT2H((3) Input Register (Buffer) PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) (PMMODEH<1:0> = 01), the module is configured with two extra inputs, PMA<1:0>, which are the address lines 1 and 0. This makes the 4-byte buffer space directly addressable as fixed pairs of read and write buffers. As with Legacy Buffered mode, data is output from PMDOUT1L, PMDOUT1H, PMDOUT2L and PMDOUT2H, and is read in on PMDIN1L, PMDIN1H, PMDIN2L and PMDIN2H. Table 10-1 provides the buffer addressing for the incoming address to the input and output registers. PMA<1:0> 00 01 10 11 FIGURE 10-6: Master PMA<1:0> PARALLEL MASTER/SLAVE CONNECTION ADDRESSED BUFFER EXAMPLE PMA<1:0> PMD<7:0> Write Address Decode PMDOUT1L (0) PIC18F Slave PMD<7:0> Read Address Decode PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) PMCS1 PMRD PMWR Address Bus Data Bus Control Lines PMCS PMRD PMWR PMDOUT1H (1) PMDOUT2L (2) PMDOUT2H (3) 10.2.5.1 READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from one of the four output bytes is presented onto PMD<7:0>. Which byte is read depends on the 2-bit address placed on ADDR<1:0>. Table 10-1 provides the corresponding output registers and their associated address. When an output buffer is read, the corresponding OBxE bit is set. The OBxE flag bit is set when all the buffers are empty. If any buffer is already empty, OBxE = 1, the next read to that buffer will generate an OBUF event. FIGURE 10-7: PARALLEL SLAVE PORT READ WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD<7:0> PMA<1:0> OBE PMPIF (c) 2009 Microchip Technology Inc. DS39932C-page 177 PIC18F46J11 FAMILY 10.2.5.2 WRITE TO SLAVE PORT When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into one of the four input buffer bytes. Which byte is written depends on the 2-bit address placed on ADDRL<1:0>. Table 10-1 provides the corresponding input registers and their associated address. When an input buffer is written, the corresponding IBxF bit is set. The IBF flag bit is set when all the buffers are written. If any buffer is already written (IBxF = 1), the next write strobe to that buffer will generate an OBUF event and the byte will be discarded. FIGURE 10-8: PARALLEL SLAVE PORT WRITE WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD<7:0> PMA<1:0> IBF PMPIF DS39932C-page 178 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 10.3 MASTER PORT MODES In its Master modes, the PMP module provides an 8-bit data bus, up to 16 bits of address, and all the necessary control signals to operate a variety of external parallel devices, such as memory devices, peripherals and slave microcontrollers. To use the PMP as a master, the module must be enabled (PMPEN = 1) and the mode must be set to one of the two possible Master modes (PMMODEH<1:0> = 10 or 11). Because there are a number of parallel devices with a variety of control methods, the PMP module is designed to be extremely flexible to accommodate a range of configurations. Some of these features include: * * * * * * * 8-Bit and 16-Bit Data modes on an 8-bit data bus Configurable address/data multiplexing Up to two chip select lines Up to 16 selectable address lines Address auto-increment and auto-decrement Selectable polarity on all control lines Configurable Wait states at different stages of the read/write cycle Note that the polarity of control signals that share the same output pin (for example, PMWR and PMENB) are controlled by the same bit; the configuration depends on which Master Port mode is being used. 10.3.3 DATA WIDTH The PMP supports data widths of both 8 bits and 16 bits. The data width is selected by the MODE16 bit (PMMODEH<2>). Because the data path into and out of the module is only 8 bits wide, 16-bit operations are always handled in a multiplexed fashion, with the Least Significant Byte (LSB) of data being presented first. To differentiate data bytes, the byte enable control strobe, PMBE, is used to signal when the Most Significant Byte (MSB) of data is being presented on the data lines. 10.3.4 ADDRESS MULTIPLEXING 10.3.1 PMP AND I/O PIN CONTROL In either of the Master modes (PMMODEH<1:0> = 1x), the user can configure the address bus to be multiplexed together with the data bus. This is accomplished by using the ADRMUX<1:0> bits (PMCONH<4:3>). There are three address multiplexing modes available; typical pinout configurations for these modes are displayed in Figure 10-9, Figure 10-10 and Figure 10-11. In Demultiplexed mode (PMCONH<4:3> = 00), data and address information are completely separated. Data bits are presented on PMD<7:0> and address bits are presented on PMADDRH<6:0> and PMADDRL<7:0>. In Partially Multiplexed mode (PMCONH<4:3> = 01), the lower eight bits of the address are multiplexed with the data pins on PMD<7:0>. The upper eight bits of address are unaffected and are presented on PMADDRH<6:0>. The PMA0 pin is used as an address latch, and presents the address latch low enable strobe (PMALL). The read and write sequences are extended by a complete CPU cycle during which the address is presented on the PMD<7:0> pins. In Fully Multiplexed mode (PMCONH<4:3> = 10), the entire 16 bits of the address are multiplexed with the data pins on PMD<7:0>. The PMA0 and PMA1 pins are used to present address latch low enable (PMALL) and address latch high enable (PMALH) strobes, respectively. The read and write sequences are extended by two complete CPU cycles. During the first cycle, the lower eight bits of the address are presented on the PMD<7:0> pins with the PMALL strobe active. During the second cycle, the upper eight bits of the address are presented on the PMD<7:0> pins with the PMALH strobe active. In the event the upper address bits are configured as chip select pins, the corresponding address bits are automatically forced to `0'. Multiple control bits are used to configure the presence or absence of control and address signals in the module. These bits are PTBEEN, PTWREN, PTRDEN and PTEN<15:0>. They give the user the ability to conserve pins for other functions and allow flexibility to control the external address. When any one of these bits is set, the associated function is present on its associated pin; when clear, the associated pin reverts to its defined I/O port function. Setting a PTENx bit will enable the associated pin as an address pin and drive the corresponding data contained in the PMADDR register. Clearing a PTENx bit will force the pin to revert to its original I/O function. For the pins configured as chip select (PMCS1 or PMCS2) with the corresponding PTENx bit set, the PTEN0 and PTEN1 bits will also control the PMALL and PMALH signals. When multiplexing is used, the associated address latch signals should be enabled. 10.3.2 READ/WRITE CONTROL The PMP module supports two distinct read/write signaling methods. In Master Mode 1, read and write strobes are combined into a single control line, PMRD/PMWR. A second control line, PMENB, determines when a read or write action is to be taken. In Master Mode 2, separate read and write strobes (PMRD and PMWR) are supplied on separate pins. All control signals (PMRD, PMAL and PMCSx) can be either positive or negative controlled by separate bits PMWR, PMBE, PMENB, individually configured as polarity. Configuration is in the PMCONL register. (c) 2009 Microchip Technology Inc. DS39932C-page 179 PIC18F46J11 FAMILY FIGURE 10-9: DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F PMA<7:0> PMD<7:0> PMCS PMRD PMWR Address Bus Data Bus Control Lines FIGURE 10-10: PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F PMD<7:0> PMA<7:0> PMCS PMALL PMRD PMWR Address Bus Multiplexed Data and Address Bus Control Lines FIGURE 10-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F PMD<7:0> PMA<13:8> PMCS PMALL PMALH PMRD PMWR Multiplexed Data and Address Bus Control Lines DS39932C-page 180 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 10.3.5 CHIP SELECT FEATURES Up to two chip select lines, PMCS1 and PMCS2, are available for the Master modes of the PMP. The two chip select lines are multiplexed with the Most Significant bit (MSb) of the address bus (PMADDRH<6>). When a pin is configured as a chip select, it is not included in any address auto-increment/decrement. The function of the chip select signals is configured using the chip select function bits (PMCONL<7:6>). Note that the read data obtained from the PMDIN1L register is actually the read value from the previous read operation. Hence, the first user read will be a dummy read to initiate the first bus read and fill the read register. Also, the requested read value will not be ready until after the BUSY bit is observed low. Thus, in a back-to-back read operation, the data read from the register will be the same for both reads. The next read of the register will yield the new value. 10.3.6 AUTO-INCREMENT/DECREMENT 10.3.9 WRITE OPERATION While the module is operating in one of the Master modes, the INCMx bits (PMMODEH<4:3>) control the behavior of the address value. The address can be made to automatically increment or decrement after each read and write operation. The address increments once each operation is completed and the BUSY bit goes to `0'. If the chip select signals are disabled and configured as address bits, the bits will participate in the increment and decrement operations; otherwise, the CS1 bit values will be unaffected. To perform a write onto the parallel bus, the user writes to the PMDIN1L register. This causes the module to first output the desired values on the chip select lines and the address bus. The write data from the PMDIN1L register is placed onto the PMD<7:0> data bus. Then the write line (PMWR) is strobed. If the 16-bit mode is enabled (MODE16 = 1), the write to the PMDIN1L register will initiate two bus writes. First write will consist of the data contained in PMDIN1L and the second write will contain the PMDIN1H. 10.3.7 WAIT STATES 10.3.10 10.3.10.1 PARALLEL MASTER PORT STATUS The BUSY Bit In Master mode, the user has control over the duration of the read, write and address cycles by configuring the module Wait states. Three portions of the cycle, the beginning, middle and end, are configured using the corresponding WAITBx, WAITMx and WAITEx bits in the PMMODEL register. The WAITBx bits (PMMODEL<7:6>) set the number of Wait cycles for the data setup prior to the PMRD/PMWT strobe in Mode 10, or prior to the PMENB strobe in Mode 11. The WAITMx bits (PMMODEL<5:2>) set the number of Wait cycles for the PMRD/PMWT strobe in Mode 10, or for the PMENB strobe in Mode 11. When this Wait state setting is `0', then WAITB and WAITE have no effect. The WAITE bits (PMMODEL<1:0>) define the number of Wait cycles for the data hold time after the PMRD/PMWT strobe in Mode 10, or after the PMENB strobe in Mode 11. In addition to the PMP interrupt, a BUSY bit is provided to indicate the status of the module. This bit is used only in Master mode. While any read or write operation is in progress, the BUSY bit is set for all but the very last CPU cycle of the operation. In effect, if a single-cycle read or write operation is requested, the BUSY bit will never be active. This allows back-to-back transfers. While the bit is set, any request by the user to initiate a new operation will be ignored (i.e., writing or reading the lower byte of the PMDIN1L register will neither initiate a read nor a write). 10.3.10.2 Interrupts When the PMP module interrupt is enabled for Master mode, the module will interrupt on every completed read or write cycle; otherwise, the BUSY bit is available to query the status of the module. 10.3.8 READ OPERATION To perform a read on the PMP, the user reads the PMDIN1L register. This causes the PMP to output the desired values on the chip select lines and the address bus. Then the read line (PMRD) is strobed. The read data is placed into the PMDIN1L register. If the 16-bit mode is enabled (MODE16 = 1), the read of the low byte of the PMDIN1L register will initiate two bus reads. The first read data byte is placed into the PMDIN1L register, and the second read data is placed into the PMDIN1H. (c) 2009 Microchip Technology Inc. DS39932C-page 181 PIC18F46J11 FAMILY 10.3.11 MASTER MODE TIMING This section contains a number of timing examples that represent the common Master mode configuration options. These options vary from 8-bit to 16-bit data, fully demultiplexed to fully multiplexed address and Wait states. FIGURE 10-12: READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMA<7:0> PMWR PMRD PMPIF BUSY FIGURE 10-13: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMWR PMRD PMALL PMPIF BUSY Address<7:0> Data FIGURE 10-14: READ TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - PMCS1 PMD<7:0> PMRD PMWR PMALL PMPIF BUSY WAITB<1:0> = 01 WAITE<1:0> = 00 WAITM<3:0> = 0010 Address<7:0> Data DS39932C-page 182 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 10-15: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMWR PMRD PMALL PMPIF BUSY Address<7:0> Data FIGURE 10-16: WRITE TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - PMCS1 PMD<7:0> PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> = 01 WAITE<1:0> = 00 WAITM<3:0> = 0010 Address<7:0> Data FIGURE 10-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY Address<7:0> Data (c) 2009 Microchip Technology Inc. DS39932C-page 183 PIC18F46J11 FAMILY FIGURE 10-18: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY Address<7:0> Data FIGURE 10-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY Address<7:0> Address<13:8> Data FIGURE 10-20: WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY Address<7:0> Address<13:8> Data DS39932C-page 184 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 10-21: READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMA<7:0> PMWR PMRD PMBE PMPIF BUSY LSB MSB FIGURE 10-22: WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMA<7:0> PMWR PMRD PMBE PMPIF BUSY LSB MSB FIGURE 10-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY Address<7:0> LSB MSB (c) 2009 Microchip Technology Inc. DS39932C-page 185 PIC18F46J11 FAMILY FIGURE 10-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY Address<7:0> LSB MSB FIGURE 10-25: READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF BUSY Address<7:0> Address<13:8> LSB MSB FIGURE 10-26: WRITE TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF BUSY Address<7:0> Address<13:8> LSB MSB DS39932C-page 186 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 10.4 Application Examples 10.4.1 This section introduces some potential applications for the PMP module. MULTIPLEXED MEMORY OR PERIPHERAL Figure 10-27 demonstrates the hookup of a memory or another addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective. However, for this configuration, there needs to be some external latches to maintain the address. FIGURE 10-27: EXAMPLE - MULTIPLEXED ADDRESSING APPLICATION 373 A<7:0> D<7:0> A<15:8> A<13:0> D<7:0> CE OE WR Address Bus Data Bus Control Lines PIC18F PMD<7:0> PMALL PMALH PMCS PMRD PMWR 373 10.4.2 PARTIALLY MULTIPLEXED MEMORY OR PERIPHERAL Partial multiplexing implies using more pins; however, for a few extra pins, some extra performance can be achieved. Figure 10-28 provides an example of a memory or peripheral that is partially multiplexed with an external latch. If the peripheral has internal latches, as displayed in Figure 10-29, then no extra circuitry is required except for the peripheral itself. FIGURE 10-28: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION 373 A<7:0> D<7:0> A<7:0> D<7:0> CE OE WR Address Bus Data Bus Control Lines PIC18F PMD<7:0> PMALL PMCS PMRD PMWR FIGURE 10-29: PIC18F EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION Parallel Peripheral AD<7:0> ALE CS RD WR Address Bus Data Bus Control Lines PMD<7:0> PMALL PMCS PMRD PMWR (c) 2009 Microchip Technology Inc. DS39932C-page 187 PIC18F46J11 FAMILY 10.4.3 PARALLEL EEPROM EXAMPLE Figure 10-30 provides an example connecting parallel EEPROM to the PMP. Figure 10-31 demonstrates a slight variation to this, configuring the connection for 16-bit data from a single EEPROM. FIGURE 10-30: PIC18F PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA) Parallel EEPROM A PMA FIGURE 10-31: PIC18F PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA) Parallel EEPROM A PMA 10.4.4 LCD CONTROLLER EXAMPLE The PMP module can be configured to connect to a typical LCD controller interface, as displayed in Figure 10-32. In this case, the PMP module is configured for active-high control signals since common LCD displays require active-high control. FIGURE 10-32: PIC18F LCD CONTROL EXAMPLE (BYTE MODE OPERATION) LCD Controller D<7:0> RS R/W E PM<7:0> PMA0 PMRD/PMWR PMCS Address Bus Data Bus Control Lines DS39932C-page 188 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 10-2: Name INTCON PIR1 PIE1 IPR1 PMCONH(2) PMCONL(2) PMADDRH(1,2) / REGISTERS ASSOCIATED WITH PMP MODULE Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TX1IF TX1IE TX1IP -- Bit 3 RBIE SSP1IF SSP1IE SSP1IP CS1P Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP PTBEEN BEP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP PTWREN WRSP Bit 0 RBIF TMR1IF TMR1IE TMR1IP PTRDEN RDSP Reset Values on Page: 63 65 65 65 67 67 67 67 67 67 67 67 67 67 67 67 INCM0 WAITM1 -- PTEN3 IB3F OB3E -- MODE16 WAITM0 -- PTEN2 IB2F OB2E MODE1 WAITE1 -- PTEN1 IB1F OB1E MODE0 WAITE0 -- PTEN0 IB0F OB0E 67 67 68 68 68 68 68 GIE/GIEH PEIE/GIEL TMR0IE PMPIF(2) PMPIE(2) PMPIP (2) ADIF ADIE ADIP -- CSF0 CS1 RC1IF RC1IE RC1IP PSIDL ALP PMPEN CSF1 -- ADRMUX1 ADRMUX0 Parallel Master Port Address High Byte PMDOUT1H(1,2) Parallel Port Out Data High Byte (Buffer 1) PMADDRL(1,2)/ PMDOUT2H(2) PMDOUT2L PMDIN1L(2) PMDIN2H(2) PMDIN2L(2) PMMODEH(2) PMMODEL(2) PMEH(2) PMEL(2) PMSTATH(2) PMSTATL(2) PADCFG1 Legend: Note 1: 2: (2) Parallel Master Port Address Low Byte Parallel Port Out Data High Byte (Buffer 3) Parallel Port Out Data Low Byte (Buffer 2) Parallel Port In Data High Byte (Buffer 1) Parallel Port In Data Low Byte (Buffer 0) Parallel Port In Data High Byte (Buffer 3) Parallel Port In Data Low Byte (Buffer 2) BUSY WAITB1 -- PTEN7 IBF OBE -- IRQM1 WAITB0 PTEN14 PTEN6 IBOV OBUF -- IRQM0 WAITM3 -- PTEN5 -- -- -- INCM1 WAITM2 -- PTEN4 -- -- -- PMDOUT1L(1,2) Parallel Port Out Data Low Byte (Buffer 0) PMDIN1H(2) RTSECSEL1 RTSECSEL0 PMPTTL -- = unimplemented, read as `0'. Shaded cells are not used during PMP operation. The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module's operating mode. These bits and/or registers are only available in 44-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 189 PIC18F46J11 FAMILY NOTES: DS39932C-page 190 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 11.0 TIMER0 MODULE The Timer0 module incorporates the following features: * Software selectable operation as a timer or counter in both 8-bit or 16-bit modes * Readable and writable registers * Dedicated 8-bit, software programmable prescaler * Selectable clock source (internal or external) * Edge select for external clock * Interrupt-on-overflow The T0CON register (Register 11-1) controls all aspects of the module's operation, including the prescale selection. It is both readable and writable. Figure 11-1 provides a simplified block diagram of the Timer0 module in 8-bit mode. Figure 11-2 provides a simplified block diagram of the Timer0 module in 16-bit mode. REGISTER 11-1: R/W-1 TMR0ON bit 7 Legend: R = Readable bit -n = Value at POR bit 7 T0CON: TIMER0 CONTROL REGISTER (ACCESS FD5h) R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0 R/W-1 T08BIT W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = Timer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value bit 6 bit 5 bit 4 bit 3 bit 2-0 (c) 2009 Microchip Technology Inc. DS39932C-page 191 PIC18F46J11 FAMILY 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 "Prescaler"). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The Counter mode is selected by setting the T0CS bit (= 1). In this mode, Timer0 increments either on every rising edge or falling edge of pin, T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. An external clock source can be used to drive Timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. 11.2 Timer0 Reads and Writes in 16-Bit Mode TMR0H is not the actual high byte of Timer0 in 16-bit mode. It is actually a buffered version of the real high byte of Timer0, which is not directly readable nor writable (refer to Figure 11-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 1 Sync with Internal Clocks (2 TCY Delay) 8 8 Internal Data Bus TMR0L Set TMR0IF on Overflow T0CKI pin T0SE T0CS T0PS<2:0> PSA Programmable Prescaler 3 0 Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 11-2: FOSC/4 TIMER0 BLOCK DIAGRAM (16-BIT MODE) 0 1 1 Sync with Internal Clocks (2 TCY Delay) Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus TMR0L TMR0 High Byte 8 Set TMR0IF on Overflow T0CKI pin T0SE T0CS T0PS<2:0> PSA Programmable Prescaler 3 0 Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39932C-page 192 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 11.3 Prescaler 11.3.1 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>), which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, etc.) clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed "on-the-fly" during program execution. 11.4 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit (INTCON<5>). Before re-enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine (ISR). Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep. TABLE 11-1: Name TMR0L TMR0H INTCON T0CON REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: 84 84 INT0IE T0SE RBIE PSA TMR0IF T0PS2 INT0IF T0PS1 RBIF T0PS0 83 84 T0CS Timer0 Register Low Byte Timer0 Register High Byte GIE/GIEH PEIE/GIEL TMR0IE TMR0ON T08BIT Legend: -- = unimplemented, read as `0'. Shaded cells are not used by Timer0. (c) 2009 Microchip Technology Inc. DS39932C-page 193 PIC18F46J11 FAMILY NOTES: DS39932C-page 194 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 12.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable 8-bit registers (TMR1H and TMR1L) * Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options * Interrupt-on-overflow * Reset on ECCP Special Event Trigger * Device clock status flag (T1RUN) * Timer with gated control Figure 12-1 displays a simplified block diagram of the Timer1 module. The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. Timer1 is controlled through the T1CON Control register (Register 12-1). It also contains the Timer1 oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). The FOSC clock source (TMR1CS<1:0> = 01) should not be used with the ECCP capture/compare features. If the timer will be used with the capture or compare features, always select one of the other timer clocking options. REGISTER 12-1: R/W-0 TMR1CS1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 T1CON: TIMER1 CONTROL REGISTER (ACCESS FCDh) R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 RD16 R/W-0 TMR1ON bit 0 R/W-0 TMR1CS0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR1CS<1:0>: Timer1 Clock Source Select bits 10 = Timer1 clock source is T1OSC or T1CKI pin 01 = Timer1 clock source is system clock (FOSC)(1) 00 = Timer1 clock source is instruction clock (FOSC/4) T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Crystal Oscillator Enable bit 1 = Timer1 oscillator circuit enabled 0 = Timer1 oscillator circuit disabled The oscillator inverter and feedback resistor are turned off to eliminate power drain. T1SYNC: Timer1 External Clock Input Synchronization Select bit TMR1CS<1:0> = 10: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS<1:0> = 0x: This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 0x. RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features. DS39932C-page 195 bit 5-4 bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 12.1 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), displayed in Register 12-2, is used to control the Timer1 gate. REGISTER 12-2: R/W-0 TMR1GE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 T1GCON: TIMER1 GATE CONTROL REGISTER (F9Ah)(1) R/W-0 T1GTM R/W-0 T1GSPM R/W-0 T1GGO/T1DONE R-x T1GVAL R/W-0 T1GSS1 R/W-0 T1GSS0 bit 0 R/W-0 T1GPOL W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored. If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. T1GSPM: Timer1 Gate Single Pulse Mode bit 1 = Timer1 Gate Single Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single Pulse mode is disabled T1GGO/T1DONE: Timer1 Gate Single Pulse Acquisition Status bit 1 = Timer1 gate single pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L; unaffected by Timer1 Gate Enable (TMR1GE) bit. T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 gate pin 01 = Timer0 overflow output 10 = TMR2 to match PR2 output Programming the T1GCON prior to T1CON is recommended. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: DS39932C-page 196 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 12-3: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TCLKCON: TIMER CLOCK CONTROL REGISTER (BANKED F52h) U-0 -- U-0 -- R-0 T1RUN U-0 -- U-0 -- R/W-0 T3CCP2 R/W-0 T3CCP1 bit 0 Unimplemented: Read as `0' T1RUN: Timer1 Run Status bit 1 = Device is currently clocked by T1OSC/T1CKI 0 = System clock comes from an oscillator other than T1OSC/T1CKI Unimplemented: Read as `0' T3CCP<2:1>: ECCP Timer Assignment bits 10 = ECCP1 and ECCP2 both use Timer3 (capture/compare) and Timer4 (PWM) 01 = ECCP1 uses Timer1 (compare/capture) and Timer2 (PWM); ECCP2 uses Timer3 (capture/compare) and Timer4 (PWM) 00 = ECCP1 and ECCP2 both use Timer1 (capture/compare) and Timer2 (PWM) bit 3-2 bit 1-0 (c) 2009 Microchip Technology Inc. DS39932C-page 197 PIC18F46J11 FAMILY 12.2 Timer1 Operation 12.3.2 EXTERNAL CLOCK SOURCE The Timer1 module is an 8-bit or 16-bit incrementing counter, which is accessed through the TMR1H:TMR1L register pair. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. When Timer1 is enabled, the RC1/T1OSI/RP12 and RC0/T1OSO/T1CKI/RP11 pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as `0'. When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input, T1CKI, or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: * Timer1 enabled after POR Reset * Write to TMR1H or TMR1L * Timer1 is disabled * Timer1 is disabled (TMR1ON = 0) when T1CKI is high, then Timer1 is enabled (TMR1ON = 1) when T1CKI is low. 12.3 Clock Source Selection The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Register 12-1 displays the clock source selections. 12.3.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. TABLE 12-1: TMR1CS1 0 0 1 1 TIMER1 CLOCK SOURCE SELECTION TMR1CS0 1 0 0 0 T1OSCEN x x 0 1 Clock Source Clock Source (FOSC) Instruction Clock (FOSC/4) External Clock on T1CKI Pin Oscillator Circuit on T1OSI/T1OSO Pin DS39932C-page 198 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 12-1: T1GSS<1:0> T1G From Timer0 Overflow From Timer2 Match PR2 00 01 10 D TMR1ON T1GPOL Set Flag bit TMR1IF on Overflow T1GTM TMR1GE TMR1ON TMR1(2) TMR1H TMR1L Q EN D T1CLK Synchronized Clock Input CK R Q Q 1 T1G_IN T1GSPM 0 0 Single Pulse Acq. Control T1GGO/T1DONE 1 Data Bus D EN Q RD T1GCON Set RTCCIF TIMER1 BLOCK DIAGRAM T1GVAL Q1 Interrupt det 0 1 TMR1CS<1:0> T1OSO/T1CKI OUT T1OSC T1OSI EN 0 T1OSCEN (1) T1SYNC Synchronize(3) det 1 10 FOSC Internal Clock FOSC/4 Internal Clock 01 Prescaler 1, 2, 4, 8 2 T1CKPS<1:0> FOSC/2 Internal Clock Sleep Input 00 T1CKI Note 1: 2: 3: ST Buffer is high-speed type when using T1CKI. Timer1 register increments on rising edge. Synchronize does not operate while in Sleep. (c) 2009 Microchip Technology Inc. DS39932C-page 199 PIC18F46J11 FAMILY 12.4 Timer1 16-Bit Read/Write Mode TABLE 12-2: Timer1 can be configured for 16-bit reads and writes. When the RD16 control bit (T1CON<1>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L loads the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(2,3,4,5) Freq. 32 kHz C1 12 pF(1) C2 12 pF(1) Oscillator Type LP Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. Values listed would be typical of a CL = 10 pF rated crystal, when LPT1OSC = 1. 5: Incorrect capacitance value may result in a frequency not meeting the crystal manufacturer's tolerance specification. The Timer1 crystal oscillator drive level is determined based on the LPT1OSC (CONFIG2L<4>) Configuration bit. The higher drive level mode, LPT1OSC = 1, is intended to drive a wide variety of 32.768 kHz crystals with a variety of load capacitance (CL) ratings. The lower drive level mode is highly optimized for extremely low-power consumption. It is not intended to drive all types of 32.768 kHz crystals. In the low drive level mode, the crystal oscillator circuit may not work if excessively large discrete capacitors are placed on the T1OSI and T1OSO pins. This mode is only designed to work with discrete capacitances of approximately 3 pF-10 pF on each pin. Crystal manufacturers usually specify a CL (load capacitance) rating for their crystals. This value is related to, but not necessarily the same as, the values that should be used for C1 and C2 in Figure 12-2. See the crystal manufacturer's applications' information for more details on how to select the optimum C1 and C2 for a given crystal. The optimum value depends in part on the amount of parasitic capacitance in the circuit, which is often unknown. Therefore, after values have been selected, it is highly recommended that thorough testing and validation of the oscillator be performed. 12.5 Timer1 Oscillator An on-chip crystal oscillator circuit is incorporated between pins, T1OSI (input) and T1OSO (amplifier output). It is enabled by setting the Timer1 Oscillator Enable bit, T1OSCEN (T1CON<3>). The oscillator is a low-power circuit rated for 32 kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical LP oscillator is depicted in Figure 12-2. Table 12-2 provides the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. FIGURE 12-2: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR PIC18F46J11 T1OSI XTAL 32.768 kHz T1OSO C1 12 pF C2 12 pF Note: See the Notes with Table 12-2 for additional information about capacitor selection. DS39932C-page 200 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 12.5.1 USING TIMER1 AS A CLOCK SOURCE FIGURE 12-3: The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select bits, SCS<1:0> (OSCCON<1:0>), to `01', the device switches to SEC_RUN mode; both the CPU and peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE mode. Additional details are available in Section 3.0 "Low-Power Modes". Whenever the Timer1 oscillator is providing the clock source, the Timer1 system clock status flag, T1RUN (TCLKCON<4>), is set. This can be used to determine the controller's current clocking mode. It can also indicate the clock source currently being used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING VDD VSS OSC1 OSC2 RC0 RC1 RC2 Note: Not drawn to scale. 12.5.2 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. This is especially true when the oscillator is configured for extremely low power mode (LPT1OSC = 0). The oscillator circuit, displayed in Figure 12-2, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator (such as the ECCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as displayed in Figure 12-3, may be helpful when used on a single-sided PCB or in addition to a ground plane. In the low drive level mode, LPT1OSC = 0, it is critical that RC2 I/O pin signals be kept away from the oscillator circuit. Configuring RC2 as a digital output, and toggling it, can potentially disturb the oscillator circuit, even with relatively good PCB layout. If possible, it is recommended to either leave RC2 unused, or use it as an input pin with a slew rate limited signal source. If RC2 must be used as a digital output, it may be necessary to use the higher drive level oscillator mode (LPT1OSC = 1) with many PCB layouts. Even in the higher drive level mode, careful layout procedures should still be followed when designing the oscillator circuit. In addition to dV/dt induced noise considerations, it is also important to ensure that the circuit board is clean. Even a very small amount of conductive soldering flux residue can cause PCB leakage currents, which can overwhelm the oscillator circuit. 12.6 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). (c) 2009 Microchip Technology Inc. DS39932C-page 201 PIC18F46J11 FAMILY 12.7 Resetting Timer1 Using the ECCP Special Event Trigger 12.8.1 TIMER1 GATE COUNT ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 12-4 for timing details. If ECCP1 or ECCP2 is configured to use Timer1 and to generate a Special Event Trigger in Compare mode (CCPxM<3:0> = 1011), this signal will reset Timer3. The trigger from ECCP2 will also start an A/D conversion if the A/D module is enabled (see Section 17.3.4 "Special Event Trigger" for more information). The module must be configured as either a timer or a synchronous counter to take advantage of this feature. When used this way, the CCPRxH:CCPRxL register pair effectively becomes a Period register for Timer1. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take precedence. Note: The Special Event Trigger from the ECCPx module will not set the TMR1IF interrupt flag bit (PIR1<0>). TABLE 12-3: T1CLK TIMER1 GATE ENABLE SELECTIONS T1G 0 1 0 1 Timer1 Operation Counts Holds Count Holds Count Counts 0 0 1 1 T1GPOL 12.8 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using the Timer1 gate circuitry. This is also referred to as Timer1 gate count enable. The Timer1 gate can also be driven by multiple selectable sources. DS39932C-page 202 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 12-4: TMR1GE T1GPOL T1G_IN TIMER1 GATE COUNT ENABLE MODE T1CKI T1GVAL Timer1 N N+1 N+2 N+3 N+4 12.8.2 TIMER1 GATE SOURCE SELECTION 12.8.2.1 T1G Pin Gate Operation The Timer1 gate source can be selected from one of four different sources. Source selection is controlled by the T1GSSx bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 12.8.2.2 Timer0 Overflow Gate Operation TABLE 12-4: T1GSS<1:0> 00 01 10 TIMER1 GATE SOURCES Timer1 Gate Source Timer1 Gate Pin Overflow of Timer0 (TMR0 increments from FFh to 00h) TMR2 to Match PR2 (TMR2 increments to match PR2) When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 12.8.2.3 Timer2 Match Gate Operation The TMR2 register will increment until it matches the value in the PR2 register. On the very next increment cycle, TMR2 will be reset to 00h. When this Reset occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. (c) 2009 Microchip Technology Inc. DS39932C-page 203 PIC18F46J11 FAMILY 12.8.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 12-5 for timing details. The T1GVAL bit will indicate when the Toggled mode is active and the timer is counting. The Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. FIGURE 12-5: TMR1GE T1GPOL TIMER1 GATE TOGGLE MODE T1GTM T1G_IN T1CKI T1GVAL Timer1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 DS39932C-page 204 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 12.8.4 TIMER1 GATE SINGLE PULSE MODE When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/T1DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/T1DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/T1DONE bit is once again set in software. Clearing the T1GSPM bit of the T1GCON register will also clear the T1GGO/T1DONE bit. See Figure 12-6 for timing details. Enabling the Toggle mode and the Single Pulse mode, simultaneously, will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 12-7 for timing details. 12.8.5 TIMER1 GATE VALUE STATUS When the Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). FIGURE 12-6: TMR1GE T1GPOL T1GSPM T1GGO/ T1DONE T1G_IN TIMER1 GATE SINGLE PULSE MODE Set by Software Counting Enabled on Rising Edge of T1G Cleared by Hardware on Falling Edge of T1GVAL T1CKI T1GVAL Timer1 N N+1 N+2 Cleared by Software RTCCIF Cleared by Software Set by Hardware on Falling Edge of T1GVAL (c) 2009 Microchip Technology Inc. DS39932C-page 205 PIC18F46J11 FAMILY FIGURE 12-7: TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ T1DONE T1G_IN Set by Software Counting Enabled on Rising Edge of T1G Cleared by Hardware on Falling Edge of T1GVAL TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE T1CKI T1GVAL Timer1 N N+1 N+2 N+3 N+4 Cleared by Software RTCCIF Cleared by Software Set by Hardware on Falling Edge of T1GVAL TABLE 12-5: Name INTCON PIR1 PIE1 IPR1 TMR1L TMR1H T1CON T1GCON TCLKCON REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 TMR0IE RC1IF RC1IE RC1IP Bit 4 INT0IE TX1IF TX1IE TX1IP Bit 3 RBIE SSP1IF SSP1IE SSP1IP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Reset Values on Page: 83 85 85 85 84 84 RD16 T1GSS1 T3CCP2 TMR1ON T1GSS0 T3CCP1 84 85 87 T1GSPM T1RUN T1GGO/ T1DONE -- T1GVAL -- GIE/GIEH PEIE/GIEL PMPIF(1) PMPIE (1) ADIF ADIE ADIP PMPIP(1) Timer1 Register Low Byte Timer1 Register High Byte TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1GE -- T1GPOL -- T1GTM -- Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are only available in 44-pin devices. DS39932C-page 206 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 13.0 TIMER2 MODULE 13.1 Timer2 Operation The Timer2 module incorporates the following features: * 8-bit Timer and Period registers (TMR2 and PR2, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1, 1:4 and 1:16) * Software programmable postscaler (1:1 through 1:16) * Interrupt on TMR2 to PR2 match * Optional use as the shift clock for the MSSP modules The module is controlled through the T2CON register (Register 13-1) which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. A simplified block diagram of the module is shown in Figure 13-1. In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by-16 prescale options. These are selected by the prescaler control bits, T2CKPS<1:0> (T2CON<1:0>). The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section 13.2 "Timer2 Interrupt"). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. Both the prescaler and postscaler counters are cleared on the following events: * a write to the TMR2 register * a write to the T2CON register * any device Reset (Power-on Reset (POR), MCLR Reset, Watchdog Timer Reset (WDTR) or Brown-out Reset (BOR)) TMR2 is not cleared when T2CON is written. REGISTER 13-1: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3 T2CON: TIMER2 CONTROL REGISTER (ACCESS FCAh) R/W-0 T2OUTPS2 R/W-0 T2OUTPS1 R/W-0 T2OUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0 bit 0 R/W-0 T2OUTPS3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 bit 2 bit 1-0 (c) 2009 Microchip Technology Inc. DS39932C-page 207 PIC18F46J11 FAMILY 13.2 Timer2 Interrupt 13.3 Timer2 Output Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 Match Interrupt Flag, which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). A range of 16 postscaler options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). The unscaled output of TMR2 is available primarily to the ECCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP modules operating in SPI mode. Additional information is provided in Section 18.0 "Master Synchronous Serial Port (MSSP) Module". FIGURE 13-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 Postscaler T2OUTPS<3:0> T2CKPS<1:0> 2 Set TMR2IF TMR2 Output (to PWM or MSSPx) FOSC/4 1:1, 1:4, 1:16 Prescaler Reset TMR2 8 TMR2/PR2 Match Comparator PR2 8 8 Internal Data Bus TABLE 13-1: Name REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 6 Bit 5 TMR0IE RC1IF RC1IE RC1IP Bit 4 INT0IE TX1IF TX1IE TX1IP Bit 3 RBIE SSP1IF SSP1IE SSP1IP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Reset Values on Page: 83 85 85 85 84 T2CKPS1 T2CKPS0 84 84 Bit 7 INTCON GIE/GIEH PEIE/GIEL PIR1 PIE1 IPR1 TMR2 T2CON PR2 PMPIF(1) PMPIE(1) PMPIP(1) -- ADIF ADIE ADIP Timer2 Register T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON Timer2 Period Register Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module. Note 1: These bits are only available in 44-pin devices. DS39932C-page 208 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 14.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable 8-bit registers (TMR3H and TMR3L) * Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options * Interrupt-on-overflow * Module Reset on ECCP Special Event Trigger A simplified block diagram of the Timer3 module is shown in Figure 14-1. The Timer3 module is controlled through the T3CON register (Register 14-1). It also selects the clock source options for the ECCP modules; see Section 17.1.1 "ECCP Module and Timer Resources" for more information. The FOSC clock source (TMR3CS<1:0> = 01) should not be used with the ECCP capture/compare features. If the timer will be used with the capture or compare features, always select one of the other timer clocking options. REGISTER 14-1: R/W-0 TMR3CS1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 T3CON: TIMER3 CONTROL REGISTER (ACCESS F79h) R/W-0 T3CKPS1 R/W-0 T3CKPS0 U-0 -- R/W-0 T3SYNC R/W-0 RD16 R/W-0 TMR3ON bit 0 R/W-0 TMR3CS0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR3CS<1:0>: Timer3 Clock Source Select bits 10 = Timer3 clock source is the T3CKI input pin (assigned in the PPS module) 01 = Timer3 clock source is the system clock (FOSC)(1) 00 = Timer3 clock source is the instruction clock (FOSC/4) T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value Reserved: Program as `0' T3SYNC: Timer3 External Clock Input Synchronization Control bit When TMR3CS<1:0> = 10: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS<1:0> = 0x: This bit is ignored; Timer3 uses the internal clock. RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features. bit 5-4 bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2009 Microchip Technology Inc. DS39932C-page 209 PIC18F46J11 FAMILY 14.1 Timer3 Gate Control Register The Timer3 Gate Control register (T3GCON), provided in Register 14-2, is used to control the Timer3 gate. REGISTER 14-2: R/W-0 TMR3GE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 T3GCON: TIMER3 GATE CONTROL REGISTER (ACCESS F97h)(1) R/W-0 T3GTM R/W-0 T3GSPM R/W-0 T3GGO/T3DONE R-x T3GVAL R/W-0 T3GSS1 R/W-0 T3GSS0 bit 0 R/W-0 T3GPOL W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR3GE: Timer3 Gate Enable bit If TMR3ON = 0: This bit is ignored. If TMR3ON = 1: 1 = Timer3 counting is controlled by the Timer3 gate function 0 = Timer3 counts regardless of Timer3 gate function T3GPOL: Timer3 Gate Polarity bit 1 = Timer3 gate is active-high (Timer3 counts when gate is high) 0 = Timer3 gate is active-low (Timer3 counts when gate is low) T3GTM: Timer3 Gate Toggle Mode bit 1 = Timer3 Gate Toggle mode is enabled 0 = Timer3 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer3 gate flip-flop toggles on every rising edge. T3GSPM: Timer3 Gate Single Pulse Mode bit 1 = Timer3 Gate Single Pulse mode is enabled and is controlling Timer3 gate 0 = Timer3 Gate Single Pulse mode is disabled T3GGO/T3DONE: Timer3 Gate Single Pulse Acquisition Status bit 1 = Timer3 gate single pulse acquisition is ready, waiting for an edge 0 = Timer3 gate single pulse acquisition has completed or has not been started This bit is automatically cleared when T3GSPM is cleared. T3GVAL: Timer3 Gate Current State bit Indicates the current state of the Timer3 gate that could be provided to TMR3H:TMR3L. Unaffected by Timer3 Gate Enable bit (TMR3GE). T3GSS<1:0>: Timer3 Gate Source Select bits 10 = TMR2 to match PR2 output 01 = Timer0 overflow output 00 = Timer3 gate pin (T3G) Programming the T3GCON prior to T3CON is recommended. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: DS39932C-page 210 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 14-3: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TCLKCON: TIMER CLOCK CONTROL REGISTER (BANKED F52h) U-0 -- U-0 -- R-0 T1RUN U-0 -- U-0 -- R/W-0 T3CCP2 R/W-0 T3CCP1 bit 0 Unimplemented: Read as `0' T1RUN: Timer1 Run Status bit 1 = Device is currently clocked by T1OSC/T1CKI 0 = System clock comes from an oscillator other than T1OSC/T1CKI Unimplemented: Read as `0' T3CCP<2:1>: ECCP Timer Assignment bits 10 = ECCP1 and ECCP2 both use Timer3 (capture/compare) and Timer4 (PWM) 01 = ECCP1 uses Timer1 (compare/capture) and Timer2 (PWM); ECCP2 uses Timer3 (capture/compare) and Timer4 (PWM) 00 = ECCP1 and ECCP2 both use Timer1 (capture/compare) and Timer2 (PWM) bit 3-2 bit 1-0 (c) 2009 Microchip Technology Inc. DS39932C-page 211 PIC18F46J11 FAMILY 14.2 * * * * Timer3 Operation Timer3 can operate in one of three modes: Timer Synchronous Counter Asynchronous Counter Timer with Gated Control The operating mode is determined by the clock select bits, TMR3CSx (T3CON<7:6>). When the TMR3CSx bits are cleared (= 00), Timer3 increments on every internal instruction cycle (FOSC/4). When TMR3CSx = 01, the Timer3 clock source is the system clock (FOSC), and when it is `10', Timer3 works as a counter from the external clock from the T3CKI pin (on the rising edge after the first falling edge) or the Timer1 oscillator. FIGURE 14-1: T3GSS<1:0> T3G From Timer0 Overflow From Timer2 Match PR2 TIMER3 BLOCK DIAGRAM 00 01 10 D TMR3ON T3GPOL Set Flag bit, TMR3IF, on Overflow T3GTM CK R Q Q 1 T3G_IN T3GSPM 0 0 Single Pulse Acq. Control T3GGO/T3DONE 1 T3GVAL Q1 D EN Q Data Bus RD T3GCON Set TMR3GIF Interrupt det TMR3GE TMR3ON TMR3(2) TMR3H TMR3L Q EN D T3CLK 0 1 Synchronized Clock Input TMR3CS<1:0> T3SYNC Prescaler 1, 2, 4, 8 2 T3CKPS<1:0> FOSC/2 Internal Clock Sleep Input Synchronize(3) det T3CKI 10 FOSC Internal Clock FOSC/4 Internal Clock 01 00 Note 1: 2: 3: ST Buffer is high-speed type when using T3CKI. Timer3 register increments on rising edge. Synchronize does not operate while in Sleep. DS39932C-page 212 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 14.3 Timer3 16-Bit Read/Write Mode Timer3 can be configured for 16-bit reads and writes (see Section 14.3 "Timer3 16-Bit Read/Write Mode"). When the RD16 control bit (T3CON<1>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer3 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. A write to the high byte of Timer3 must also take place through the TMR3H Buffer register. The Timer3 high byte is updated with the contents of TMR3H when a write occurs to TMR3L. This allows a user to write all 16 bits to both the high and low bytes of Timer3 at once. The high byte of Timer3 is not directly readable or writable in this mode. All reads and writes must take place through the Timer3 High Byte Buffer register. Writes to TMR3H do not clear the Timer3 prescaler. The prescaler is only cleared on writes to TMR3L. The Timer1 oscillator is described in Section 12.0 "Timer1 Module". 14.5 Timer3 Gate Timer3 can be configured to count freely, or the count can be enabled and disabled using Timer3 gate circuitry. This is also referred to as Timer3 gate count enable. Timer3 gate can also be driven by multiple selectable sources. 14.5.1 TIMER3 GATE COUNT ENABLE The Timer3 Gate Enable mode is enabled by setting the TMR3GE bit of the T3GCON register. The polarity of the Timer3 Gate Enable mode is configured using the T3GPOL bit of the T3GCON register. When Timer3 Gate Enable mode is enabled, Timer3 will increment on the rising edge of the Timer3 clock source. When Timer3 Gate Enable mode is disabled, no incrementing will occur and Timer3 will hold the current count. See Figure 14-2 for timing details. 14.4 Using the Timer1 Oscillator as the Timer3 Clock Source TABLE 14-1: T3CLK TIMER3 GATE ENABLE SELECTIONS T3G 0 1 0 1 Timer3 Operation Counts Holds Count Holds Count Counts 0 0 1 1 T3GPOL The Timer1 internal oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. To use it as the Timer3 clock source, the TMR3CS bit must also be set. As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. FIGURE 14-2: TMR3GE TIMER3 GATE COUNT ENABLE MODE T3GPOL T3G_IN T1CKI T3GVAL Timer3 N N+1 N+2 N+3 N+4 (c) 2009 Microchip Technology Inc. DS39932C-page 213 PIC18F46J11 FAMILY 14.5.2 TIMER3 GATE SOURCE SELECTION 14.5.2.3 Timer2 Match Gate Operation The Timer3 gate source can be selected from one of four different sources. Source selection is controlled by the T3GSSx bits of the T3GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T3GPOL bit of the T3GCON register. The TMR2 register will increment until it matches the value in the PR2 register. On the very next increment cycle, TMR2 will be reset to 00h. When this Reset occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timer3 gate circuitry. 14.5.3 TIMER3 GATE TOGGLE MODE TABLE 14-2: T3GSS<1:0> 00 01 10 11 TIMER3 GATE SOURCES Timer3 Gate Source Timer3 Gate Pin Overflow of Timer0 (TMR0 increments from FFh to 00h) TMR2 to Match PR2 (TMR2 increments to match PR2) Reserved When Timer3 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer3 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 14-3 for timing details. The T3GVAL bit will indicate when the Toggled mode is active and the timer is counting. Timer3 Gate Toggle mode is enabled by setting the T3GTM bit of the T3GCON register. When the T3GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. 14.5.2.1 T3G Pin Gate Operation The T3G pin is one source for Timer3 gate control. It can be used to supply an external source to the Timer3 gate circuitry. 14.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer3 gate circuitry. FIGURE 14-3: TMR3GE T3GPOL TIMER3 GATE TOGGLE MODE T3GTM T3G_IN T1CKI T3GVAL Timer3 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 DS39932C-page 214 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 14.5.4 TIMER3 GATE SINGLE PULSE MODE When Timer3 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer3 Gate Single Pulse mode is first enabled by setting the T3GSPM bit in the T3GCON register. Next, the T3GGO/T3DONE bit in the T3GCON register must be set. The Timer3 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T3GGO/T3DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer3 until the T3GGO/T3DONE bit is once again set in software. Clearing the T3GSPM bit of the T3GCON register will also clear the T3GGO/T3DONE bit. See Figure 14-4 for timing details. Enabling the Toggle mode and the Single Pulse mode, simultaneously, will permit both sections to work together. This allows the cycle times on the Timer3 gate source to be measured. See Figure 14-5 for timing details. FIGURE 14-4: TMR3GE TIMER3 GATE SINGLE PULSE MODE T3GPOL T3GSPM Cleared by Hardware on Falling Edge of T3GVAL T3GGO/ T3DONE Set by Software Counting Enabled on Rising Edge of T3G T3G_IN T1CKI T3GVAL Timer3 N N+1 N+2 Cleared by Software TMR3GIF Cleared by Software Set by Hardware on Falling Edge of T3GVAL (c) 2009 Microchip Technology Inc. DS39932C-page 215 PIC18F46J11 FAMILY FIGURE 14-5: TMR3GE TIMER3 GATE SINGLE PULSE AND TOGGLE COMBINED MODE T3GPOL T3GSPM T3GTM Cleared by Hardware on Falling Edge of T3GVAL T3GGO/ T3DONE Set by Software Counting Enabled on Rising Edge of T3G T3G_IN T1CKI T3GVAL Timer3 N N+1 N+2 N+3 N+4 Cleared by Software TMR3GIF Cleared by Software Set by Hardware on Falling Edge of T3GVAL 14.5.5 TIMER3 GATE VALUE STATUS 14.5.6 TIMER3 GATE EVENT INTERRUPT When Timer3 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T3GVAL bit in the T3GCON register. The T3GVAL bit is valid even when the Timer3 gate is not enabled (TMR3GE bit is cleared). When the Timer3 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T3GVAL occurs, the TMR3GIF flag bit in the PIR3 register will be set. If the TMR3GIE bit in the PIE3 register is set, then an interrupt will be recognized. The TMR3GIF flag bit operates even when the Timer3 gate is not enabled (TMR3GE bit is cleared). DS39932C-page 216 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 14.6 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled or disabled by setting or clearing the Timer3 Interrupt Enable bit, TMR3IE (PIE2<1>). The trigger from ECCP2 will also start an A/D conversion if the A/D module is enabled (see Section 17.3.4 "Special Event Trigger" for more information). The module must be configured as either a timer or synchronous counter to take advantage of this feature. When used this way, the CCPRxH:CCPRxL register pair effectively becomes a Period register for Timer3. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. In the event that a write to Timer3 coincides with a Special Event Trigger from an ECCP module, the write will take precedence. Note: The Special Event Triggers from the ECCPx module will not set the TMR3IF interrupt flag bit (PIR1<0>). 14.7 Resetting Timer3 Using the ECCP Special Event Trigger If ECCP1 or ECCP2 is configured to use Timer3 and to generate a Special Event Trigger in Compare mode (CCPxM<3:0> = 1011), this signal will reset Timer3. TABLE 14-3: Name INTCON PIR2 PIE2 IPR2 TMR3L TMR3H T1CON T3CON T3GCON TCLKCON PIR3 PIE3 IPR3 REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 TMR0IE CM1IF CM1IE CM1IP Bit 4 INT0IE -- -- -- Bit 3 RBIE BCL1IF BCL1IE BCL1IP Bit 2 TMR0IF LVDIF LVDIE LVDIP Bit 1 INT0IF TMR3IF TMR3IE TMR3IP Bit 0 RBIF CCP2IF CCP2IE CCP2IP Reset Values on Page: 83 85 85 85 86 86 RD16 RD16 T3GSS1 T3CCP2 TMR3GIF TMR3GIE TMR3GIP TMR1ON TMR3ON T3GSS0 T3CCP1 RTCCIF RTCCIE RTCCIP 84 86 85 87 85 85 85 -- T3GGO/ T3DONE -- TMR4IF TMR4IE TMR4IP T3SYNC T3GVAL -- CTMUIF CTMUIE CTMUIP GIE/GIEH PEIE/GIEL OSCFIF OSCFIE OSCFIP CM2IF CM2IE CM2IP Timer3 Register Low Byte Timer3 Register High Byte TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 TMR3GE -- SSP2IF SSP2IE SSP2IP T3GPOL -- BCL2IF BCL2IE BCL2IP T3GTM -- RC2IF RC2IE RC2IP T3GSPM T1RUN TX2IF TX2IE TX2IP Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer3 module. (c) 2009 Microchip Technology Inc. DS39932C-page 217 PIC18F46J11 FAMILY NOTES: DS39932C-page 218 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 15.0 * * * * * * TIMER4 MODULE 15.1 Timer4 Operation The Timer4 timer module has the following features: 8-Bit Timer register (TMR4) 8-Bit Period register (PR4) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR4 match of PR4 Timer4 has a control register shown in Register 15-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 is also controlled by this register. Figure 15-1 is a simplified block diagram of the Timer4 module. Timer4 can be used as the PWM time base for the PWM mode of the ECCP modules. The TMR4 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, T4CKPS<1:0> (T4CON<1:0>). The match output of TMR4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR4 interrupt, latched in flag bit, TMR4IF (PIR3<3>). The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR4 register * a write to the T4CON register * any device Reset (Power-on Reset (POR), MCLR Reset, Watchdog Timer Reset (WDTR) or Brown-out Reset (BOR)) TMR4 is not cleared when T4CON is written. REGISTER 15-1: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3 T4CON: TIMER4 CONTROL REGISTER (ACCESS F76h) R/W-0 T4OUTPS2 R/W-0 T4OUTPS1 R/W-0 T4OUTPS0 R/W-0 TMR4ON R/W-0 T4CKPS1 R/W-0 T4CKPS0 bit 0 R/W-0 T4OUTPS3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' T4OUTPS<3:0>: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off T4CKPS<1:0>: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 bit 2 bit 1-0 (c) 2009 Microchip Technology Inc. DS39932C-page 219 PIC18F46J11 FAMILY 15.2 Timer4 Interrupt 15.3 Output of TMR4 The Timer4 module has an 8-bit Period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. The output of TMR4 (before the postscaler) is used only as a PWM time base for the ECCP modules. It is not used as a baud rate clock for the MSSP modules as is the Timer2 output. FIGURE 15-1: TIMER4 BLOCK DIAGRAM 4 1:1 to 1:16 Postscaler T4OUTPS<3:0> T4CKPS<1:0> 2 Set TMR4IF TMR4 Output (to PWM) Reset FOSC/4 1:1, 1:4, 1:16 Prescaler TMR4 8 Internal Data Bus TMR4/PR4 Match Comparator PR4 8 8 TABLE 15-1: Name REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Bit 6 Bit 5 TMR0IE RC2IP RC2IF RC2IE Bit 4 INT0IE TX2IP TX2IF TX2IE Bit 3 RBIE TMR4IP TMR4IF TMR4IE Bit 2 TMR0IF CTMUIP CTMUIF CTMUIE Bit 1 INT0IF TMR3GIP TMR3GIF TMR3GIE Bit 0 RBIF RTCIP RTCIF RTCIE Reset Values on Page: 83 85 85 85 86 86 86 Bit 7 INTCON GIE/GIEH PEIE/GIEL IPR3 PIR3 PIE3 TMR4 T4CON PR4 SSP2IP SSP2IF SSP2IE -- BCL2IP BCL2IF BCL2IE Timer4 Register T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 Timer4 Period Register Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer4 module. DS39932C-page 220 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 16.0 REAL-TIME CLOCK AND CALENDAR (RTCC) The RTCC module is intended for applications where accurate time must be maintained for an extended period with minimum to no intervention from the CPU. The module is optimized for low-power usage in order to provide extended battery life while keeping track of time. The module is a 100-year clock and calendar with automatic leap year detection. The range of the clock is from 00:00:00 (midnight) on January 1, 2000 to 23:59:59 on December 31, 2099. Hours are measured in 24-hour (military time) format. The clock provides a granularity of one second with half-second visibility to the user. The key features of the Real-Time Clock and Calendar (RTCC) module are: * * * * * * * * * * * * Time: hours, minutes and seconds 24-hour format (military time) Calendar: weekday, date, month and year Alarm configurable Year range: 2000 to 2099 Leap year correction BCD format for compact firmware Optimized for low-power operation User calibration with auto-adjust Calibration range: 2.64 seconds error per month Requirements: external 32.768 kHz clock crystal Alarm pulse or seconds clock output on RTCC pin FIGURE 16-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain 32.768 kHz Input from Timer1 Oscillator or Internal RC RTCCFG RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVALx ALRMRPT YEAR MTHDY WKDYHR MINSEC Comparator ALMTHDY Compare Registers with Masks ALRMVALx ALWDHR ALMINSEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE (c) 2009 Microchip Technology Inc. DS39932C-page 221 PIC18F46J11 FAMILY 16.1 RTCC MODULE REGISTERS Alarm Value Registers * ALRMVALH and ALRMVALL - Can access the following registers: - ALRMMNTH - ALRMDAY - ALRMWD - ALRMHR - ALRMMIN - ALRMSEC Note: The RTCVALH and RTCVALL registers can be accessed through RTCRPT<1:0>. ALRMVALH and ALRMVALL can be accessed through ALRMPTR<1:0>. The RTCC module registers are divided into following categories: RTCC Control Registers * * * * * RTCCFG RTCCAL PADCFG1 ALRMCFG ALRMRPT RTCC Value Registers * RTCVALH and RTCVALL - Can access the following registers - YEAR - MONTH - DAY - WEEKDAY - HOUR - MINUTE - SECOND DS39932C-page 222 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 16.1.1 RTCC CONTROL REGISTERS RTCCFG: RTCC CONFIGURATION REGISTER (BANKED F3Fh)(1) U-0 -- R/W-0 RTCWREN R-0 R-0 (3) REGISTER 16-1: R/W-0 RTCEN(2) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 R/W-0 RTCOE R/W-0 RTCPTR1 R/W-0 RTCPTR0 bit 0 RTCSYNC HALFSEC W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as `0' RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALRMRPT registers can change while reading due to a rollover ripple resulting in an invalid data read If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC clock output enabled 0 = RTCC clock output disabled RTCPTR<1:0>: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH<7:0> and RTCVALL<7:0> registers; the RTCPTR<1:0> value decrements on every read or write of RTCVALH<7:0> until it reaches `00'. RTCVALH<7:0>: 00 = Minutes 01 = Weekday 10 = Month 11 = Reserved RTCVALL<7:0>: 00 = Seconds 01 = Hours 10 = Day 11 = Year The RTCCFG register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to `0' on a write to the lower half of the MINSEC register. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: 2: 3: (c) 2009 Microchip Technology Inc. DS39932C-page 223 PIC18F46J11 FAMILY REGISTER 16-2: R/W-0 CAL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RTCCAL: RTCC CALIBRATION REGISTER (BANKED F3Eh) R/W-0 CAL6 R/W-0 CAL5 R/W-0 CAL4 R/W-0 CAL3 R/W-0 CAL2 R/W-0 CAL1 R/W-0 CAL0 bit 0 CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every minute . . . 00000001 = Minimum positive adjustment; adds four RTC clock pulses every minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts four RTC clock pulses every minute . . . 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every minute REGISTER 16-3: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2-1 -- PADCFG1: PAD CONFIGURATION REGISTER (BANKED F3Ch) U-0 U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 PMPTTL bit 0 RTSECSEL1(1) RTSECSEL0(1) W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1) 11 = Reserved, do not use 10 = RTCC source clock is selected for the RTCC pin (pin can be INTRC or T1OSC, depending on the RTCOSC (CONFIG3L<1>) setting) 01 = RTCC seconds clock is selected for the RTCC pin 00 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt input buffers To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set. bit 0 Note 1: DS39932C-page 224 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 16-4: R/W-0 ALRMEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ALRMCFG: ALARM CONFIGURATION REGISTER (ACCESS F91h) R/W-0 CHIME R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0 ALRMPTR1 R/W-0 ALRMPTR0 bit 0 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 0000 0000 and CHIME = 0) 0 = Alarm is disabled CHIME: Chime Enable bit 1 = Chime is enabled; ALRMRPT<7:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ALRMRPT<7:0> bits stop once they reach 00h AMASK<3:0>: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every four years) 101x = Reserved - do not use 11xx = Reserved - do not use ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches `00'. ALRMVALH<15:8>: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVALL<7:0>: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented bit 6 bit 5-2 bit 1-0 (c) 2009 Microchip Technology Inc. DS39932C-page 225 PIC18F46J11 FAMILY REGISTER 16-5: R/W-0 ARPT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ALRMRPT: ALARM CALIBRATION REGISTER (ACCESS F90h) R/W-0 ARPT6 R/W-0 ARPT5 R/W-0 ARPT4 R/W-0 ARPT3 R/W-0 ARPT2 R/W-0 ARPT1 R/W-0 ARPT0 bit 0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times . . . 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1. DS39932C-page 226 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 16.1.2 RTCVALH AND RTCVALL REGISTER MAPPINGS RESERVED REGISTER (ACCESS F99h, PTR 11b) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 REGISTER 16-6: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' REGISTER 16-7: R/W-x YRTEN3 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 bit 3-0 Note 1: YEAR: YEAR VALUE REGISTER (ACCESS F98h, PTR 11b)(1) R/W-x R/W-x YRTEN1 R/W-x YRTEN0 R/W-x YRONE3 R/W-x YRONE2 R/W-x YRONE1 R/W-x YRONE0 bit 0 YRTEN2 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown YRTEN<3:0>: Binary Coded Decimal Value of Year's Tens Digit bits Contains a value from 0 to 9. YRONE<3:0>: Binary Coded Decimal Value of Year's Ones Digit bits Contains a value from 0 to 9. A write to the YEAR register is only allowed when RTCWREN = 1. REGISTER 16-8: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 bit 3-0 Note 1: MONTH: MONTH VALUE REGISTER (ACCESS F99h, PTR 10b)(1) U-0 -- U-0 -- R/W-x MTHTEN0 R/W-x MTHONE3 R/W-x MTHONE2 R/W-x MTHONE1 R/W-x MTHONE0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' MTHTEN0: Binary Coded Decimal Value of Month's Tens Digit bit Contains a value of 0 or 1. MTHONE<3:0>: Binary Coded Decimal Value of Month's Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. (c) 2009 Microchip Technology Inc. DS39932C-page 227 PIC18F46J11 FAMILY REGISTER 16-9: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 bit 3-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DAY: DAY VALUE REGISTER (ACCESS F98h, PTR 10b)(1) U-0 -- R/W-x DAYTEN1 R/W-x DAYTEN0 R/W-x DAYONE3 R/W-x DAYONE2 R/W-x DAYONE1 R/W-x DAYONE0 bit 0 Unimplemented: Read as `0' DAYTEN<1:0>: Binary Coded Decimal value of Day's Tens Digit bits Contains a value from 0 to 3. DAYONE<3:0>: Binary Coded Decimal Value of Day's Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. REGISTER 16-10: WKDY: WEEKDAY VALUE REGISTER (ACCESS F99h, PTR 01b)(1) U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 0 Unimplemented: Read as `0' WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. A write to this register is only allowed when RTCWREN = 1. DS39932C-page 228 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 16-11: HOURS: HOURS VALUE REGISTER (ACCESS F98h, PTR 01b)(1) U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 bit 3-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-x HRTEN1 R/W-x HRTEN0 R/W-x HRONE3 R/W-x HRONE2 R/W-x HRONE1 R/W-x HRONE0 bit 0 Unimplemented: Read as `0' HRTEN<1:0>: Binary Coded Decimal Value of Hour's Tens Digit bits Contains a value from 0 to 2. HRONE<3:0>: Binary Coded Decimal Value of Hour's Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. REGISTER 16-12: MINUTES: MINUTES VALUE REGISTER (ACCESS F99h, PTR 00b) U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x MINTEN2 R/W-x MINTEN1 R/W-x MINTEN0 R/W-x MINONE3 R/W-x MINONE2 R/W-x MINONE1 R/W-x MINONE0 bit 0 Unimplemented: Read as `0' MINTEN<2:0>: Binary Coded Decimal Value of Minute's Tens Digit bits Contains a value from 0 to 5. MINONE<3:0>: Binary Coded Decimal Value of Minute's Ones Digit bits Contains a value from 0 to 9. REGISTER 16-13: SECONDS: SECONDS VALUE REGISTER (ACCESS F98h, PTR 00b) U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x SECTEN2 R/W-x SECTEN1 R/W-x SECTEN0 R/W-x SECONE3 R/W-x SECONE2 R/W-x SECONE1 R/W-x SECONE0 bit 0 Unimplemented: Read as `0' SECTEN<2:0>: Binary Coded Decimal Value of Second's Tens Digit bits Contains a value from 0 to 5. SECONE<3:0>: Binary Coded Decimal Value of Second's Ones Digit bits Contains a value from 0 to 9. (c) 2009 Microchip Technology Inc. DS39932C-page 229 PIC18F46J11 FAMILY 16.1.3 ALRMVALH AND ALRMVALL REGISTER MAPPINGS REGISTER 16-14: ALRMMNTH: ALARM MONTH VALUE REGISTER (ACCESS F8Fh, PTR 10b)(1) U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 bit 3-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-x MTHTEN0 R/W-x MTHONE3 R/W-x MTHONE2 R/W-x MTHONE1 R/W-x MTHONE0 bit 0 Unimplemented: Read as `0' MTHTEN0: Binary Coded Decimal Value of Month's Tens Digit bit Contains a value of 0 or 1. MTHONE<3:0>: Binary Coded Decimal Value of Month's Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. REGISTER 16-15: ALRMDAY: ALARM DAY VALUE REGISTER (ACCESS F8Eh, PTR 10b)(1) U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 bit 3-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-x DAYTEN1 R/W-x DAYTEN0 R/W-x DAYONE3 R/W-x DAYONE2 R/W-x DAYONE1 R/W-x DAYONE0 bit 0 Unimplemented: Read as `0' DAYTEN<1:0>: Binary Coded Decimal Value of Day's Tens Digit bits Contains a value from 0 to 3. DAYONE<3:0>: Binary Coded Decimal Value of Day's Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. DS39932C-page 230 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 16-16: ALRMWD: ALARM WEEKDAY VALUE REGISTER (ACCESS F8Fh, PTR 01b)(1) U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 0 Unimplemented: Read as `0' WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. A write to this register is only allowed when RTCWREN = 1. REGISTER 16-17: ALRMHR: ALARM HOURS VALUE REGISTER (ACCESS F8Eh, PTR 01b)(1) U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 bit 3-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-x HRTEN1 R/W-x HRTEN0 R/W-x HRONE3 R/W-x HRONE2 R/W-x HRONE1 R/W-x HRONE0 bit 0 Unimplemented: Read as `0' HRTEN<1:0>: Binary Coded Decimal Value of Hour's Tens Digit bits Contains a value from 0 to 2. HRONE3:HRONE0: Binary Coded Decimal Value of Hour's Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. (c) 2009 Microchip Technology Inc. DS39932C-page 231 PIC18F46J11 FAMILY REGISTER 16-18: ALRMMIN: ALARM MINUTES VALUE REGISTER (ACCESS F8Fh, PTR 00b) U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x MINTEN2 R/W-x MINTEN1 R/W-x MINTEN0 R/W-x MINONE3 R/W-x MINONE2 R/W-x MINONE1 R/W-x MINONE0 bit 0 Unimplemented: Read as `0' MINTEN<2:0>: Binary Coded Decimal Value of Minute's Tens Digit bits Contains a value from 0 to 5. MINONE<3:0>: Binary Coded Decimal Value of Minute's Ones Digit bits Contains a value from 0 to 9. REGISTER 16-19: ALRMSEC: ALARM SECONDS VALUE REGISTER (ACCESS F8Eh, PTR 00b) U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x SECTEN2 R/W-x SECTEN1 R/W-x SECTEN0 R/W-x SECONE3 R/W-x SECONE2 R/W-x SECONE1 R/W-x SECONE0 bit 0 Unimplemented: Read as `0' SECTEN<2:0>: Binary Coded Decimal Value of Second's Tens Digit bits Contains a value from 0 to 5. SECONE<3:0>: Binary Coded Decimal Value of Second's Ones Digit bits Contains a value from 0 to 9. DS39932C-page 232 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 16.1.4 RTCEN BIT WRITE 16.2 16.2.1 Operation REGISTER INTERFACE An attempt to write to the RTCEN bit while RTCWREN = 0 will be ignored. RTCWREN must be set before a write to RTCEN can take place. Like the RTCEN bit, the RTCVALH<15:8> and RTCVALL<7:0> registers can only be written to when RTCWREN = 1. A write to these registers, while RTCWREN = 0, will be ignored. The register interface for the RTCC and alarm values is implemented using the Binary Coded Decimal (BCD) format. This simplifies the firmware, when using the module, as each of the digits is contained within its own 4-bit value (see Figure 16-2 and Figure 16-3). FIGURE 16-2: TIMER DIGIT FORMAT Year Month Day Day Of Week 0-9 0-9 0-1 0-9 0-3 0-9 0-6 Hours (24-hour format) Minutes Seconds 1/2 Second Bit (binary format) 0-2 0-9 0-5 0-9 0-5 0-9 0/1 FIGURE 16-3: ALARM DIGIT FORMAT Month Day Day Of Week 0-1 0-9 0-3 0-9 0-6 Hours (24-hour format) Minutes Seconds 0-2 0-9 0-5 0-9 0-5 0-9 (c) 2009 Microchip Technology Inc. DS39932C-page 233 PIC18F46J11 FAMILY 16.2.2 CLOCK SOURCE As mentioned earlier, the RTCC module is intended to be clocked by an external Real-Time Clock crystal oscillating at 32.768 kHz, but also can be clocked by the internal RC oscillator. The RTCC clock selection is decided by the RTCOSC bit (CONFIG3L<1>). Calibration of the crystal can be done through this module to yield an error of 3 seconds or less per month. (For further details, see Section 16.2.9 "Calibration".) FIGURE 16-4: 32.768 kHz XTAL from T1OSC Internal RC CONFIG 3L<1> CLOCK SOURCE MULTIPLEXING Half-Second Clock 1:16384 Clock Prescaler(1) Half Second(1) One-Second Clock Second Hour:Minute Day Day of Week Month Year Note 1: Writing to the lower half of the MINSEC register resets all counters, allowing fraction of a second synchronization; the clock prescaler is held in Reset when RTCEN = 0. 16.2.2.1 Real-Time Clock Enable For the day to month rollover schedule, see Table 16-2. Considering that the following values are in BCD format, the carry to the upper BCD digit will occur at a count of 10 and not at 16 (SECONDS, MINUTES, HOURS, WEEKDAY, DAYS and MONTHS). The RTCC module can be clocked by an external, 32.768 kHz crystal (Timer1 oscillator) or the internal RC oscillator, which can be selected in CONFIG3L<1>. If the external clock is used, the Timer1 oscillator should be enabled by setting T1CON<3> (T1OSCEN). If INTRC is providing the clock, the INTRC clock can be brought out to the RTCC pin by the RTSECSEL<1:0> bits in the PADCFG register. TABLE 16-1: DAY OF WEEK SCHEDULE Day of Week 0 1 2 3 4 5 6 Sunday Monday Tuesday Wednesday Thursday Friday Saturday 16.2.3 DIGIT CARRY RULES This section explains which timer values are affected when there is a rollover. * Time of Day: From 23:59:59 to 00:00:00 with a carry to the Day field * Month: From 12/31 to 01/01 with a carry to the Year field * Day of Week: From 6 to 0 with no carry (see Table 16-1) * Year Carry: From 99 to 00; this also surpasses the use of the RTCC DS39932C-page 234 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 16-2: Month 01 (January) 02 (February) 03 (March) 04 (April) 05 (May) 06 (June) 07 (July) 08 (August) 09 (September) 10 (October) 11 (November) 12 (December) Note 1: DAY TO MONTH ROLLOVER SCHEDULE Maximum Day Field 31 28 or 29(1) 31 30 31 30 31 31 30 31 30 31 16.2.6 SAFETY WINDOW FOR REGISTER READS AND WRITES The RTCSYNC bit indicates a time window during which the RTCC Clock Domain registers can be safely read and written without concern about a rollover. When RTCSYNC = 0, the registers can be safely accessed by the CPU. Whether RTCSYNC = 1 or 0, the user should employ a firmware solution to ensure that the data read did not fall on a rollover boundary, resulting in an invalid or partial read. This firmware solution would consist of reading each register twice and then comparing the two values. If the two values matched, then, a rollover did not occur. 16.2.7 WRITE LOCK See Section 16.2.4 "Leap Year". In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RTCCFG<5>) must be set. To avoid accidental writes to the RTCC Timer register, it is recommended that the RTCWREN bit (RTCCFG<5>) be kept clear at any time other than while writing to. For the RTCWREN bit to be set, there is only one instruction cycle time window allowed between the 55h/AA sequence and the setting of RTCWREN. For that reason, it is recommended that users follow the code example in Example 16-1. 16.2.4 LEAP YEAR Since the year range on the RTCC module is 2000 to 2099, the leap year calculation is determined by any year divisible by `4' in the above range. Only February is effected in a leap year. February will have 29 days in a leap year and 28 days in any other year. 16.2.5 GENERAL FUNCTIONALITY EXAMPLE 16-1: movlb movlw movwf movlw movwf bsf All Timer registers containing a time value of seconds or greater are writable. The user configures the time by writing the required year, month, day, hour, minutes and seconds to the Timer registers, via Register Pointers (see Section 16.2.8 "Register Mapping"). The timer uses the newly written values and proceeds with the count from the required starting point. The RTCC is enabled by setting the RTCEN bit (RTCCFG<7>). If enabled, while adjusting these registers, the timer still continues to increment. However, any time the MINSEC register is written to, both of the timer prescalers are reset to `0'. This allows fraction of a second synchronization. The Timer registers are updated in the same cycle as the write instruction's execution by the CPU. The user must ensure that when RTCEN = 1, the updated registers will not be incremented at the same time. This can be accomplished in several ways: * By checking the RTCSYNC bit (RTCCFG<4>) * By checking the preceding digits from which a carry can occur * By updating the registers immediately following the seconds pulse (or alarm interrupt) The user has visibility to the half-second field of the counter. This value is read-only and can be reset only by writing to the lower half of the SECONDS register. SETTING THE RTCWREN BIT 0x0f 0x55 EECON2,0 0xAA EECON2,0 RTCCFG,5,1 16.2.8 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Timer registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RTCCFG<1:0>) to select the required Timer register pair. By reading or writing to the RTCVALH register, the RTCC Pointer value (RTCPTR<1:0>) decrements by 1 until it reaches `00'. Once it reaches `00', the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed. (c) 2009 Microchip Technology Inc. DS39932C-page 235 PIC18F46J11 FAMILY TABLE 16-3: RTCVALH AND RTCVALL REGISTER MAPPING RTCC Value Register Window RTCVALH<15:8> RTCVALL<7:0> MINUTES WEEKDAY MONTH -- SECONDS HOURS DAY YEAR To calibrate the RTCC module: 1. 2. Use another timer resource on the device to find the error of the 32.768 kHz crystal. Convert the number of error clock pulses per minute (see Equation 16-1). RTCPTR<1:0> 00 01 10 11 EQUATION 16-1: CONVERTING ERROR CLOCK PULSES (Ideal Frequency (32,758) - Measured Frequency) * 60 = Error Clocks per Minute * If the oscillator is faster than ideal (negative result from step 2), the RTCCALL register value needs to be negative. This causes the specified number of clock pulses to be subtracted from the timer counter once every minute. * If the oscillator is slower than ideal (positive result from step 2), the RTCCALL register value needs to be positive. This causes the specified number of clock pulses to be added to the timer counter once every minute. Load the RTCCAL register with the correct value. The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALRMCFG<1:0>) to select the desired Alarm register pair. By reading or writing to the ALRMVALH register, the Alarm Pointer value, ALRMPTR<1:0>, decrements by 1 until it reaches `00'. Once it reaches `00', the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. TABLE 16-4: ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVALH<15:8> ALRMVALL<7:0> ALRMMIN ALRMWD ALRMMNTH -- ALRMSEC ALRMHR ALRMDAY -- 3. ALRMPTR<1:0> 00 01 10 11 Writes to the RTCCAL register should occur only when the timer is turned off, or immediately after the rising edge of the seconds pulse. Note: In determining the crystal's error value, it is the user's responsibility to include the crystal's initial error from drift due to temperature or crystal aging. 16.2.9 CALIBRATION The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than three seconds per month. To perform this calibration, find the number of error clock pulses and store the value in the lower half of the RTCCAL register. The 8-bit, signed value - loaded into RTCCAL - is multiplied by `4' and will either be added or subtracted from the RTCC timer, once every minute. DS39932C-page 236 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 16.3 Alarm The alarm features and characteristics are: * Configurable from half a second to one year * Enabled using the ALRMEN bit (ALRMCFG<7>, Register 16-4) * Offers one-time and repeat alarm options The alarm can also be configured to repeat based on a preconfigured interval. The number of times this occurs after the alarm is enabled is stored in the ALRMRPT register. Note: While the alarm is enabled (ALRMEN = 1), changing any of the registers - other than the RTCCAL, ALRMCFG and ALRMRPT registers and the CHIME bit - can result in a false alarm event leading to a false alarm interrupt. To avoid this, only change the timer and alarm values while the alarm is disabled (ALRMEN = 0). It is recommended that the ALRMCFG and ALRMRPT registers and CHIME bit be changed when RTCSYNC = 0. 16.3.1 CONFIGURING THE ALARM The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. The bit will not be cleared if the CHIME bit = 1 or if ALRMRPT 0. The interval selection of the alarm is configured through the ALRMCFG bits (AMASK<3:0>). (See Figure 16-5.) These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. FIGURE 16-5: ALARM MASK SETTINGS Day of the Week Month Day Hours Minutes Seconds Alarm Mask Setting AMASK<3:0> 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds 0011 - Every minute 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week 1000 - Every month 1001 - Every year(1) Note 1: s s m m h d d m m d d d h h h h h h h m m m m m m m m m s s s s s s s s s s s s s Annually, except when configured for February 29. (c) 2009 Microchip Technology Inc. DS39932C-page 237 PIC18F46J11 FAMILY When ALRMCFG = 00 and the CHIME bit = 0 (ALRMCFG<6>), the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading the ALRMRPT register with FFh. After each alarm is issued, the ALRMRPT register is decremented by one. Once the register has reached `00', the alarm will be issued one last time. After the alarm is issued a last time, the ALRMEN bit is cleared automatically and the alarm turned off. Indefinite repetition of the alarm can occur if the CHIME bit = 1. When CHIME = 1, the alarm is not disabled when the ALRMRPT register reaches `00', but it rolls over to FF and continues counting indefinitely. 16.3.2 ALARM INTERRUPT At every alarm event, an interrupt is generated. Additionally, an alarm pulse output is provided that operates at half the frequency of the alarm. The alarm pulse output is completely synchronous with the RTCC clock and can be used as a trigger clock to other peripherals. This output is available on the RTCC pin. The output pulse is a clock with a 50% duty cycle and a frequency half that of the alarm event (see Figure 16-6). The RTCC pin also can output the seconds clock. The user can select between the alarm pulse, generated by the RTCC module, or the seconds clock output. The RTSECSEL (PADCFG1<1:0>) bits select between these two outputs: * Alarm pulse - RTSECSEL<1:0> = 00 * Seconds clock - RTSECSEL<1:0> = 0 FIGURE 16-6: RTCEN bit TIMER PULSE GENERATION ALRMEN bit RTCC Alarm Event RTCC Pin 16.4 Low-Power Modes 16.5.2 POWER-ON RESET (POR) The timer and alarm can optionally continue to operate while in Sleep, Idle and even Deep Sleep mode. An alarm event can be used to wake-up the microcontroller from any of these Low-Power modes. The RTCCFG and ALRMRPT registers are reset only on a POR. Once the device exits the POR state, the clock registers should be reloaded with the desired values. The timer prescaler values can be reset only by writing to the SECONDS register. No device Reset can affect the prescalers. 16.5 16.5.1 Reset DEVICE RESET When a device Reset occurs, the ALCFGRPT register is forced to its Reset state causing the alarm to be disabled (if enabled prior to the Reset). If the RTCC was enabled, it will continue to operate when a basic device Reset occurs. DS39932C-page 238 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 16.6 Register Maps Table 16-5, Table 16-6 and Table 16-7 summarize the registers associated with the RTCC module. TABLE 16-5: File Name RTCCFG RTCCAL PADCFG1 ALRMCFG ALRMRPT IPR3 PIR3 PIE3 Legend: RTCC CONTROL REGISTERS Bit 7 Bit 6 -- CAL6 -- CHIME ARPT6 BCL2IP BCL2IF BCL2IE Bit 5 RTCWREN CAL5 -- AMASK3 ARPT5 RC2IP RC2IF RC2IE Bit 4 RTCSYNC CAL4 -- AMASK2 ARPT4 TX2IP TX2IF TX2IE Bit 3 HALFSEC CAL3 -- AMASK1 ARPT3 TMR4IP TMR4IF TMR4IE Bit 2 RTCOE CAL2 AMASK0 ARPT2 CTMUIP CTMUIF CTMUIE Bit 1 RTCPTR1 CAL1 Bit 0 RTCPTR0 CAL0 PMPTTL ARPT0 RTCCIP RTCCIF RTCCIE All Resets 0000 0000 0000 0000 0000 1111 0000 0000 RTCEN CAL7 -- ALRMEN ARPT7 SSP2IP SSP2IF SSP2IE RTSECSEL1 RTSECSEL0 ARPT1 TMR3GIP TMR3GIF TMR3GIE ALRMPTR1 ALRMPTR0 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 44-pin devices. TABLE 16-6: File Name RTCVALH RTCVALL RTCCFG ALRMCFG ALRMVALL Legend: RTCC VALUE REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx RTCPTR1 ALRMPTR1 RTCPTR0 ALRMPTR0 0000 0000 xxxx xxxx RTCC Value Register Window High Byte, Based on RTCPTR<1:0> RTCC Value Register Window Low Byte, Based on RTCPTR<1:0> RTCEN ALRMEN -- CHIME RTCWREN RTCSYNC HALFSEC AMASK3 AMASK2 AMASK1 RTCOE AMASK0 ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0> Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0> -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 44-pin devices. TABLE 16-7: File Name ALRMRPT ALARM VALUE REGISTERS Bit 7 ARPT7 Bit 6 ARPT6 Bit 5 ARPT5 Bit 4 ARPT4 Bit 3 ARPT3 Bit 2 ARPT2 Bit 1 ARPT1 Bit 0 ARPT0 All Resets 0000 xxxx xxxx CAL2 CAL1 CAL0 0000 xxxx xxxx ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0> ALRMVALL Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0> RTCCAL RTCVALH RTCVALL Legend: CAL7 CAL6 CAL5 CAL4 CAL3 RTCC Value Register Window High Byte, Based on RTCPTR<1:0> RTCC Value Register Window Low Byte, Based on RTCPTR<1:0> -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 44-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 239 PIC18F46J11 FAMILY NOTES: DS39932C-page 240 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 17.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE ECCP1 and ECCP2 are implemented as standard CCP modules with enhanced PWM capabilities. These include: * * * * * Provision for two or four output channels Output Steering modes Programmable polarity Programmable dead-band control Automatic shutdown and restart PIC18F46J11 family devices have two Enhanced Capture/Compare/PWM (ECCP) modules: ECCP1 and ECCP2. These modules contain a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. These ECCP modules are upward compatible with CCP Note: Register and bit names referencing one of the two ECCP modules substitute an `x' for the module number. For example, registers CCP1CON and CCP2CON, which have the same definitions, are called CCPxCON. Figures and diagrams use ECCP1-based names, but those names also apply to ECCP2, with a "2" replacing the illustration name's "1". When writing firmware, the "x" in register and bit names must be replaced with the appropriate module number. The enhanced features are discussed in detail in Section 17.5 "PWM (Enhanced Mode)". Note: PxA, PxB, PxC and PxD are associated with the remappable pins (RPn). (c) 2009 Microchip Technology Inc. DS39932C-page 241 PIC18F46J11 FAMILY REGISTER 17-1: R/W-0 PxM1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CCPxCON: ECCPx CONTROL (ACCESS FBAh/FB4h) R/W-0 DCxB1 R/W-0 DCxB0 R/W-0 CCPxM3 R/W-0 CCPxM2 R/W-0 CCPxM1 R/W-0 CCPxM0 bit 0 PxM0 R/W-0 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as capture/compare input/output; PxB, PxC and PxD assigned as port pins If CCPxM<3:2> = 11: 00 = Single output: PxA, PxB, PxC and PxD controlled by steering (see Section 17.5.7 "Pulse Steering Mode") 01 = Full-bridge output forward: PxD modulated; PxA active; PxB, PxC inactive 10 = Half-bridge output: PxA, PxB modulated with dead-band control; PxC and PxD assigned as port pins 11 = Full-bridge output reverse: PxB modulated; PxC active; PxA and PxD inactive DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPRxL. CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match 0011 = Capture mode 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize ECCPx pin low, set output on compare match (set CCPxIF) 1001 = Compare mode, initialize ECCPx pin high, clear output on compare match (set CCPxIF) 1010 = Compare mode, generate software interrupt only, ECCPx pin reverts to I/O state 1011 = Compare mode, trigger special event (ECCPx resets TMR1 or TMR3, starts A/D conversion, sets CCxIF bit) 1100 = PWM mode; PxA and PxC active-high; PxB and PxD active-high 1101 = PWM mode; PxA and PxC active-high; PxB and PxD active-low 1110 = PWM mode; PxA and PxC active-low; PxB and PxD active-high 1111 = PWM mode; PxA and PxC active-low; PxB and PxD active-low bit 5-4 bit 3-0 DS39932C-page 242 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY In addition to the expanded range of modes available through the CCPxCON and ECCPxAS registers, the ECCP modules have two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: * ECCPxDEL (Enhanced PWM Control) * PSTRxCON (Pulse Steering Control) 17.2 Capture Mode In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding ECCPx pin. An event is defined as one of the following: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 17.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are routed through the Peripheral Pin Select (PPS) module. Therefore, individual functions may be mapped to any of the remappable I/O pins, RPn. The outputs that are active depend on the ECCP operating mode selected. The pin assignments are summarized in Table 17-4. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the PxM<1:0> and CCPxM<3:0> bits. The appropriate TRIS direction bits for the port pins must also be set as outputs and the output functions need to be assigned to I/O pins in the PPS module. (For details on configuring the module, see Section 9.7 "Peripheral Pin Select (PPS)".) The event is selected by the mode select bits, CCPxM<3:0>, of the CCPxCON register. When a capture is made, the interrupt request flag bit, CCPxIF, is set; it must be cleared by software. If another capture occurs before the value in register CCPRx is read, the old captured value is overwritten by the new captured value. 17.2.1 ECCP PIN CONFIGURATION In Capture mode, the appropriate ECCPx pin should be configured as an input by setting the corresponding TRIS direction bit. Additionally, the ECCPx input function needs to be assigned to an I/O pin through the Peripheral Pin Select module. For details on setting up the remappable pins, see Section 9.7 "Peripheral Pin Select (PPS)". Note: If the ECCPx pin is configured as an output, a write to the port can cause a capture condition. 17.1.1 ECCP MODULE AND TIMER RESOURCES The ECCP modules utilize Timers 1, 2, 3 or 4, depending on the mode selected. Timer1 and Timer3 are available to modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. 17.2.2 TIMER1/TIMER3 MODE SELECTION TABLE 17-1: ECCP MODE - TIMER RESOURCE Timer Resource Timer1 or Timer3 Timer1 or Timer3 Timer2 or Timer4 ECCP Mode Capture Compare PWM The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each ECCP module is selected in the TCLKCON register (Register 12-3). 17.2.3 SOFTWARE INTERRUPT The assignment of a particular timer to a module is determined by the Timer-to-ECCP enable bits in the TCLKCON register (Register 12-3). The interactions between the two modules are depicted in Figure 17-1. Capture operations are designed to be used when the timer is configured for Synchronous Counter mode. Capture operations may not work as expected if the associated timer is configured for Asynchronous Counter mode. When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. (c) 2009 Microchip Technology Inc. DS39932C-page 243 PIC18F46J11 FAMILY 17.2.4 ECCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCPxM<3:0>). Whenever the ECCP module is turned off, or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 17-1 provides the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. EXAMPLE 17-1: CLRF MOVLW CHANGING BETWEEN CAPTURE PRESCALERS MOVWF CCP1CON ; Turn CCP module off NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and CCP ON CCP1CON ; Load CCP1CON with ; this value FIGURE 17-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set CCP1IF T3CCP1 ECCP1 pin Prescaler / 1, 4, 16 and Edge Detect T3CCP1 CCP1CON<3:0> Q1:Q4 4 4 TMR3H TMR3 Enable CCPR1H TMR1 Enable TMR1H TMR3L CCPR1L TMR1L DS39932C-page 244 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 17.3 Compare Mode 17.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the ECCPx pin can be: * * * * Driven high Driven low Toggled (high-to-low or low-to-high) Remain unchanged (that is, reflects the state of the I/O latch) Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the ECCP module is using the compare feature. In Asynchronous Counter mode, the compare operation will not work reliably. 17.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the ECCPx pin is not affected; only the CCPxIF interrupt flag is affected. The action on the pin is based on the value of the mode select bits (CCPxM<3:0>). At the same time, the interrupt flag bit, CCPxIF, is set. 17.3.4 SPECIAL EVENT TRIGGER 17.3.1 ECCP PIN CONFIGURATION Users must configure the ECCPx pin as an output by clearing the appropriate TRIS bit. Note: Clearing the CCPxCON register will force the ECCPx compare output latch (depending on device configuration) to the default low level. This is not the PORTx I/O data latch. The ECCP module is equipped with a Special Event Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode (CCPxM<3:0> = 1011). The Special Event Trigger resets the Timer register pair for whichever timer resource is currently assigned as the module's time base. This allows the CCPRx registers to serve as a programmable period register for either timer. The Special Event Trigger can also start an A/D conversion. In order to do this, the A/D converter must already be enabled. FIGURE 17-2: COMPARE MODE OPERATION BLOCK DIAGRAM 0 TMR1H TMR1L 1 TMR3H T3CCP1 TMR3L Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) Set CCP1IF Comparator Compare Match Output Logic 4 CCP1CON<3:0> S R Q ECCP1 Pin CCPR1H CCPR1L TRIS Output Enable (c) 2009 Microchip Technology Inc. DS39932C-page 245 PIC18F46J11 FAMILY 17.4 PWM Mode 17.4.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Note: Clearing the CCPxCON register will force the output latch (depending on device configuration) to the default low level. This is not the LATx data latch. The PWM period is specified by writing to the PR2 (PR4) register. The PWM period can be calculated using Equation 17-1: EQUATION 17-1: PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 (TMR4) is equal to PR2 (PR4), the following three events occur on the next increment cycle: * TMR2 (TMR4) is cleared * The CCPx pin is set (exception: if PWM duty cycle = 0%, the CCPx pin will not be set) * The PWM duty cycle is latched from CCPRxL into CCPRxH Note: The Timer2 and Timer 4 postscalers (see Section 13.0 "Timer2 Module" and Section 15.0 "Timer4 Module") are not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. Figure 17-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up a CCP module for PWM operation, see Section 17.4.3 "Setup for PWM Operation". FIGURE 17-3: SIMPLIFIED PWM BLOCK DIAGRAM 0 Duty Cycle Register 9 CCPRxL Latch Duty Cycle CCPRxH (1) CCPxCON<5:4> Comparator Reset TMRx = PRx Match S R Q CCPx pin TMRx 2 LSbs latched from Q clocks Comparator 17.4.2 PWM DUTY CYCLE PRx Set CCPx pin Note 1: TRIS Output Enable The two LSbs of the Duty Cycle register are held by a 2-bit latch that is part of the module's hardware. It is physically separate from the CCPRx registers. The PWM duty cycle is specified by writing to the CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available. The CCPRxL contains the eight MSbs and the CCPxCON<5:4> contains the two LSbs. This 10-bit value is represented by CCPRxL:CCPxCON<5:4>. Equation 17-2 is used to calculate the PWM duty cycle in time. A PWM output (Figure 17-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). EQUATION 17-2: PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) * TOSC * (TMR2 Prescale Value) CCPRxL and CCPxCON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. FIGURE 17-4: Period PWM OUTPUT Duty Cycle TMR2 (TMR4) = PR2 (PR4) TMR2 (TMR4) = Duty Cycle TMR2 (TMR4) = PR2 (TMR4) DS39932C-page 246 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPRxH and 2-bit latch match TMR2 (TMR4), concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by Equation 17-3: 17.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. Set the PWM period by writing to the PR2 (PR4) register. Set the PWM duty cycle by writing to the CCPRxL register and CCPxCON<5:4> bits. Make the CCPx pin an output by clearing the appropriate TRIS bit. Set the TMR2 (TMR4) prescale value, then enable Timer2 (Timer4) by writing to T2CON (T4CON). Configure the CCPx module for PWM operation. EQUATION 17-3: PWM Resolution (max) = FOSC log( FPWM log(2) ) 5. bits Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 17-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz 2.44 kHz 16 FFh 10 9.77 kHz 4 FFh 10 39.06 kHz 1 FFh 10 156.25 kHz 1 3Fh 8 312.50 kHz 1 1Fh 7 416.67 kHz 1 17h 6.58 PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) (c) 2009 Microchip Technology Inc. DS39932C-page 247 PIC18F46J11 FAMILY TABLE 17-3: Name INTCON RCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 TRISG TMR2(1) PR2(1) T2CON TMR4 PR4(1) T4CON CCPR4L CCPR4H CCPR5L CCPR5H CCP4CON CCP5CON ODCON1(2) REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Bit 7 Bit 6 Bit 5 TMR0IE CM RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP -- Bit 4 INT0IE RI TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP TRISG4 Bit 3 RBIE TO SSP1IF SSP1IE SSP1IP TMR4IF TMR4IE TMR4IP TRISG3 Bit 2 TMR0IF PD CCP1IF CCP1IE CCP1IP CCP5IF CCP5IE CCP5IP TRISG2 Bit 1 INT0IF POR TMR2IF TMR2IE TMR2IP CCP4IF CCP4IE CCP4IP TRISG1 Bit 0 RBIF BOR TMR1IF TMR1IE TMR1IP CCP3IF CCP3IE CCP3IP TRISG0 Reset Values on Page: 63 64 65 65 65 65 65 65 65 64 64 64 67 67 67 67 67 67 67 CCP4M3 CCP5M3 CCP4M2 CCP5M2 CCP4M1 CCP5M1 CCP4M0 CCP5M0 67 67 68 GIE/GIEH PEIE/GIEL IPEN PMPIF PMPIE PMPIP SSP2IF SSP2IE SSP2IP -- Timer2 Register Timer2 Period Register -- -- ADIF ADIE ADIP BCL2IF BCL2IE BCL2IP -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 Timer4 Register Timer4 Period Register -- T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 Capture/Compare/PWM Register 4 Low Byte Capture/Compare/PWM Register 4 High Byte Capture/Compare/PWM Register 5 Low Byte Capture/Compare/PWM Register 5 High Byte -- -- -- -- -- -- DC4B1 DC5B1 -- DC4B0 DC5B0 CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PWM, Timer2 or Timer4. Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. DS39932C-page 248 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 17.5 PWM (Enhanced Mode) The Enhanced PWM mode can generate a PWM signal on up to four different output pins with up to 10 bits of resolution. It can do this through four different PWM Output modes: * * * * Single PWM Half-Bridge PWM Full-Bridge PWM, Forward mode Full-Bridge PWM, Reverse mode The PWM outputs are multiplexed with I/O pins and are designated: PxA, PxB, PxC and PxD. The polarity of the PWM pins is configurable and is selected by setting the CCPxM bits in the CCPxCON register appropriately. Table 17-1 provides the pin assignments for each Enhanced PWM mode. Figure 17-5 provides an example of a simplified block diagram of the Enhanced PWM module. Note: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal. To select an Enhanced PWM mode, the PxM bits of the CCPxCON register must be set appropriately. FIGURE 17-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DC1B<1:0> PxM<1:0> 2 CCPxM<3:0> 4 Duty Cycle Registers CCPR1L ECCPx/PxA(2) TRIS CCPR1H (Slave) Comparator R Q PxB(2) Output Controller PxC(2) TMR2 (1) S PxD(2) Clear Timer2, toggle PWM pin and latch duty cycle ECCP1DEL TRIS TRIS TRIS ECCP1/RPn RPn PRn Comparator PRn PR2 Note 1: 2: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. These pins are remappable. Note 1: The TRIS register value for each PWM output must be configured appropriately. 2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions. (c) 2009 Microchip Technology Inc. DS39932C-page 249 PIC18F46J11 FAMILY TABLE 17-4: ECCP Mode Single Half-Bridge Full-Bridge, Forward Full-Bridge, Reverse Note 1: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES PxM<1:0> 00 10 01 11 PxA Yes(1) Yes Yes Yes PxB Yes(1) Yes Yes Yes PxC Yes(1) No Yes Yes PxD Yes(1) No Yes Yes Outputs are enabled by pulse steering in Single mode (see Register 17-4). FIGURE 17-6: PxM<1:0> EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Signal 0 Pulse Width Period PR2 + 1 00 (Single Output) PxA Modulated Delay(1) PxA Modulated Delay(1) 10 (Half-Bridge) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (ECCPxDEL<6:0>) Note 1: Dead-band delay is programmed using the ECCPxDEL register (Section 17.5.6 "Programmable Dead-Band Delay Mode"). DS39932C-page 250 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 17-7: PxM<1:0> EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal 0 Pulse Width Period PR2 + 1 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay(1) PxB Modulated PxA Active Delay(1) 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (ECCPxDEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 17.5.6 "Programmable Dead-Band Delay Mode"). (c) 2009 Microchip Technology Inc. DS39932C-page 251 PIC18F46J11 FAMILY 17.5.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 17-8). This mode can be used for half-bridge applications, as shown in Figure 17-9, or for full-bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in half-bridge power devices. The value of the PxDC<6:0> bits of the ECCPxDEL register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 17.5.6 "Programmable Dead-Band Delay Mode" for more details of the dead-band delay operations. Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure PxA and PxB as outputs. FIGURE 17-8: EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period Period Pulse Width PxA(2) td PxB(2) (1) td (1) (1) td = Dead-Band Delay Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high. FIGURE 17-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit ("Push-Pull") FET Driver PxA + Load FET Driver PxB + - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET Driver PxA Load FET Driver FET Driver PxB FET Driver DS39932C-page 252 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 17.5.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of a full-bridge application is provided in Figure 17-10. In the Forward mode, the PxA pin is driven to its active state, the PxD pin is modulated, while the PxB and PxC pins will be driven to their inactive state as provided in Figure 17-11. In the Reverse mode, the PxC pin is driven to its active state, the PxB pin is modulated, while the PxA and PxD pins will be driven to their inactive state as provided Figure 17-11. The PxA, PxB, PxC and PxD outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs. FIGURE 17-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver PxA QA QC FET Driver PxB FET Driver Load FET Driver PxC QB QD VPxD (c) 2009 Microchip Technology Inc. DS39932C-page 253 PIC18F46J11 FAMILY FIGURE 17-11: Forward Mode Period PxA (2) EXAMPLE OF FULL-BRIDGE PWM OUTPUT Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) (1) Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. The output signal is shown as active-high. DS39932C-page 254 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 17.5.2.1 Direction Change in Full-Bridge Mode 1. 2. In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register. The following sequence occurs prior to the end of the current PWM period: * The modulated outputs (PxB and PxD) are placed in their inactive state. * The associated unmodulated outputs (PxA and PxC) are switched to drive in the opposite direction. * PWM modulation resumes at the beginning of the next period. See Figure 17-12 for an illustration of this sequence. The Full-Bridge mode does not provide a dead-band delay. As one output is modulated at a time, a dead-band delay is generally not required. There is a situation where a dead-band delay is required. This situation occurs when both of the following conditions are true: The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. Figure 17-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty cycle. In this example, at time, t1, the PxA and PxD outputs become inactive, while the PxC output becomes active. Since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current will flow through power devices, QC and QD (see Figure 17-10), for the duration of `t'. The same phenomenon will occur to power devices, QA and QB, for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. Reduce PWM duty cycle for one PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 17-12: Signal EXAMPLE OF PWM DIRECTION CHANGE Period(1) Period PxA (Active-High) PxB (Active-High) PxC (Active-High) PxD (Active-High) Pulse Width Note 1: 2: The direction bit, PxM1 of the CCPxCON register, is written any time during the PWM cycle. When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is: (1/FOSC) * TMR2 Prescale Value (2) Pulse Width (c) 2009 Microchip Technology Inc. DS39932C-page 255 PIC18F46J11 FAMILY FIGURE 17-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PxC PxD PW PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current T = TOFF - TON Note 1: 2: 3: All signals are shown as active-high. TON is the turn-on delay of power switch QC and its driver. TOFF is the turn-off delay of power switch QD and its driver. 17.5.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enabled is not recommended since it may result in damage to the application circuits. The PxA, PxB, PxC and PxD output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF or TMR4IF bit of the PIR1 or PIR3 register being set as the second PWM period begins. The CCPxM<1:0> bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (PxA/PxC and PxB/PxD). The PWM output DS39932C-page 256 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 17.5.4 ENHANCED PWM AUTO-SHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCPxAS<2:0> bits of the ECCPAS register. A shutdown event may be generated by: * A logic `0' on the pin that is assigned the FLT0 input function * Comparator C1 * Comparator C2 * Setting the ECCPxASE bit in firmware A shutdown condition is indicated by the ECCPxASE (Auto-Shutdown Event Status) bit of the ECCPxAS register. If the bit is a `0', the PWM pins are operating normally. If the bit is a `1', the PWM outputs are in the shutdown state. When a shutdown event occurs, two things happen: The ECCPxASE bit is set to `1'. The ECCPxASE will remain set until cleared in firmware or an auto-restart occurs (see Section 17.5.5 "Auto-Restart Mode"). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [PxA/PxC] and [PxB/PxD]. The state of each pin pair is determined by the PSSxAC and PSSxBD bits of the ECCPxAS register. Each pin pair may be placed into one of three states: * Drive logic `1' * Drive logic `0' * Tri-state (high-impedance) REGISTER 17-2: R/W-0 ECCPxASE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 ECCPxAS: ECCPx AUTO-SHUTDOWN CONTROL REGISTER (ACCESS FBEh/FB8h) R/W-0 R/W-0 ECCPxAS1 R/W-0 ECCPxAS0 R/W-0 PSSxAC1 R/W-0 PSSxAC0 R/W-0 PSSxBD1 R/W-0 PSSxBD0 bit 0 ECCPxAS2 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ECCPxASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in a shutdown state 0 = ECCP outputs are operating ECCPxAS<2:0>: ECCP Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator C1OUT output is high 010 = Comparator C2OUT output is high 011 = Either Comparator C1OUT or C2OUT is high 100 = VIL on FLT0 pin 101 = VIL on FLT0 pin or Comparator C1OUT output is high 110 = VIL on FLT0 pin or Comparator C2OUT output is high 111 = VIL on FLT0 pin or Comparator C1OUT or Comparator C2OUT is high PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits 00 = Drive pins PxA and PxC to `0' 01 = Drive pins PxA and PxC to `1' 1x = Pins PxA and PxC tri-state PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits 00 = Drive pins PxB and PxD to `0' 01 = Drive pins PxB and PxD to `1' 1x = Pins PxB and PxD tri-state bit 6-4 bit 3-2 bit 1-0 Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCPxASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period. (c) 2009 Microchip Technology Inc. DS39932C-page 257 PIC18F46J11 FAMILY FIGURE 17-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0) PWM Period Shutdown Event ECCPxASE bit PWM Activity Normal PWM Start of PWM Period Shutdown Event Occurs Shutdown Event Clears ECCPxASE Cleared by Firmware PWM Resumes 17.5.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit in the ECCPxDEL register. If auto-restart is enabled, the ECCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPxASE bit will be cleared via hardware and normal operation will resume. The module will wait until the next PWM period begins, however, before re-enabling the output pin. This behavior allows the auto-shutdown with auto-restart features to be used in applications based on current mode PWM control. FIGURE 17-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PxRSEN = 1) PWM Period Shutdown Event ECCPxASE bit PWM Activity Normal PWM Start of PWM Period Shutdown Event Occurs Shutdown Event Clears PWM Resumes DS39932C-page 258 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 17.5.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 17-16: In half-bridge applications, where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period until one switch completely turns off. During this brief interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In Half-Bridge mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 17-16 for illustration. The lower seven bits of the associated ECCPxDEL register (Register 17-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period Period Pulse Width PxA(2) td PxB(2) (1) td (1) (1) td = Dead-Band Delay Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high. FIGURE 17-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit ("Push-Pull") FET Driver PxA + V Load + V - FET Driver PxB V- (c) 2009 Microchip Technology Inc. DS39932C-page 259 PIC18F46J11 FAMILY REGISTER 17-3: R/W-0 PxRSEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ECCPxDEL: ENHANCED PWM CONTROL REGISTER (ACCESS FBDh/FB7h) R/W-0 R/W-0 PxDC5 R/W-0 PxDC4 R/W-0 PxDC3 R/W-0 PxDC2 R/W-0 PxDC1 R/W-0 PxDC0 bit 0 PxDC6 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPxASE must be cleared by software to restart the PWM PxDC<6:0>: PWM Delay Count bits PxDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active. bit 6-0 17.5.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can simultaneously be available on multiple pins. Once the Single Output mode is selected (CCPxM<3:2> = 11 and PxM<1:0> = 00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR While the PWM Steering mode is active, the CCPxM<1:0> bits of the CCPxCON register select the PWM output polarity for the Px DS39932C-page 260 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 17-4: R/W-0 CMPL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PSTRxCON: PULSE STEERING CONTROL (ACCESS FBFh/FB9h)(1) R/W-0 U-0 -- R/W-0 STRSYNC R/W-0 STRD R/W-0 STRC R/W-0 STRB R/W-1 STRA bit 0 CMPL0 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits 1 = Modulated output pin toggles between PxA and PxB for each period 0 = Complementary output assignment disabled; STRD:STRA bits used to determine Steering mode Unimplemented: Read as `0' STRSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary STRD: Steering Enable bit D 1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxD pin is assigned to port pin STRC: Steering Enable bit C 1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxC pin is assigned to port pin STRB: Steering Enable bit B 1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxB pin is assigned to port pin STRA: Steering Enable bit A 1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxA pin is assigned to port pin The PWM Steering mode is available only when the CCPxCON register bits, CCPxM<3:2> = 11 and PxM<1:0> = 00. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2009 Microchip Technology Inc. DS39932C-page 261 PIC18F46J11 FAMILY FIGURE 17-18: STRA PxA Signal CCPxM1 PORT Data STRB CCPxM0 PORT Data STRC CCPxM1 PORT Data STRD CCPxM0 PORT Data Note 1: 2: 1 0 1 0 TRIS 1 0 1 0 TRIS RPn pin SIMPLIFIED STEERING BLOCK DIAGRAM 17.5.7.1 Steering Synchronization RPn pin The STRSYNC bit of the PSTRxCON register gives the user two selections of when the steering event will happen. When the STRSYNC bit is `0', the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the Px TRIS RPn pin Figures 17-19 and 17-20 illustrate the timing diagrams of the PWM steering depending on the STRSYNC setting. RPn pin TRIS Port outputs are configured as displayed when the CCPxCON register bits, PxM<1:0> = 00 and CCP1M<3:2> = 11. Single PWM output requires setting at least one of the STRx bits. FIGURE 17-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0) PWM Period PWM STRn P1 PORT Data P1n = PWM PORT Data FIGURE 17-20: PWM STRn EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) P1 PORT Data P1n = PWM PORT Data DS39932C-page 262 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 17.5.8 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the ECCPx pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from HFINTOSC and the postscaler may not be stable immediately. In PRI_IDLE mode, the primary clock will continue to clock the ECCPx module without change. the PIR2 register will be set. The ECCPx will then be clocked from the internal oscillator clock source, which may have a different clock frequency than the primary clock. 17.5.9 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the ECCP registers to their Reset states. This forces the ECCP module to reset to a state compatible with previous, non-enhanced ECCP modules used on other PIC18 and PIC16 devices. 17.5.8.1 Operation with Fail-Safe Clock Monitor (FSCM) If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock failure will force the device into the power-managed RC_RUN mode and the OSCFIF bit of TABLE 17-5: Name INTCON RCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 TRISC TMR1L TMR1H TCLKCON T1CON TMR2 T2CON PR2 TMR3L TMR3H T3CON CCPR1L CCPR1H CCP1CON ECCP1AS ECCP1DEL Legend: Note 1: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Bit 7 Bit 6 PEIE/GIEL SBOREN ADIF ADIE ADIP CM2IF CM2IE CM2IP TRISC6 Bit 5 TMR0IE -- RCIF RCIE RCIP CM1IF CM1IE CM1IP TRISC5 Bit 4 INT0IE RI TXIF TXIE TXIP -- -- -- TRISC4 Bit 3 RABIE TO SSPIF SSPIE SSPIP BCL1IF BCL1IE BCL1IP TRISC3 Bit 2 TMR0IF PD CCP1IF CCP1IE CCP1IP LVDIF LVDIE LVDIP TRISC2 Bit 1 INT0IF POR TMR2IF TMR2IE TMR2IP TMR3IF TMR3IE TMR3IP TRISC1 Bit 0 RABIF BOR TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP TRISC0 Reset Values on page: 63 64 65 65 65 65 65 65 66 64 64 -- T1CKPS1 T1RUN T1CKPS0 -- T1OSCEN -- T1SYNC T3CCP2 RD16 T3CCP1 TMR1ON 87 64 64 64 64 67 67 T3CKPS1 T3CKPS0 -- T3SYNC RD16 TMR3ON 67 65 65 CCP1M3 PSS1AC1 P1DC3 CCP1M2 P1DC2 CCP1M1 P1DC1 CCP1M0 P1DC0 65 64 65 PSS1AC0 PSS1BD1 PSS1BD0 GIE/GIEH IPEN PMPIF(1) PMPIE(1) PMPIP(1) OSCFIF OSCFIE OSCFIP TRISC7 Timer1 Register Low Byte Timer1 Register High Byte -- TMR1CS1 -- Timer2 Register T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 Timer2 Period Register Timer3 Register Low Byte Timer3 Register High Byte TMR3CS1 TMR3CS0 Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte P1M1 P1RSEN P1M0 P1DC6 DC1B1 P1DC5 DC1B0 P1DC4 ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 -- TMR1CS0 -- = unimplemented, read as `0'. Shaded cells are not used during ECCP operation. These bits are only available on 44-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 263 PIC18F46J11 FAMILY NOTES: DS39932C-page 264 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE All of the MSSP1 module-related SPI and I2C I/O functions are hard-mapped to specific I/O pins. For MSSP2 functions: * SPI I/O functions (SDO2, SDI2, SCK2 and SS2) are all routed through the Peripheral Pin Select (PPS) module. These functions may be configured to use any of the RPn remappable pins, as described in Section 9.7 "Peripheral Pin Select (PPS)". * I2C functions (SCL2 and SDA2) have fixed pin locations. On all PIC18F46J11 family devices, the SPI DMA capability can only be used in conjunction with MSSP2. The SPI DMA feature is described in Section 18.4 "SPI DMA Module". Note: Throughout this section, generic references to an MSSP module in any of its operating modes may be interpreted as being equally applicable to MSSP1 or MSSP2. Register names and module I/O signals use the generic designator `x' to indicate the use of a numeral to distinguish a particular module when required. Control bit names are not individuated. The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices include serial EEPROMs, shift registers, display drivers and A/D Converters. 18.1 Master SSP (MSSP) Module Overview The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) - Full Master mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: * Master mode * Multi-Master mode * Slave mode with 5-bit and 7-bit address masking (with address masking for both 10-bit and 7-bit addressing) All members of the PIC18F46J11 family have two MSSP modules, designated as MSSP1 and MSSP2. The modules operate independently: * PIC18F4XJ11 devices - Both modules can be configured for either I2C or SPI communication * PIC18F2XJ11 devices: - MSSP1 can be used for either I2C or SPI communication - MSSP2 can be used only for SPI communication (c) 2009 Microchip Technology Inc. DS39932C-page 265 PIC18F46J11 FAMILY 18.2 Control Registers FIGURE 18-1: Each MSSP module has three associated control registers. These include a status register (SSPxSTAT) and two control registers (SSPxCON1 and SSPxCON2). The use of these registers and their individual Configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual sections. Note: In devices with more than one MSSP module, it is very important to pay close attention to the SSPxCON register names. SSP1CON1 and SSP1CON2 control different operational aspects of the same module, while SSP1CON1 and SSP2CON1 control the same features for two different modules. MSSPx BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read SSPxBUF reg Write SDIx SSPxSR reg SDOx bit 0 Shift Clock SSx SSx Control Enable Edge Select 2 Clock Select SSPM<3:0> SMP:CKE 4 (TMR2 Output 2 2 Edge Select 18.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. When MSSP2 is used in SPI mode, it can optionally be configured to work with the SPI DMA submodule described in Section 18.4 "SPI DMA Module". To accomplish communication, typically three pins are used: * Serial Data Out (SDOx) - RC7/RX1/DT1/SDO1/RP18 or SDO2/Remappable * Serial Data In (SDIx) - RB5/KBI1/SDI1/SDA1/RP8 or SDI2/Remappable * Serial Clock (SCKx) - RB4/KBI0/SCK1/SCL1/RP7 or SCK2/Remappable Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SSx) - RA5/AN4/SS1/ HLVDIN/RCV/RP2 or SS2/Remappable Figure 18-1 depicts the block diagram of the MSSP module when operating in SPI mode. SCKx ) Prescaler TOSC 4, 16, 64 Data to TXx/RXx in SSPxSR TRIS bit Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. DS39932C-page 266 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.3.1 REGISTERS Each MSSP module has four registers for SPI mode operation. These are: * MSSPx Control Register 1 (SSPxCON1) * MSSPx Status Register (SSPxSTAT) * Serial Receive/Transmit Buffer Register (SSPxBUF) * MSSPx Shift Register (SSPxSR) - Not directly accessible SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. REGISTER 18-1: R/W-1 SMP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 SSPxSTAT: MSSPx STATUS REGISTER - SPI MODE (ACCESS FC7h/F73h) R-1 D/A R-1 P R-1 S R-1 R/W R-1 UA R-1 BF bit 0 (1) R/W-1 CKE W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state D/A: Data/Address bit Used in I2CTM mode only. P: Stop bit Used in I2C mode only; this bit is cleared when the MSSP module is disabled, SSPEN is cleared. S: Start bit Used in I2C mode only. R/W: Read/Write Information bit Used in I2C mode only. UA: Update Address bit Used in I2C mode only. BF: Buffer Full Status bit 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Polarity of clock state is set by the CKP bit (SSPxCON1<4>). bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2009 Microchip Technology Inc. DS39932C-page 267 PIC18F46J11 FAMILY REGISTER 18-2: R/W-0 WCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SSPxCON1: MSSPx CONTROL REGISTER 1 - SPI MODE (ACCESS FC6H/F72h) R/W-0 SSPEN(2) R/W-0 CKP R/W-0 SSPM3(3) R/W-0 SSPM2(3) R/W-0 SSPM1(3) R/W-0 SSPM0(3) bit 0 R/W-0 SSPOV(1) WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, this pin must be properly configured as input or output. Bit combinations not specifically listed here, are either reserved or implemented in I2CTM mode only. bit 6 bit 5 bit 4 bit 3-0 Note 1: 2: 3: DS39932C-page 268 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: Master mode (SCKx is the clock output) Slave mode (SCKx is the clock input) Clock Polarity (Idle state of SCKx) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCKx) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) Each MSSP module consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full (BF) detect bit (SSPxSTAT<0>) and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the Write Collision Detect bit, WCOL (SSPxCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPxBUF register completed successfully. Note: When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of transfer data is written to the SSPxBUF. Application software should follow this process even when the current contents of SSPxBUF are not important. * * * * The Buffer Full bit, BF (SSPxSTAT<0>), indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 18-1 provides the loading of the SSPxBUF (SSPxSR) for data transmission. The SSPxSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various status conditions. 18.3.3 OPEN-DRAIN OUTPUT OPTION The drivers for the SDOx output and SCKx clock pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor, provided the SDOx or SCKx pin is not multiplexed with an ANx analog function. This allows the output to communicate with external circuits without the need for additional level shifters. For more information, see Section 9.1.4 "Open-Drain Outputs". The open-drain output option is controlled by the SPI2OD and SPI1OD bits (ODCON3<1:0>). Setting an SPIxOD bit configures both SDOx and SCKx pins for the corresponding open-drain operation. EXAMPLE 18-1: LOOP BTFSS BRA MOVF MOVWF MOVF MOVWF LOADING THE SSP1BUF (SSP1SR) REGISTER SSP1STAT, BF LOOP SSP1BUF, W RXDATA TXDATA, W SSP1BUF ;Has data been received (transmit complete)? ;No ;WREG reg = contents of SSP1BUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit (c) 2009 Microchip Technology Inc. DS39932C-page 269 PIC18F46J11 FAMILY 18.3.4 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPxCON1 registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins. For the pins to behave as the serial port function, the appropriate TRIS bits, ANCON/PCFG bits and Peripheral Pin Select registers (if using MSSP2) should be correctly initialized prior to setting the SSPEN bit. A typical SPI serial port initialization process follows: * Initialize ODCON3 register (optional open-drain output control) * Initialize remappable pin functions (if using MSSP2, see Section 9.7 "Peripheral Pin Select (PPS)") * Initialize SCKx LAT value to desired Idle SCK level (if master device) * Initialize SCKx ANCON/PCFG bit (if Slave mode and multiplexed with ANx function) * Initialize SCKx TRIS bit as output (Master mode) or input (Slave mode) * Initialize SDIx ANCON/PCFG bit (if SDIx is multiplexed with ANx function) * Initialize SDIx TRIS bit * Initialize SSx ANCON/PCFG bit (if Slave mode and multiplexed with ANx function) * Initialize SSx TRIS bit (Slave modes) * Initialize SDOx TRIS bit * Initialize SSPxSTAT register * Initialize SSPxCON1 register * Set SSPEN bit to enable the module Any MSSP1 serial port function that is not desired may be overridden by programming the corresponding Data Direction (TRIS) register to the opposite value. If individual MSSP2 serial port functions will not be used, they may be left unmapped. Note: When MSSP2 is used in SPI Master mode, the SCK2 function must be configured as both an output and input in the PPS module. SCK2 must be initialized as an output pin (by writing 0x0A to one of the RPORx registers). Additionally, SCK2IN must also be mapped to the same pin, by initializing the RPINR22 register. Failure to initialize SCK2/SCK2IN as both output and input will prevent the module from receiving data on the SDI2 pin, as the module uses the SCK2IN signal to latch the received data. 18.3.5 TYPICAL CONNECTION Figure 18-2 illustrates a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCKx signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends valid data - Slave sends dummy data * Master sends valid data - Slave sends valid data * Master sends dummy data - Slave sends valid data FIGURE 18-2: SPI MASTER/SLAVE CONNECTION SPI Slave SSPM<3:0> = 010xb SDOx SDIx SPI Master SSPM<3:0> = 00xxb Serial Input Buffer (SSPxBUF) Serial Input Buffer (SSPxBUF) Shift Register (SSPxSR) MSb LSb SDIx SDOx Shift Register (SSPxSR) MSb LSb SCKx PROCESSOR 1 Serial Clock SCKx PROCESSOR 2 DS39932C-page 270 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.3.6 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 2, Figure 18-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDIx pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. The CKP is selected by appropriately programming the CKP bit (SSPxCON1<4>). This then, would give waveforms for SPI communication as illustrated in Figure 18-3, Figure 18-5 and Figure 18-6, where the Most Significant Byte (MSB) is transmitted first. In Master mode, the SPI clock rate (bit rate) is user-programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 When using the Timer2 output/2 option, the Period Register 2 (PR2) can be used to determine the SPI bit rate. However, only PR2 values of 0x01 to 0xFF are valid in this mode. Figure 18-3 illustrates the waveforms for Master mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. FIGURE 18-3: Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx (CKE = 0) SDOx (CKE = 1) SDIx (SMP = 0) Input Sample (SMP = 0) SDIx (SMP = 1) Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF SPI MODE WAVEFORM (MASTER MODE) 4 Clock Modes bit 7 bit 7 bit 6 bit 6 bit 5 bit 5 bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 bit 7 bit 0 bit 7 bit 0 Next Q4 Cycle after Q2 (c) 2009 Microchip Technology Inc. DS39932C-page 271 PIC18F46J11 FAMILY 18.3.7 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device can be configured to wake-up from Sleep. transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with pin control enabled the SSx (SSPxCON1<3:0> = 0100), the SPI module will reset if the SSx pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SSx pin control must be enabled. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SSx pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDOx pin can be connected to the SDIx pin. When the SPI needs to operate as a receiver, the SDOx pin can be configured as an input. This disables transmissions from the SDOx. The SDIx can always be left as an input (SDIx function) since it cannot create a bus conflict. 18.3.8 SLAVE SELECT SYNCHRONIZATION The SSx pin allows a Synchronous Slave mode. The SPI must be in Slave mode with the SSx pin control enabled (SSPxCON1<3:0> = 04h). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a FIGURE 18-4: SSx SLAVE SYNCHRONIZATION WAVEFORM SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 7 bit 0 SDIx (SMP = 0) Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF bit 0 bit 7 bit 7 Next Q4 Cycle after Q2 DS39932C-page 272 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 18-5: SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) bit 7 bit 0 Next Q4 Cycle after Q2 FIGURE 18-6: SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx SDIx (SMP = 0) Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 Next Q4 Cycle after Q2 (c) 2009 Microchip Technology Inc. DS39932C-page 273 PIC18F46J11 FAMILY 18.3.9 OPERATION IN POWER-MANAGED MODES 18.3.11 BUS MODE COMPATIBILITY In SPI Master mode, module clocks may be operating at a different speed than when in full-power mode. In the case of Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the secondary clock (Timer1 oscillator) or the INTOSC source. See Section 2.3 "Clock Sources and Oscillator Switching" for additional information. In most cases, the speed that the master clocks SPI data is not important; however, this should be evaluated for each system. If MSSP interrupts are enabled, they can wake the controller from Sleep mode, or one of the Idle modes, when the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts should be disabled. If the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set, and if enabled, will wake the device. Table 18-1 provides the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 18-1: SPI BUS MODES Control Bits State CKP 0 0 1 1 CKE 1 0 1 0 Standard SPI Mode Terminology 0, 0 0, 1 1, 0 1, 1 There is also an SMP bit, which controls when the data is sampled. 18.3.12 SPI CLOCK SPEED AND MODULE INTERACTIONS Because MSSP1 and MSSP2 are independent modules, they can operate simultaneously at different data rates. Setting the SSPM<3:0> bits of the SSPxCON1 register determines the rate for the corresponding module. An exception is when both modules use Timer2 as a time base in Master mode. In this instance, any changes to the Timer2 module's operation will affect both MSSP modules equally. If different bit rates are required for each module, the user should select one of the other three time base options for one of the modules. 18.3.10 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. DS39932C-page 274 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 18-2: Name INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 TRISB TRISC TRISD SSP1BUF SSPxCON1 SSPxSTAT SSP2BUF ODCON3(1) REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP TRISB4 TRISC4 TRISD4 CKP P -- Bit 3 RBIE SSP1IF SSP1IE SSP1IP TMR4IF TMR4IE TMR4IP TRISB3 TRISC3 TRISD3 SSPM3 S -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP CTMUIF CTMUIE CTMUIP TRISB2 TRISC2 TRISD2 SSPM2 R/W -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3GIF TMR3GIE TMR3GIP TRISB1 TRISC1 TRISD1 SSPM1 UA SPI2OD Bit 0 RBIF TMR1IF TMR1IE TMR1IP RTCCIF RTCCIE RTCCIP TRISB0 TRISC0 TRISD0 SSPM0 BF SPI1OD Reset Values on Page: 63 65 65 65 65 65 65 66 66 66 64 64 64 67 68 GIE/GIEH PEIE/GIEL TMR0IE PMPIF (2) ADIF ADIE ADIP BCL2IF BCL2IE BCL2IP TRISB6 TRISC6 TRISD6 SSPOV CKE -- RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP TRISB5 TRISC5 TRISD5 SSPEN D/A -- PMPIE(2) PMPIP(2) SSP2IF SSP2IE SSP2IP TRISB7 TRISC7 TRISD7 WCOL SMP -- MSSP1 Receive Buffer/Transmit Register MSSP2 Receive Buffer/Transmit Register Legend: Shaded cells are not used by the MSSP module in SPI mode. Note 1: Configuration SFR overlaps with default SFR at this address; available only when WDTCON<4> = 1. 2: These bits are only available on 44-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 275 PIC18F46J11 FAMILY 18.4 SPI DMA Module The SPI DMA module contains control logic to allow the MSSP2 module to perform SPI direct memory access transfers. This enables the module to quickly transmit or receive large amounts of data with relatively little CPU intervention. When the SPI DMA module is used, MSSP2 can directly read and write to general purpose SRAM. When the SPI DMA module is not enabled, MSSP2 functions normally, but without DMA capability. The SPI DMA module is composed of control logic, a Destination Receive Address Pointer, a Transmit Source Address Pointer, an interrupt manager and a Byte Count register for setting the size of each DMA transfer. The DMA module may be used with all SPI Master and Slave modes, and supports both half-duplex and full-duplex transfers. In SPI Slave modes, the MSSP2 module is capable of transmitting and/or receiving one byte of data while in Sleep mode. This allows the SSP2IF flag in the PIR3 register to be used as a wake-up source. When the DMAEN bit is cleared, the SPI DMA module is effectively disabled, and the MSSP2 module functions normally, but without DMA capabilities. If the DMAEN bit is clear prior to entering Sleep, it is still possible to use the SSP2IF as a wake-up source without any data loss. Neither MSSP2 nor the SPI DMA module will provide any functionality in Deep Sleep. Upon exiting from Deep Sleep, all of the I/O pins, MSSP2 and SPI DMA related registers will need to be fully reinitialized before the SPI DMA module can be used again. 18.4.4 REGISTERS 18.4.1 I/O PIN CONSIDERATIONS When enabled, the SPI DMA module uses the MSSP2 module. All SPI related input and output signals related to MSSP2 are routed through the Peripheral Pin Select module. The appropriate initialization procedure as described in Section 18.4.6 "Using the SPI DMA Module" will need to be followed prior to using the SPI DMA module. The output pins assigned to the SDO2 and SCK2 functions can optionally be configured as open-drain outputs, such as for level shifting operations mentioned in the same section. The SPI DMA engine is enabled and controlled by the following Special Function Registers: * DMACON1 * TXADDRH * RXADDRH * DMABCH * DMACON2 * TXADDRL * RXADDRL * DMABCL 18.4.4.1 DMACON1 18.4.2 RAM TO RAM COPY OPERATIONS The DMACON1 register is used to select the main operating mode of the SPI DMA module. The SSCON1 and SSCON0 bits are used to control the slave select pin. When MSSP2 is used in SPI Master mode with the SPI DMA module, SSDMA can be controlled by the DMA module as an output pin. If MSSP2 will be used to communicate with an SPI slave device that needs the SS pin to be toggled periodically, the SPI DMA hardware can automatically be used to deassert SS between each byte, every two bytes or every four bytes. Alternatively, user firmware can manually generate slave select signals with normal general purpose I/O pins, if required by the slave device(s). When the TXINC bit is set, the TXADDR register will automatically increment after each transmitted byte. Automatic transmit address increment can be disabled by clearing the TXINC bit. If the automatic transmit address increment is disabled, each byte which is output on SDO2, will be the same (the contents of the SRAM pointed to by the TXADDR register) for the entire DMA transaction. Although the SPI DMA module is primarily intended to be used for SPI communication purposes, the module can also be used to perform RAM to RAM copy operations. To do this, configure the module for Full-Duplex Master mode operation, but assign the SDO2 output and SDI2 input functions onto the same RPn pin in the PPS module. This will allow the module to operate in Loopback mode, providing RAM copy capability. 18.4.3 IDLE AND SLEEP CONSIDERATIONS The SPI DMA module remains fully functional when the microcontroller is in Idle mode. During normal sleep, the SPI DMA module is not functional and should not be used. To avoid corrupting a transfer, user firmware should be careful to make certain that pending DMA operations are complete by polling the DMAEN bit in the DMACON1 register prior to putting the microcontroller into Sleep. DS39932C-page 276 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY When the RXINC bit is set, the RXADDR register will automatically increment after each received byte. Automatic receive address increment can be disabled by clearing the RXINC bit. If RXINC is disabled in Full-Duplex or Half-Duplex Receive modes, all incoming data bytes on SDI2 will overwrite the same memory location pointed to by the RXADDR register. After the SPI DMA transaction has completed, the last received byte will reside in the memory location pointed to by the RXADDR register. The SPI DMA module can be used for either half-duplex receive only communication, half-duplex transmit only communication or full-duplex simultaneous transmit and receive operations. All modes are available for both SPI master and SPI slave configurations. The DUPLEX0 and DUPLEX1 bits can be used to select the desired operating mode. The behavior of the DLYINTEN bit varies greatly depending on the SPI operating mode. For example behavior for each of the modes, see Figure 18-3 through Figure 18-6. SPI Slave mode, DLYINTEN = 1: In this mode, an SSP2IF interrupt will be generated during a transfer if the time between successful byte transmission events is longer than the value set by the DLYCYC<3:0> bits in the DMACON2 register. This interrupt allows slave firmware to know that the master device is taking an unusually large amount of time between byte transmissions. For example, this information may be useful for implementing application-defined communication protocols involving time-outs if the bus remains Idle for too long. When DLYINTEN = 1, the DLYLVL<3:0> interrupts occur normally according to the selected setting. SPI Slave mode, DLYINTEN = 0: In this mode, the time-out based interrupt is disabled. No additional SSP2IF interrupt events will be generated by the SPI DMA module, other than those indicated by the INTLVL<3:0> bits in the DMACON2 register. In this mode, always set DLYCYC<3:0> = 0000. SPI Master mode, DLYINTEN = 0: The DLYCYC<3:0> bits in the DMACON2 register determine the amount of additional inter-byte delay, which is added by the SPI DMA module during a transfer. The Master mode SS2 output feature may be used. SPI Master mode, DLYINTEN = 1: The amount of hardware overhead is slightly reduced in this mode, and the minimum inter-byte delay is 8 TCY for FOSC/4, 9 TCY for FOSC/16 and 15 TCY for FOSC/64. This mode can potentially be used to obtain slightly higher effective SPI bandwidth. In this mode, the SS2 control feature cannot be used, and should always be disabled (DMACON1<7:6> = 00). Additionally, the interrupt generating hardware (used in Slave mode) remains active. To avoid extraneous SSP2IF interrupt events, set the DMACON2 delay bits, DLYCYC<3:0> = 1111, and ensure that the SPI serial clock rate is no slower than FOSC/64. In SPI Master modes, the DMAEN bit is used to enable the SPI DMA module and to initiate an SPI DMA transaction. After user firmware sets the DMAEN bit, the DMA hardware will begin transmitting and/or receiving data bytes according to the configuration used. In SPI Slave modes, setting the DMAEN bit will finish the initialization steps needed to prepare the SPI DMA module for communication (which must still be initiated by the master device). To avoid possible data corruption, once the DMAEN bit is set, user firmware should not attempt to modify any of the MSSP2 or SPI DMA related registers, with the exception of the INTLVL bits in the DMACON2 register. If user firmware wants to halt an ongoing DMA transaction, the DMAEN bit can be manually cleared by the firmware. Clearing the DMAEN bit while a byte is currently being transmitted will not immediately halt the byte in progress. Instead, any byte currently in progress will be completed before the MSSP2 and SPI DMA modules go back to their Idle conditions. If user firmware clears the DMAEN bit, the TXADDR, RXADDR and DMABC registers will no longer update, and the DMA module will no longer make any additional read or writes to SRAM; therefore, state information can be lost. (c) 2009 Microchip Technology Inc. DS39932C-page 277 PIC18F46J11 FAMILY REGISTER 18-3: R/W-0 SSCON1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DMACON1: DMA CONTROL REGISTER 1 (ACCESS F88h) R/W-0 R/W-0 TXINC R/W-0 RXINC R/W-0 DUPLEX1 R/W-0 DUPLEX0 R/W-0 DLYINTEN R/W-0 DMAEN bit 0 SSCON0 SSCON<1:0>: SSDMA Output Control bits (Master modes only) 11 = SSDMA is asserted for the duration of 4 bytes; DLYINTEN is always reset low 01 = SSDMA is asserted for the duration of 2 bytes; DLYINTEN is always reset low 10 = SSDMA is asserted for the duration of 1 byte; DLYINTEN is always reset low 00 = SSDMA is not controlled by the DMA module; DLYINTEN bit is software programmable TXINC: Transmit Address Increment Enable bit Allows the transmit address to increment as the transfer progresses. 1 = The transmit address is to be incremented from the initial value of TXADDR<11:0> 0 = The transmit address is always set to the initial value of TXADDR<11:0> RXINC: Receive Address Increment Enable bit Allows the receive address to increment as the transfer progresses. 1 = The received address is to be incremented from the intial value of RXADDR<11:0> 0 = The received address is always set to the initial value of RXADDR<11:0> DUPLEX<1:0>: Transmit/Receive Operating Mode Select bits 10 = SPI DMA operates in Full-Duplex mode, data is simultaneously transmitted and received 01 = DMA operates in Half-Duplex mode, data is transmitted only 00 = DMA operates in Half-Duplex mode, data is received only DLYINTEN: Delay Interrupt Enable bit Enables the interrupt to be invoked after the number of SCK cycles specified in DLYCYC<2:0> has elapsed from the latest completed transfer. 1 = The interrupt is enabled, SSCON<1:0> must be set to `00' 0 = The interrupt is disabled DMAEN: DMA Operation Start/Stop bit This bit is set by the users' software to start the DMA operation. It is reset back to zero by the DMA engine when the DMA operation is completed or aborted. 1 = DMA is in session 0 = DMA is not in session bit 5 bit 4 bit 3-2 bit 1 bit 0 DS39932C-page 278 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.4.4.2 DMACON2 The DMACON2 register contains control bits for controlling interrupt generation and inter-byte delay behavior. The INTLVL<3:0> bits are used to select when an SSP2IF interrupt should be generated.The function of the DLYCYC<3:0> bits depends on the SPI operating mode (Master/Slave), as well as the DLYINTEN setting. In SPI Master mode, the DLYCYC<3:0> bits can be used to control how much time the module will Idle between bytes in a transfer. By default, the hardware requires a minimum delay of: 8 TCY for FOSC/4, 9 TCY for FOSC/16 and 15 TCY for FOSC/64. Additional delays can be added with the DLYCYC bits. In SPI Slave modes, the DLYCYC<3:0> bits may optionally be used to trigger an additional time-out based interrupt. REGISTER 18-4: R/W-0 DLYCYC3 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 DMACON2: DMA CONTROL REGISTER 2 (ACCESS F86h) R/W-0 R/W-0 DLYCYC1 R/W-0 DLYCYC0 R/W-0 INTLVL3 R/W-0 INTLVL2 R/W-0 INTLVL1 R/W-0 INTLVL0 bit 0 DLYCYC2 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DLYCYC<3:0>: Delay Cycle Selection bits When DLYINTEN = 0, these bits specify the additional delay (above the base overhead of the hardware) in number of TCY cycles before the SSP2BUF register is written again for the next transfer. When DLYINTEN = 1, these bits specify the additional delay in number of TCY cycles from the latest completed transfer before an interrupt to the CPU is invoked. In this case, the delay before the SSP2BUF register is written again is 1 TCY + (base overhead of hardware). 1111 = Delay time in number of instruction cycles is 2,048 cycles 1110 = Delay time in number of instruction cycles is 1,024 cycles 1101 = Delay time in number of instruction cycles is 896 cycles 1100 = Delay time in number of instruction cycles is 768 cycles 1011 = Delay time in number of instruction cycles is 640 cycles 1010 = Delay time in number of instruction cycles is 512 cycles 1001 = Delay time in number of instruction cycles is 384 cycles 1000 = Delay time in number of instruction cycles is 256 cycles 0111 = Delay time in number of instruction cycles is 128 cycles 0110 = Delay time in number of instruction cycles is 64 cycles 0101 = Delay time in number of instruction cycles is 32 cycles 0100 = Delay time in number of instruction cycles is 16 cycles 0011 = Delay time in number of instruction cycles is 8 cycles 0010 = Delay time in number of instruction cycles is 4 cycles 0001 = Delay time in number of instruction cycles is 2 cycles 0000 = Delay time in number of instruction cycles is 1 cycle (c) 2009 Microchip Technology Inc. DS39932C-page 279 PIC18F46J11 FAMILY REGISTER 18-4: bit 3-0 DMACON2: DMA CONTROL REGISTER 2 (ACCESS F86h) (CONTINUED) INTLVL<3:0>: Watermark Interrupt Enable bits These bits specify the amount of remaining data yet to be transferred (transmitted and/or received) upon which an interrupt is generated. 1111 = Amount of remaining data to be transferred is 576 bytes 1110 = Amount of remaining data to be transferred is 512 bytes 1101 = Amount of remaining data to be transferred is 448 bytes 1100 = Amount of remaining data to be transferred is 384 bytes 1011 = Amount of remaining data to be transferred is 320 bytes 1010 = Amount of remaining data to be transferred is 256 bytes 1001 = Amount of remaining data to be transferred is 192 bytes 1000 = Amount of remaining data to be transferred is 128 bytes 0111 = Amount of remaining data to be transferred is 67 bytes 0110 = Amount of remaining data to be transferred is 32 bytes 0101 = Amount of remaining data to be transferred is 16 bytes 0100 = Amount of remaining data to be transferred is 8 bytes 0011 = Amount of remaining data to be transferred is 4 bytes 0010 = Amount of remaining data to be transferred is 2 bytes 0001 = Amount of remaining data to be transferred is 1 byte 0000 = Transfer complete DS39932C-page 280 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.4.4.3 DMABCH and DMABCL The DMABCH and DMABCL register pair forms a 10-bit Byte Count register, which is used by the SPI DMA module to send/receive up to 1,024 bytes for each DMA transaction. When the DMA module is actively running (DMAEN = 1), the DMA Byte Count register decrements after each byte is transmitted/received. The DMA transaction will halt and the DMAEN bit will be automatically cleared by hardware after the last byte has completed. After a DMA transaction is complete, the DMABC register will read 0x000. Prior to initiating a DMA transaction by setting the DMAEN bit, user firmware should load the appropriate value into the DMABCH/DMABCL registers. The DMABC is a "base zero" counter, so the actual number of bytes which will be transmitted follows in Equation 18-1. For example, if user firmware wants to transmit 7 bytes in one transaction, DMABC should be loaded with 006h. Similarly, if user firmware wishes to transmit 1,024 bytes, DMABC should be loaded with 3FFh. The SPI DMA module can write received data to all general purpose memory on the device. The SPI DMA module cannot be used to modify the Special Function Registers contained in banks 14 and 15. 18.4.5 INTERRUPTS The SPI DMA module alters the behavior of the SSP2IF interrupt flag. In normal/non-DMA modes, the SSP2IF is set once after every single byte is transmitted/received through the MSSP2 module. When MSSP2 is used with the SPI DMA module, the SSP2IF interrupt flag will be set according to the user-selected INTLVL<3:0> value specified in the DMACON2 register. The SSP2IF interrupt condition will also be generated once the SPI DMA transaction has fully completed, and the DMAEN bit has been cleared by hardware. The SSP2IF flag becomes set once the DMA byte count value indicates that the specified INTLVL has been reached. For example, if DMACON2<3:0> = 0101 (16 bytes remaining), the SSP2IF interrupt flag will become set once DMABC reaches 00Fh. If user firmware then clears the SSP2IF interrupt flag, the flag will not be set again by the hardware until after all bytes have been fully transmitted and the DMA transaction is complete. Note: User firmware may modify the INTLVL bits while a DMA transaction is in progress (DMAEN = 1). If an INTLVL value is selected which is higher than the actual remaining number of bytes (indicated by DMABC + 1), the SSP2IF interrupt flag will immediately become set. EQUATION 18-1: BYTES TRANSMITTED FOR A GIVEN DMABC Bytes XMIT ( DMABC + 1 ) 18.4.4.4 TXADDRH and TXADDRL The TXADDRH and TXADDRL registers pair together to form a 12-bit Transmit Source Address Pointer register. In modes that use TXADDR (Full-Duplex and Half-Duplex Transmit), the TXADDR will be incremented after each byte is transmitted. Transmitted data bytes will be taken from the memory location pointed to by the TXADDR register. The contents of the memory locations pointed to by TXADDR will not be modified by the DMA module during a transmission. The SPI DMA module can read from and transmit data from all general purpose memory on the device. The SPI DMA module cannot be used to read from the Special Function Registers (SFRs) contained in banks 14 and 15. For example, if DMABC = 00Fh (implying 16 bytes are remaining) and user firmware writes `1111' to INTLVL<3:0> (interrupt when 576 bytes remaining), the SSP2IF interrupt flag will immediately become set. If user firmware clears this interrupt flag, a new interrupt condition will not be generated until either: user firmware again writes INTLVL with an interrupt level higher than the actual remaining level, or the DMA transaction completes and the DMAEN bit is cleared. Note: If the INTLVL bits are modified while a DMA transaction is in progress, care should be taken to avoid inadvertently changing the DLYCYC<3:0> value. 18.4.4.5 RXADDRH and RXADDRL The RXADDRH and RXADDRL register pair together to form a 12-bit Receive Destination Address Pointer. In modes that use RXADDR (Full-Duplex and Half-Duplex Receive), the RXADDR register will be incremented after each byte is received. Received data bytes will be stored at the memory location pointed to by the RXADDR register. (c) 2009 Microchip Technology Inc. DS39932C-page 281 PIC18F46J11 FAMILY 18.4.6 USING THE SPI DMA MODULE 4. The following steps would typically be taken to enable and use the SPI DMA module: 1. Configure the I/O pins, which will be used by MSSP2. a) Assign SCK2, SDO2, SDI2 and SS2 to RPn pins as appropriate for the SPI mode which will be used. Only functions which will be used need to be assigned to a pin. b) Initialize the associated LATx registers for the desired Idle SPI bus state. c) If Open-Drain Output mode on SDO2 and SCK2 (Master mode) is desired, set ODCON3<1>. d) Configure corresponding TRISx bits for each I/O pin used Configure and enable MSSP2 for the desired SPI operating mode. a) Select the desired operating mode (Master or Slave, SPI Mode 0, 1, 2 and 3) and configure the module by writing to the SSP2STAT and SSP2CON1 registers. b) Enable MSSP2 by setting SSP2CON1<5> = 1. Configure the SPI DMA engine. a) Select the desired operating mode by writing the appropriate values to DMACON2 and DMACON1. b) Initialize the TXADDRH/TXADDRL Pointer (Full-Duplex or Half-Duplex Transmit Only mode). c) Initialize the RXADDRH/RXADDRL Pointer (Full-Duplex or Half-Duplex Receive Only mode). d) Initialize the DMABCH/DMABCL Byte Count register with the number of bytes to be transferred in the next SPI DMA operation. e) Set the DMAEN bit (DMACON1<0>). In SPI Master modes, this will initiate a DMA transaction. In SPI Slave modes, this will complete the initialization process, and the module will now be ready to begin receiving and/or transmitting data to the master device once the master starts the transaction. Detect the SSP2IF interrupt condition (PIR3<7). a) If the interrupt was configured to occur at the completion of the SPI DMA transaction, the DMAEN bit (DMACON1<0>) will be clear. User firmware may prepare the module for another transaction by repeating steps 3.b through 3.e. b) If the interrupt was configured to occur prior to the completion of the SPI DMA transaction, the DMAEN bit may still be set, indicating the transaction is still in progress. User firmware would typically use this interrupt condition to begin preparing new data for the next DMA transaction. Firmware should not repeat steps 3.b. through 3.e. until the DMAEN bit is cleared by the hardware, indicating the transaction is complete. 2. Example 18-2 provides example code demonstrating the initialization process and the steps needed to use the SPI DMA module to perform a 512-byte Full-Duplex, Master mode transfer. 3. DS39932C-page 282 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY EXAMPLE 18-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER ;For this example, let's use RP5(RB2) for SCK2, ;RP4(RB1) for SDO2, and RP3(RB0) for SDI2 ;Let's use SPI master mode, CKE = 0, CKP = 0, ;without using slave select signalling. InitSPIPins: movlb bcf bcf bcf bcf bcf bsf 0x0F ODCON3, SPI2OD LATB, RB2 LATB, RB1 TRISB, RB1 TRISB, RB2 TRISB, RB0 ;Select bank 15, for access to ODCON3 register ;Let's not use open drain outputs in this example ;Initialize our (to be) SCK2 ;Initialize our (to be) SDO2 ;Make SDO2 output, and drive ;Make SCK2 output, and drive ;SDI2 is an input, make sure pin low (idle). pin to an idle state low low (idle state) it is tri-stated ;Now we should unlock the PPS registers, so we can ;assign the MSSP2 functions to our desired I/O pins. movlb bcf movlw movwf movlw movwf bcf bsf movlw movwf movlw movwf movlw movwf movlw movwf bsf movlb InitMSSP2: clrf movlw movwf bsf InitSPIDMA: movlw movwf movlw movwf 0x0E INTCON, GIE 0x55 EECON2 0xAA EECON2 PPSCON, IOLOCK INTCON, GIE 0x03 RPINR21 0x0A RPOR4 0x04 RPINR22 0x09 RPOR5 PPSCON, IOLOCK 0x0F ;Select bank 14 for access to PPS registers ;I/O Pin unlock sequence will not work if CPU ;services an interrupt during the sequence ;Unlock sequence consists of writing 0x55 ;and 0xAA to the EECON2 register. ;We may now write to RPINRx and RPORx registers ;May now turn back on interrupts if desired ;0x0A is SCK2 output signal ;Assign the SDI2 function to pin RP3 ;Let's assign SCK2 output to pin RP4 ;RPOR4 maps output signals to RP4 pin ;SCK2 also needs to be configured as an input on the same pin ;SCK2 input function taken from RP4 pin ;0x09 is SDO2 output ;Assign SDO2 output signal to the RP5 (RB2) pin ;Lock the PPS registers to prevent changes ;Done with PPS registers, bank 15 has other SFRs SSP2STAT b'00000000' SSP2CON1 SSP2CON1, SSPEN ;CKE = 0, SMP = 0 (sampled at middle of bit) ;CKP = 0, SPI Master mode, Fosc/4 ;MSSP2 initialized ;Enable the MSSP2 module b'00111110' DMACON1 b'11110000' DMACON2 ;Full duplex, RX/TXINC enabled, no SSCON ;DLYINTEN is set, so DLYCYC3:DLYCYC0 = 1111 ;Minimum delay between bytes, interrupt ;only once when the transaction is complete (c) 2009 Microchip Technology Inc. DS39932C-page 283 PIC18F46J11 FAMILY EXAMPLE 18-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER (CONTINUED) ;Somewhere else in our project, lets assume we have ;allocated some RAM for use as SPI receive and ;transmit buffers. ; ;DestBuf ; ;SrcBuf ; udata res res 0x500 0x200 0x200 ;Let's reserve 0x500-0x6FF for use as our SPI ;receive data buffer in this example ;Lets reserve 0x700-0x8FF for use as our SPI ;transmit data buffer in this example PrepareTransfer: movlw HIGH(DestBuf) movwf RXADDRH movlw LOW(DestBuf) movwf RXADDRL movlw movwf movlw movwf movlw movwf movlw movwf BeginXfer: bsf HIGH(SrcBuf) TXADDRH LOW(SrcBuf) TXADDRL 0x01 DMABCH 0xFF DMABCL ;Get high byte of DestBuf address (0x05) ;Load upper four bits of the RXADDR register ;Get low byte of the DestBuf address (0x00) ;Load lower eight bits of the RXADDR register ;Get high byte of SrcBuf address (0x07) ;Load upper four bits of the TXADDR register ;Get low byte of the SrcBuf address (0x00) ;Load lower eight bits of the TXADDR register ;Lets move 0x200 (512) bytes in one DMA xfer ;Load the upper two bits of DMABC register ;Actual bytes transferred is (DMABC + 1), so ;we load 0x01FF into DMABC to xfer 0x200 bytes DMACON1, DMAEN ;The SPI DMA module will now begin transferring ;the data taken from SrcBuf, and will store ;received bytes into DestBuf. ;CPU is now free to do whatever it wants to ;and the DMA operation will continue without ;intervention, until it completes. ;When the transfer is complete, the SSP2IF flag in ;the PIR3 register will become set, and the DMAEN bit ;is automatically cleared by the hardware. ;The DestBuf (0x500-0x7FF) will contain the received ;data. To start another transfer, firmware will need ;to reinitialize RXADDR, TXADDR, DMABC and then ;set the DMAEN bit. ;Execute whatever DS39932C-page 284 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.5 I2C Mode 18.5.1 REGISTERS The MSSP module in I2C mode fully implements all master and slave functions (including general call support), and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications and 7-bit and 10-bit addressing. Two pins are used for data transfer: * Serial Clock (SCLx) - RB4/PMA1/KBI0/SCK1/SCL1/RP7 or RD0/PMD0/SCL2 * Serial Data (SDAx) - RB5/PMA0/KBI1/SDI1/SDA1/RP8 or RD1/PMD1/SDA2 The user must configure these pins as inputs by setting the associated TRIS bits. The MSSP module has six registers for I2C operation. These are: * * * * MSSPx Control Register 1 (SSPxCON1) MSSPx Control Register 2 (SSPxCON2) MSSPx Status Register (SSPxSTAT) Serial Receive/Transmit Buffer Register (SSPxBUF) * MSSPx Shift Register (SSPxSR) - Not directly accessible * MSSPx Address Register (SSPxADD) * MSSPx 7-Bit Address Mask Register (SSPxMSK) SSPxCON1, SSPxCON2 and SSPxSTAT are the control and status registers in I2C mode operation. The SSPxCON1 and SSPxCON2 registers are readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. SSPxADD contains the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator (BRG) reload value. SSPxMSK holds the slave address mask value when the module is configured for 7-Bit Address Masking mode. While it is a separate register, it shares the same SFR address as SSPxADD; it is only accessible when the SSPM<3:0> bits are specifically set to permit access. Additional details are provided in Section 18.5.3.4 "7-Bit Address Masking Mode". In receive operations, SSPxSR and SSPxBUF together, create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. Set, Reset S, P bits (SSPxSTAT reg) FIGURE 18-7: MSSPx BLOCK DIAGRAM (I2CTM MODE) Internal Data Bus Read SCLx Shift Clock SSPxSR reg SDAx MSb SSPxBUF reg Write LSb Addr Match Match Detect Address Mask SSPxADD reg Start and Stop bit Detect During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. (c) 2009 Microchip Technology Inc. DS39932C-page 285 PIC18F46J11 FAMILY REGISTER 18-5: R/W-1 SMP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SSPxSTAT: MSSPx STATUS REGISTER - I2CTM MODE (ACCESS FC7h/F73h) R-1 D/A R-1 P (1) R/W-1 CKE R-1 S (1) R-1 R/W (2,3) R-1 UA R-1 BF bit 0 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last R/W: Read/Write Information bit(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) This bit is cleared on Reset and when SSPEN is cleared. This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: DS39932C-page 286 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 18-6: R/W-0 WCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SSPxCON1: MSSPx CONTROL REGISTER 1 - I2CTM MODE (ACCESS FC6h/F72h) R/W-0 SSPEN (1) R/W-0 SSPOV R/W-0 CKP R/W-0 SSPM3(2) R/W-0 SSPM2(2) R/W-0 SSPM1(2) R/W-0 SSPM0(2) bit 0 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit. SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode. SSPEN: Master Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins CKP: SCKx Release Control bit In Slave mode: 1 = Releases clock 0 = Holds clock low (clock stretch); used to ensure data setup time In Master mode: Unused in this mode. SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(2) 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1001 = Load SSPxMSK register at SSPxADD SFR address(3,4) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address When enabled, the SDAx and SCLx pins must be configured as inputs. Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. When SSPM<3:0> = 1001, any reads or writes to the SSPxADD SFR address actually accesses the SSPxMSK register. This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit is `1'). bit 6 bit 5 bit 4 bit 3-0 Note 1: 2: 3: 4: (c) 2009 Microchip Technology Inc. DS39932C-page 287 PIC18F46J11 FAMILY REGISTER 18-7: R/W-0 GCEN(3) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SSPxCON2: MSSPx CONTROL REGISTER 2 -I2CTM MASTER MODE (ACCESS FC5h/F71h) R/W-0 ACKDT(1) R/W-0 ACKEN(2) R/W-0 RCEN(2) R/W-0 PEN(2) R/W-0 RSEN(2) R/W-0 SEN(2) bit 0 R/W-0 ACKSTAT GCEN: General Call Enable bit (Slave mode only)(3) 1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; automatically cleared by hardware 0 = Acknowledge sequence Idle RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle PEN: Stop Condition Enable bit(2) 1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Stop condition Idle RSEN: Repeated Start Condition Enable bit(2) 1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Repeated Start condition Idle SEN: Start Condition Enable bit(2) 1 = Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Start condition Idle Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). This bit is not implemented in I2C Master mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: DS39932C-page 288 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 18-8: R/W-0 GCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SSPxCON2: MSSPx CONTROL REGISTER 2 - I2CTM SLAVE MODE (ACCESS FC5h/F71h) R/W-0 ADMSK5 R/W-0 ADMSK4 R/W-0 ADMSK3 R/W-0 ADMSK2 R/W-0 ADMSK1 R/W-0 SEN(1) bit 0 R/W-0 ACKSTAT(2) GCEN: General Call Enable bit (Slave mode only) 1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit(2) Unused in Slave mode. ADMSK<5:2>: Slave Address Mask Select bits (5-Bit Address Masking) 1 = Masking of corresponding bits of SSPxADD enabled 0 = Masking of corresponding bits of SSPxADD disabled ADMSK1: Slave Address Least Significant bit(s) Mask Select bit In 7-Bit Addressing mode: 1 = Masking of SSPxADD<1> only enabled 0 = Masking of SSPxADD<1> only disabled In 10-Bit Addressing mode: 1 = Masking of SSPxADD<1:0> enabled 0 = Masking of SSPxADD<1:0> disabled SEN: Start Condition Enable/Stretch Enable bit(1) 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). This bit is unimplemented in I2C Slave mode. bit 6 bit 5-2 bit 1 bit 0 Note 1: 2: REGISTER 18-9: R/W-1 MSK7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 SSPxMSK: I2CTM SLAVE ADDRESS MASK REGISTER - 7-BIT MASKING MODE (ACCESS FC8h/F74h)(1) R/W-1 MSK5 R/W-1 MSK4 R/W-1 MSK3 R/W-1 MSK2 R/W-1 MSK1 R/W-1 MSK0(2) bit 0 R/W-1 MSK6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown MSK<7:0>: Slave Address Mask Select bits 1 = Masking of corresponding bit of SSPxADD enabled 0 = Masking of corresponding bit of SSPxADD disabled This register shares the same SFR address as SSPxADD and is only addressable in select MSSP operating modes. See Section 18.5.3.4 "7-Bit Address Masking Mode" for more details. MSK0 is not used as a mask bit in 7-bit addressing. Note 1: 2: (c) 2009 Microchip Technology Inc. DS39932C-page 289 PIC18F46J11 FAMILY 18.5.2 OPERATION The MSSP module functions are enabled by setting the MSSP Enable bit, SSPEN (SSPxCON1<5>). The SSPxCON1 register allows control of the I2C operation. Four mode selection bits (SSPxCON1<3:0>) allow one of the following I2C modes to be selected: * * * * I C Master mode, clock I2C Slave mode (7-bit address) I2C Slave mode (10-bit address) I2C Slave mode (7-bit address) with Start and Stop bit interrupts enabled * I2C Slave mode (10-bit address) with Start and Stop bit interrupts enabled * I2C Firmware Controlled Master mode, slave is Idle 2 The SCLx clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. 18.5.3.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPxSR register. All incoming bits are sampled with the rising edge of the clock (SCLx) line. The value of register, SSPxSR<7:1>, is compared to the value of the SSPxADD register. The address is compared on the falling edge of the eighth clock (SCLx) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur: 1. 2. 3. 4. The SSPxSR register value is loaded into the SSPxBUF register. The Buffer Full bit, BF, is set. An ACK pulse is generated. The MSSPx Interrupt Flag bit, SSPxIF, is set (and interrupt is generated, if enabled) on the falling edge of the ninth SCLx pulse. Selection of any I2C mode with the SSPEN bit set forces the SCLx and SDAx pins to be open-drain, provided these pins are programmed as inputs by setting the appropriate TRISB or TRISD bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCLx and SDAx pins. 18.5.3 SLAVE MODE In Slave mode, the SCLx and SDAx pins must be configured as inputs (TRISB<5:4> set). The MSSP module will override the input state with the output data when required (slave-transmitter). The I2C Slave mode hardware will always generate an interrupt on an address match. Address masking will allow the hardware to generate an interrupt for more than one address (up to 31 in 7-bit addressing and up to 63 in 10-bit addressing). Through the mode select bits, the user can also choose to interrupt on Start and Stop bits. When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPxBUF register with the received value currently in the SSPxSR register. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: * The Buffer Full bit, BF (SSPxSTAT<0>), was set before the transfer was received. * The overflow bit, SSPOV (SSPxCON1<6>), was set before the transfer was received. In this case, the SSPxSR register value is not loaded into the SSPxBUF, but bit, SSPxIF, is set. The BF bit is cleared by reading the SSPxBUF register, while bit, SSPOV, is cleared through software. In 10-Bit Addressing mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPxSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `11110 A9 A8 0', where `A9' and `A8' are the two MSbs of the address. The sequence of events for 10-bit addressing is as follows, with steps 7 through 9 for the slave-transmitter: 1. 2. Receive first (high) byte of address (bits, SSPxIF, BF and UA, are set on address match). Update the SSPxADD register with second (low) byte of address (clears bit, UA, and releases the SCLx line). Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF. Receive second (low) byte of address (bits, SSPxIF, BF and UA, are set). Update the SSPxADD register with the first (high) byte of address. If match releases SCLx line, this will clear bit, UA. Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF. Receive Repeated Start condition. Receive first (high) byte of address (bits, SSPxIF and BF, are set). Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF. 3. 4. 5. 6. 7. 8. 9. DS39932C-page 290 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.5.3.2 Address Masking Modes Masking an address bit causes that bit to become a "don't care". When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which greatly expands the number of addresses Acknowledged. The I2C slave behaves the same way, whether address masking is used or not. However, when address masking is used, the I2C slave can Acknowledge multiple addresses and cause interrupts. When this occurs, it is necessary to determine which address caused the interrupt by checking SSPxBUF. The PIC18F46J11 family of devices is capable of using two different Address Masking modes in I2C slave operation: 5-Bit Address Masking and 7-Bit Address Masking. The Masking mode is selected at device configuration using the MSSPMSK Configuration bit. The default device configuration is 7-Bit Address Masking. Both Masking modes, in turn, support address masking of 7-bit and 10-bit addresses. The combination of Masking modes and addresses provide different ranges of Acknowledgable addresses for each combination. While both Masking modes function in roughly the same manner, the way they use address masks is different. the incoming address. This allows the module to Acknowledge up to 31 addresses when using 7-bit addressing, or 63 addresses with 10-bit addressing (see Example 18-3). This Masking mode is selected when the MSSPMSK Configuration bit is programmed (`0'). The address mask in this mode is stored in the SSPxCON2 register, which stops functioning as a control register in I2C Slave mode (Register 18-8). In 7-Bit Address Masking mode, address mask bits, ADMSK<5:1> (SSPxCON2<5:1>), mask the corresponding address bits in the SSPxADD register. For any ADMSK bits that are set (ADMSK 18.5.3.3 5-Bit Address Masking Mode As the name implies, 5-Bit Address Masking mode uses an address mask of up to five bits to create a range of addresses to be Acknowledged, using bits 5 through 1 of EXAMPLE 18-3: 7-Bit Addressing: ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be `0') ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh 10-Bit Addressing: SSPxADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since they are not affected by masking) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh (c) 2009 Microchip Technology Inc. DS39932C-page 291 PIC18F46J11 FAMILY 18.5.3.4 7-Bit Address Masking Mode Unlike 5-Bit Address Masking mode, 7-Bit Address Masking mode uses a mask of up to eight bits (in 10-bit addressing) to define a range of addresses than can be Acknowledged, using the lowest bits of the incoming address. This allows the module to Acknowledge up to 127 different addresses with 7-bit addressing, or 255 with 10-bit addressing (see Example 18-4). This mode is the default configuration of the module, and is selected when MSSPMSK is unprogrammed (`1'). The address mask for 7-Bit Address Masking mode is stored in the SSPxMSK register, instead of the SSPxCON2 register. SSPxMSK is a separate hardware register within the module, but it is not directly addressable. Instead, it shares an address in the SFR space with the SSPxADD register. To access the SSPxMSK register, it is necessary to select MSSP mode, `1001' (SSPCON1<3:0> = 1001), and then read or write to the location of SSPxADD. To use 7-Bit Address Masking mode, it is necessary to initialize SSPxMSK with a value before selecting the I2C Slave Addressing mode. Thus, the required sequence of events is: 1. 2. Select SSPxMSK Access mode (SSPxCON2<3:0> = 1001). Write the mask value to the appropriate SSPxADD register address (FC8h for MSSP1, F6Eh for MSSP2). Set the appropriate I2C Slave mode (SSPxCON2<3:0> = 0111 for 10-bit addressing, 0110 for 7-bit addressing). Setting or clearing mask bits in SSPxMSK behaves in the opposite manner of the ADMSK bits in 5-Bit Address Masking mode. That is, clearing a bit in SSPxMSK causes the corresponding address bit to be masked; setting the bit requires a match in that position. SSPxMSK resets to all `1's upon any Reset condition and, therefore, has no effect on the standard MSSP operation until written with a mask value. With 7-Bit Address Masking mode, SSPxMSK<7:1> bits mask the corresponding address bits in the SSPxADD register. For any SSPxMSK bits that are active (SSPxMSK 3. EXAMPLE 18-4: 7-Bit Addressing: ADDRESS MASKING EXAMPLES IN 7-BIT MASKING MODE SSPxADD<7:1>= 1010 000 SSPxMSK<7:1>= 1111 001 Addresses Acknowledged = A8h, A6h, A4h, A0h 10-Bit Addressing: SSPxADD<7:0> = 1010 0000 (The two MSbs are ignored in this example since they are not affected) SSPxMSK<5:1> = 1111 0 Addresses Acknowledged = A8h, A6h, A4h, A0h DS39932C-page 292 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.5.3.5 Reception 18.5.3.6 Transmission When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and the SDAx line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPxSTAT<0>), is set or bit, SSPOV (SSPxCON1<6>), is set. An MSSP interrupt is generated for each data transfer byte. The interrupt flag bit, SSPxIF, must be cleared in software. The SSPxSTAT register is used to determine the status of the byte. If SEN is enabled (SSPxCON2<0> = 1), SCLx will be held low (clock stretch) following each data transfer. The clock must be released by setting bit, CKP (SSPxCON1<4>). See Section 18.5.4 "Clock Stretching" for more details. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register. The ACK pulse will be sent on the ninth bit and pin SCLx is held low regardless of SEN (see Section 18.5.4 "Clock Stretching" for more details). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPxBUF register, which also loads the SSPxSR register. Then, the SCLx pin should be enabled by setting bit, CKP (SSPxCON1<4>). The eight data bits are shifted out on the falling edge of the SCLx input. This ensures that the SDAx signal is valid during the SCLx high time (Figure 18-10). The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCLx input pulse. If the SDAx line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets the SSPxSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCLx pin must be enabled by setting bit, CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. (c) 2009 Microchip Technology Inc. DS39932C-page 293 FIGURE 18-8: DS39932C-page 294 Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 R/W = 0 Receiving Data ACK Receiving Data D1 D0 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPxBUF is read SSPOV is set because SSPxBUF is still full. ACK is not sent. SDAx A7 A6 PIC18F46J11 FAMILY SCLx S 1 2 SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP (SSPxCON1<4>) I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) (c) 2009 Microchip Technology Inc. (CKP does not reset to `0' when SEN = 0) FIGURE 18-9: (c) 2009 Microchip Technology Inc. Receiving Address A5 X A3 X X ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 R/W = 0 Receiving Data ACK Receiving Data D2 D1 D0 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPxBUF is read SSPOV is set because SSPxBUF is still full. ACK is not sent. SDAx A7 A6 SCLx S 1 2 SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP (SSPxCON1<4>) (CKP does not reset to `0' when SEN = 0) I2CTM SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) Note 1: x = Don't care (i.e., address bit can either be a `1' or a `0'). PIC18F46J11 FAMILY DS39932C-page 295 2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt. FIGURE 18-10: DS39932C-page 296 R/W = 1 ACK D1 D0 D4 D3 D2 D5 D7 D6 D1 Transmitting Data D0 A1 D3 D2 ACK D5 D4 D7 D6 Transmitting Data ACK A4 A2 A3 4 9 SCL held low while CPU responds to SSPIF 5 6 7 8 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software SSPBUF is written in software Clear by reading From SSPIF ISR Cleared in software SSPBUF is written in software From SSPIF ISR Receiving Address SDA A7 A6 A5 SCL S 1 2 3 Data in sampled PIC18F46J11 FAMILY SSPIF (PIR1<3>) BF (SSPSTAT<0>) CKP I2CTM SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) (c) 2009 Microchip Technology Inc. CKP is set in software CKP is set in software FIGURE 18-11: Clock is held low until update of SSPxADD has taken place R/W = 0 A8 D3 D2 ACK A7 A6 A5 X A3 A2 X X D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 ACK Receive Second Byte of Address Receive Data Byte Receive Data Byte D1 D0 ACK Clock is held low until update of SSPxADD has taken place Receive First Byte of Address (c) 2009 Microchip Technology Inc. 6 1 2 3 4 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 5 6 7 8 9 P Bus master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPxBUF to clear BF flag SSPOV is set because SSPxBUF is still full. ACK is not sent. Cleared by hardware when SSPxADD is updated with low byte of address UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with high byte of address SDAx 1 1 1 1 0 A9 SCLx S 1 2 3 4 5 SSPxIF (PIR1<3> or PIR3<7>) Cleared in software BF (SSPxSTAT<0>) SSPxBUF is written with contents of SSPxSR SSPOV (SSPxCON1<6>) UA (SSPxSTAT<1>) UA is set indicating that the SSPxADD needs to be updated CKP (SSPxCON1<4>) (CKP does not reset to `0' when SEN = 0) I2CTM SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESS) Note 1: x = Don't care (i.e., address bit can either be a `1' or a `0'). 2: In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt. PIC18F46J11 FAMILY DS39932C-page 297 3: Note that the Most Significant bits of the address are not affected by the bit masking. FIGURE 18-12: DS39932C-page 298 Clock is held low until update of SSPxADD has taken place R/W = 0 A8 D3 D2 ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 A0 ACK D1 D0 Receive Second Byte of Address Receive Data Byte Receive Data Byte ACK Clock is held low until update of SSPxADD has taken place 0 A9 5 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 6 7 8 9 P Bus master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPxBUF to clear BF flag SSPOV is set because SSPxBUF is still full. ACK is not sent. Cleared by hardware when SSPxADD is updated with low byte of address UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with high byte of address Receive First Byte of Address SDAx 1 1 1 1 SCLx S 1 2 3 4 SSPxIF (PIR1<3> or PIR3<7>) Cleared in software PIC18F46J11 FAMILY BF (SSPxSTAT<0>) SSPxBUF is written with contents of SSPxSR SSPOV (SSPxCON1<6>) UA (SSPxSTAT<1>) UA is set indicating that the SSPxADD needs to be updated CKP (SSPxCON1<4>) I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) (c) 2009 Microchip Technology Inc. (CKP does not reset to `0' when SEN = 0) FIGURE 18-13: Bus master terminates transfer Clock is held low until CKP is set to `1' R/W = 1 ACK Transmitting Data Byte D7 D6 D5 D4 D3 D2 D1 D0 ACK (c) 2009 Microchip Technology Inc. Clock is held low until update of SSPxADD has taken place R/W = 0 Receive Second Byte of Address Receive First Byte of Address ACK 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 Clock is held low until update of SSPxADD has taken place 1 0 A9 A8 4 Sr 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Dummy read of SSPxBUF to clear BF flag Dummy read of SSPxBUF to clear BF flag Write of SSPxBUF BF flag is clear initiates transmit at the end of the third address sequence Completion of data transmission clears BF flag Cleared by hardware when SSPxADD is updated with low byte of address UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with high byte of address. CKP is set in software CKP is automatically cleared in hardware, holding SCLx low Receive First Byte of Address SDAx 1 1 1 SCLx S 1 2 3 SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPxBUF is written with contents of SSPxSR UA (SSPxSTAT<1>) UA is set indicating that the SSPxADD needs to be updated I2CTM SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) CKP (SSPxCON1<4>) PIC18F46J11 FAMILY DS39932C-page 299 PIC18F46J11 FAMILY 18.5.4 CLOCK STRETCHING 18.5.4.3 Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPxCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data receive sequence. Clock Stretching for 7-Bit Slave Transmit Mode The 7-Bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless of the state of the SEN bit. The user's Interrupt Service Routine (ISR) must set the CKP bit before transmission is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and load the contents of the SSPxBUF before the master device can initiate another transmit sequence (see Figure 18-10). Note 1: If the user loads the contents of SSPxBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. 18.5.4.1 Clock Stretching for 7-Bit Slave Receive Mode (SEN = 1) In 7-Bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence, if the BF bit is set, the CKP bit in the SSPxCON1 register is automatically cleared, forcing the SCLx output to be held low. The CKP bit being cleared to `0' will assert the SCLx line low. The CKP bit must be set in the user's ISR before reception is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and read the contents of the SSPxBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure 18-15). Note 1: If the user reads the contents of the SSPxBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition. 18.5.4.4 Clock Stretching for 10-Bit Slave Transmit Mode In 10-Bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-Bit Slave Receive mode. The first two addresses are followed by a third address sequence, which contains the high-order bits of the 10-bit address and the R/W bit set to `1'. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 18-13). 18.5.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to `0'. The release of the clock line occurs upon updating SSPxADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPxADD register before the falling edge of the ninth clock occurs, and if the user has not cleared the BF bit by reading the SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39932C-page 300 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.5.4.5 Clock Synchronization and CKP bit When the CKP bit is cleared, the SCLx output is forced to `0'. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCLx (see Figure 18-14). FIGURE 18-14: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX DX - 1 SCLx CKP Master device asserts clock Master device deasserts clock WR SSPxCON1 (c) 2009 Microchip Technology Inc. DS39932C-page 301 FIGURE 18-15: DS39932C-page 302 Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock Clock is held low until CKP is set to `1' ACK Receiving Data D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 R/W = 0 Receiving Data Clock is not held low because ACK = 1 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPxBUF is read SSPOV is set because SSPxBUF is still full. ACK is not sent. SDAx A7 A6 PIC18F46J11 FAMILY SCLx S 1 2 SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP (SSPxCON1<4>) CKP written to `1' in software BF is set after falling edge of the 9th clock, CKP is reset to `0' and clock stretching occurs I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) (c) 2009 Microchip Technology Inc. If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to `0' and no clock stretching will occur FIGURE 18-16: Clock is held low until update of SSPxADD has taken place Clock is held low until CKP is set to `1' Receive Data Byte D1 D0 D7 D6 D5 D4 ACK D3 D2 D1 D0 R/W = 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 Receive Second Byte of Address Receive Data Byte Clock is held low until update of SSPxADD has taken place Clock is not held low because ACK = 1 ACK Receive First Byte of Address A9 A8 (c) 2009 Microchip Technology Inc. 6 1 2 3 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Bus master terminates transfer Dummy read of SSPxBUF to clear BF flag Dummy read of SSPxBUF to clear BF flag SSPOV is set because SSPxBUF is still full. ACK is not sent. Cleared by hardware when SSPxADD is updated with low byte of address after falling edge of ninth clock UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with high byte of address after falling edge of ninth clock Note: An update of the SSPxADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. Note: An update of the SSPxADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. CKP written to `1' in software SDAx 1 1 1 1 0 SCLx S 1 2 3 4 5 SSPxIF (PIR1<3> or PIR3<7>) Cleared in software BF (SSPxSTAT<0>) SSPxBUF is written with contents of SSPxSR SSPOV (SSPxCON1<6>) UA (SSPxSTAT<1>) UA is set indicating that the SSPxADD needs to be updated I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) CKP (SSPxCON1<4>) PIC18F46J11 FAMILY DS39932C-page 303 PIC18F46J11 FAMILY 18.5.5 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all `0's with R/W = 0. The general call address is recognized when the General Call Enable bit, GCEN, is enabled (SSPxCON2<7> set). Following a Start bit detect, 8 bits are shifted into the SSPxSR and the address is compared against the SSPxADD. It is also compared to the general call address and fixed in hardware. If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPxBUF. The value can be used to determine if the address was device-specific or a general call address. In 10-bit mode, the SSPxADD is required to be updated for the second half of the address to match and the UA bit is set (SSPxSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second half of the address is not necessary, the UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 18-17). FIGURE 18-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7-BIT OR 10-BIT ADDRESSING MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 D6 Receiving Data D5 D4 D3 D2 D1 D0 ACK SDAx SCLx S SSPxIF BF (SSPxSTAT<0>) General Call Address 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Cleared in software SSPxBUF is read SSPOV (SSPxCON1<6>) GCEN (SSPxCON2<7>) `1' `0' 18.5.6 MASTER MODE Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a Start condition on SDAx and SCLx. Assert a Repeated Start condition on SDAx and SCLx. Write to the SSPxBUF register initiating transmission of data/address. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Generate a Stop condition on SDAx and SCLx. Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPxCON1 and by setting the SSPEN bit. In Master mode, the SCLx and SDAx lines are manipulated by the MSSP hardware if the TRIS bits are set. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Start (S) and Stop (P) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the Stop bit is set, or the bus is Idle, with both the Start and Stop bits clear. In Firmware Controlled Master mode, user code conducts all I2C bus operations based on Start and Stop bit conditions. DS39932C-page 304 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Note: The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur. The following events will cause the MSSP Interrupt Flag bit, SSPxIF, to be set (and MSSP interrupt, if enabled): * * * * * Start condition Stop condition Data transfer byte transmitted/received Acknowledge transmitted Repeated Start FIGURE 18-18: MSSPx BLOCK DIAGRAM (I2CTM MASTER MODE) Internal Data Bus Read SSPxBUF Write Baud Rate Generator Clock Arbitrate/WCOL Detect (hold off clock source) DS39932C-page 305 Shift Clock SSPxSR Receive Enable MSb LSb SSPM<3:0> SSPxADD<6:0> SDAx SDAx In SCLx SCLx In Bus Collision Start bit Detect Stop bit Detect Write Collision Detect Clock Arbitration State Counter for End of XMIT/RCV Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1) Set SSPxIF, BCLxIF Reset ACKSTAT, PEN (SSPxCON2) 18.5.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx while SCLx outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. S and P conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address, followed by a `1' to indicate the receive bit. Serial data is received via SDAx, while SCLx outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. S and P conditions indicate the beginning and end of transmission. The BRG, used for the SPI mode operation, is used to set the SCLx clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 18.5.7 "Baud Rate" for more details. (c) 2009 Microchip Technology Inc. Clock Cntl Start bit, Stop bit, Acknowledge Generate PIC18F46J11 FAMILY A typical transmit sequence would go as follows: The user generates a Start condition by setting the Start Enable bit, SEN (SSPxCON2<0>). 2. SSPxIF is set. The MSSP module will wait for the required start time before any other operation takes place. 3. The user loads the SSPxBUF with the slave address to transmit. 4. Address is shifted out of the SDAx pin until all 8 bits are transmitted. 5. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPxCON2 register (SSPxCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. 7. The user loads the SSPxBUF with 8 bits of data. 8. Data is shifted out the SDAx pin until all 8 bits are transmitted. 9. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPxCON2 register (SSPxCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPxCON2<2>). 12. Interrupt is generated once the Stop condition is complete. 1. 18.5.7 2 BAUD RATE In I C Master mode, the BRG reload value is placed in the lower seven bits of the SSPxADD register (Figure 18-19). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCLx pin will remain in its last state. Table 18-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. DS39932C-page 306 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.5.7.1 Baud Rate and Module Interdependence Because MSSP1 and MSSP2 are independent, they can operate simultaneously in I2C Master mode at different baud rates. This is done by using different BRG reload values for each module. Because this mode derives its basic clock source from the system clock, any changes to the clock will affect both modules in the same proportion. It may be possible to change one or both baud rates back to a previous value by changing the BRG reload value. FIGURE 18-19: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPxADD<6:0> SSPM<3:0> SCLx Reload Control CLKO Reload BRG Down Counter FOSC/4 TABLE 18-3: FOSC 40 MHz 40 MHz 40 MHz 16 MHz 16 MHz 16 MHz 4 MHz 4 MHz 4 MHz Note 1: I2CTM CLOCK RATE w/BRG FCY 10 MHz 10 MHz 10 MHz 4 MHz 4 MHz 4 MHz 1 MHz 1 MHz 1 MHz I2C FCY * 2 20 MHz 20 MHz 20 MHz 8 MHz 8 MHz 8 MHz 2 MHz 2 MHz 2 MHz I2C BRG Value 18h 1Fh 63h 09h 0Ch 27h 02h 09h 00h FSCL (2 Rollovers of BRG) 400 kHz(1) 312.5 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 333 kHz(1) 100 kHz 1 MHz(1) The interface does not conform to the 400 kHz specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. (c) 2009 Microchip Technology Inc. DS39932C-page 307 PIC18F46J11 FAMILY 18.5.7.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the BRG is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the BRG is reloaded with the contents of SSPxADD<6:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 18-20). FIGURE 18-20: SDAx BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION DX SCLx deasserted but slave holds SCLx low (clock arbitration) DX - 1 SCLx allowed to transition high SCLx BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCLx is sampled high, reload takes place and BRG starts its count BRG Reload 18.5.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx pins are sampled high, the BRG is reloaded with the contents of SSPxADD<6:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low. The action of the SDAx being driven low while SCLx is high is the Start condition and causes the Start bit (SSPxSTAT<3>) to be set. Following this, the BRG is reloaded with the contents of SSPxADD<6:0> and resumes its count. When the BRG times out (TBRG), the SEN bit (SSPxCON2<0>) will be automatically cleared by hardware. The BRG is suspended, leaving the SDAx line held low and the Start condition is complete. If, at the beginning of the Start condition, the SDAx and SCLx pins are already sampled low or if during the Start condition, the SCLx line is sampled low, before the SDAx line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 18.5.8.1 WCOL Status Flag If the user writes the SSPxBUF when a Start sequence is in progress, the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). Note: Because queueing of events is not allowed, writing to the lower five bits of SSPxCON2 is disabled until the Start condition is complete. FIGURE 18-21: FIRST START BIT TIMING Write to SEN bit occurs here SDAx = 1, SCLx = 1 TBRG SDAx TBRG Set S bit (SSPxSTAT<3>) At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit Write to SSPxBUF occurs here 1st bit TBRG TBRG S 2nd bit SCLx DS39932C-page 308 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.5.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: * SDAx is sampled low when SCLx goes from low-to-high. * SCLx goes low before SDAx is asserted low. This may indicate that another master is attempting to transmit a data `1'. Immediately following the SSPxIF bit getting set, the user may write the SSPxBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional 8 bits of address (10-bit mode) or 8 bits of data (7-bit mode). A Repeated Start condition occurs when the RSEN bit (SSPxCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the BRG is loaded with the contents of SSPxADD<5:0> and begins counting. The SDAx pin is released (brought high) for one BRG count (TBRG). When the BRG times out, and if SDAx is sampled high, the SCLx pin will be deasserted (brought high). When SCLx is sampled high, the BRG is reloaded with the contents of SSPxADD<6:0> and begins counting. SDAx and SCLx must be sampled high for one TBRG. This action is then followed by assertion of the SDAx pin (SDAx = 0) for one TBRG while SCLx is high. Following this, the RSEN bit (SSPxCON2<1>) will be automatically cleared and the BRG will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the Start bit (SSPxSTAT<3>) will be set. The SSPxIF bit will not be set until the BRG has timed out. 18.5.9.1 WCOL Status Flag If the user writes the SSPxBUF when a Repeated Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Note: Because queueing of events is not allowed, writing of the lower five bits of SSPxCON2 is disabled until the Repeated Start condition is complete. FIGURE 18-22: REPEATED START CONDITION WAVEFORM S bit set by hardware SDAx = 1, SCLx = 1 TBRG TBRG 1st bit Write to SSPxCON2 occurs here: SDAx = 1, SCLx (no change). At completion of Start bit, hardware clears RSEN bit and sets SSPxIF TBRG SDAx RSEN bit set by hardware on falling edge of ninth clock, end of XMIT SCLx Write to SSPxBUF occurs here TBRG TBRG Sr = Repeated Start (c) 2009 Microchip Technology Inc. DS39932C-page 309 PIC18F46J11 FAMILY 18.5.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the BRG to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted (see data hold time specification parameter 106). SCLx is held low for one BRG rollover count (TBRG). Data should be valid before SCLx is released high (see data setup time specification parameter 107). When the SCLx pin is released high, it is held that way for TBRG. The data on the SDAx pin must remain stable for that duration and some hold time after the next falling edge of SCLx. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared; if not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (BRG) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCLx low and SDAx unchanged (Figure 18-23). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCLx until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert the SDAx pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPxCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPxIF flag is set, the BF flag is cleared and the BRG is turned off until another write to the SSPxBUF takes place, holding SCLx low and allowing SDAx to float. The user should verify that the WCOL bit is clear after each write to SSPxBUF to ensure the transfer is correct. In all cases, WCOL must be cleared in software. 18.5.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPxCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 18.5.11 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPxCON2<3>). Note: The MSSP module must be in an inactive state before the RCEN bit is set or the RCEN bit will be disregarded. The BRG begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the BRG is suspended from counting, holding SCLx low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable bit, ACKEN (SSPxCON2<4>). 18.5.11.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read. 18.5.11.2 SSPOV Status Flag In receive operation, the SSPOV bit is set when 8 bits are received into the SSPxSR and the BF flag bit is already set from a previous reception. 18.5.11.3 WCOL Status Flag 18.5.10.1 BF Status Flag In Transmit mode, the BF bit (SSPxSTAT<0>) is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted out. If users write the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). 18.5.10.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur) after 2 TCY after the SSPxBUF write. If SSPxBUF is rewritten within 2 TCY, the WCOL bit is set and SSPxBUF is updated. This may result in a corrupted transfer. DS39932C-page 310 (c) 2009 Microchip Technology Inc. FIGURE 18-23: Write SSPxCON2<0> (SEN = 1), Start condition begins From slave, clear ACKSTAT bit (SSPxCON2<6>) R/W = 0 ACKSTAT in SSPxCON2 = 1 (c) 2009 Microchip Technology Inc. SEN = 0 Transmit Address to Slave SDAx A7 SSPxBUF written with 7-bit address and R/W, start transmit SCLx S 1 2 3 4 5 6 7 8 9 1 SCLx held low while CPU responds to SSPxIF 2 3 4 5 6 7 8 9 P A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 Transmitting Data or Second Half of 10-bit Address D1 D0 ACK SSPxIF Cleared in software Cleared in software service routine from MSSP interrupt Cleared in software BF (SSPxSTAT<0>) SSPxBUF written SEN After Start condition, SEN cleared by hardware SSPxBUF is written in software PEN R/W I 2CTM MASTER MODE WAVEFORM (TRANSMISSION, 7-BIT OR 10-BIT ADDRESS) PIC18F46J11 FAMILY DS39932C-page 311 FIGURE 18-24: DS39932C-page 312 Write to SSPxCON2<4> to start Acknowledge sequence, SDAx = ACKDT (SSPxCON2<5>) = 0 Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) RCEN cleared automatically Receiving Data from Slave ACK Receiving Data from Slave RCEN = 1, start next receive RCEN cleared automatically ACK ACK from master, SDAx = ACKDT = 0 Set ACKEN, start Acknowledge sequence, SDAx = ACKDT = 1 PEN bit = 1 written here R/W = 0 Write to SSPxCON2<0> (SEN = 1), begin Start condition SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT Transmit Address to Slave SDAx D0 A7 A1 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D0 A6 A5 A4 A3 A2 ACK ACK is not sent Bus master terminates transfer SCLx Set SSPxIF interrupt at end of receive S 1 5 1 2 3 4 5 1 2 3 4 8 5 2 3 4 9 6 7 6 7 8 9 6 7 8 9 Set SSPxIF at end of receive P Set SSPxIF interrupt at end of Acknowledge sequence PIC18F46J11 FAMILY Data shifted in on falling edge of CLK SSPxIF Cleared in software Cleared in software Set SSPxIF interrupt at end of Acknowledge sequence Cleared in software Cleared in software Cleared in software SDAx = 0, SCLx = 1, while CPU responds to SSPxIF Set P bit (SSPxSTAT<4>) and SSPxIF BF (SSPxSTAT<0>) Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF SSPOV SSPOV is set because SSPxBUF is still full I2CTM MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) (c) 2009 Microchip Technology Inc. ACKEN PIC18F46J11 FAMILY 18.5.12 ACKNOWLEDGE SEQUENCE TIMING 18.5.13 STOP CONDITION TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN (SSPxCON2<4>). When this bit is set, the SCLx pin is pulled low and the contents of the Acknowledge data bit are presented on the SDAx pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The BRG then counts for one rollover period (TBRG) and the SCLx pin is deasserted (pulled high). When the SCLx pin is sampled high (clock arbitration), the BRG counts for TBRG; the SCLx pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the BRG is turned off and the MSSP module then goes into an inactive state (Figure 18-25). A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the BRG is reloaded and counts down to 0. When the BRG times out, the SCLx pin will be brought high and one Baud Rate Generator rollover count (TBRG) later, the SDAx pin will be deasserted. When the SDAx pin is sampled high while SCLx is high, the Stop bit (SSPxSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 18-26). 18.5.13.1 WCOL Status Flag 18.5.12.1 WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does not occur). If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 18-25: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPxCON2, ACKEN = 1, ACKDT = 0 TBRG SDAx D0 ACK TBRG ACKEN automatically cleared SCLx 8 9 SSPxIF Cleared in software SSPxIF set at the end of Acknowledge sequence SSPxIF set at the end of receive Note: TBRG = one Baud Rate Generator period. Cleared in software FIGURE 18-26: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPxCON2, set PEN Falling edge of 9th clock SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. (c) 2009 Microchip Technology Inc. DS39932C-page 313 PIC18F46J11 FAMILY 18.5.14 SLEEP OPERATION 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 18.5.15 EFFECTS OF A RESET puts a `1' on SDAx, by letting SDAx float high and another master asserts a `0'. When the SCLx pin floats high, data should be stable. If the expected data on SDAx is a `1' and the data sampled on the SDAx pin = 0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF, and reset the I2C port to its Idle state (Figure 18-27). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDAx and SCLx lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDAx and SCLx lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine (ISR), and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDAx and SCLx pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the Stop bit is set in the SSPxSTAT register, or the bus is Idle and the Start and Stop bits are cleared. A Reset disables the MSSP module and terminates the current transfer. 18.5.16 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Start and Stop bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit (SSPxSTAT<4>) is set, or the bus is Idle, with both the Start and Stop bits clear. When the bus is busy, enabling the MSSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDAx line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed in hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition 18.5.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master out- FIGURE 18-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master Sample SDAx. While SCLx is high, data doesn't match what is driven by the master; bus collision has occurred SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF DS39932C-page 314 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.5.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx is sampled low at the beginning of the Start condition (Figure 18-28). SCLx is sampled low before SDAx is asserted low (Figure 18-29). If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 18-30). If, however, a `1' is sampled on the SDAx pin, the SDAx pin is asserted low at the end of the BRG count. The BRG is then reloaded and counts down to 0. If the SCLx pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCLx pin is asserted low. Note: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDAx before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is already low, or the SCLx pin is already low, then all of the following occur: * The Start condition is aborted * The BCLxIF flag is set * The MSSP module is reset to its inactive state (Figure 18-28) The Start condition begins with the SDAx and SCLx pins deasserted. When the SDAx pin is sampled high, the BRG is loaded from SSPxADD<6:0> and counts down to 0. If the SCLx pin is sampled low while SDAx is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. FIGURE 18-28: BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start condition if SDAx = 1, SCLx = 1 SEN SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared in software S SEN cleared automatically because of bus collision. MSSPx module reset into Idle state. BCLxIF SSPxIF SSPxIF and BCLxIF are cleared in software (c) 2009 Microchip Technology Inc. DS39932C-page 315 PIC18F46J11 FAMILY FIGURE 18-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared in software S SSPxIF `0' `0' `0' `0' SCLx SEN FIGURE 18-30: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Less than TBRG Set SSPxIF TBRG SDAx SDAx pulled low by other master. Reset BRG and assert SDAx. SCLx S SCLx pulled low after BRG time-out Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SEN BCLxIF `0' S SSPxIF SDAx = 0, SCLx = 1, set SSPxIF Interrupts cleared in software DS39932C-page 316 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 18.5.17.2 Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDAx when SCLx goes from a low level to a high level. SCLx goes low before SDAx is asserted low, indicating that another master is attempting to transmit a data `1'. If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', see Figure 18-31). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time. If SCLx goes from high-to-low before the BRG times out and SDAx has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition (see Figure 18-32). If, at the end of the BRG time-out, both SCLx and SDAx are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. When the user deasserts SDAx and the pin is allowed to float high, the BRG is loaded with SSPxADD<6:0> and counts down to 0. The SCLx pin is then deasserted and when sampled high, the SDAx pin is sampled. FIGURE 18-31: SDAx BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared in software S SSPxIF `0' `0' FIGURE 18-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx SCLx goes low before SDAx, set BCLxIF. Release SDAx and SCLx. Interrupt cleared in software RSEN S SSPxIF `0' BCLxIF (c) 2009 Microchip Technology Inc. DS39932C-page 317 PIC18F46J11 FAMILY 18.5.17.3 Bus Collision During a Stop Condition Bus collision occurs during a Stop condition if: a) After the SDAx pin has been deasserted and allowed to float high, SDAx is sampled low after the BRG has timed out. After the SCLx pin is deasserted, SCLx is sampled low before SDAx goes high. The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the BRG is loaded with SSPxADD<6:0> and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 18-33). If the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 18-34). b) FIGURE 18-33: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDAx sampled low after TBRG, set BCLxIF SDAx SDAx asserted low SCLx PEN BCLxIF P SSPxIF `0' `0' FIGURE 18-34: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx Assert SDAx SCLx PEN BCLxIF P SSPxIF `0' `0' SCLx goes low before SDAx goes high, set BCLxIF DS39932C-page 318 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 18-4: Name INTCON PIR1 PIE1 IPR1 REGISTERS ASSOCIATED WITH I2CTM OPERATION Bit 7 Bit 6 Bit 5 TMR0IE RC1IF RC1IE RC1IP CM1IF CM1IE CM1IP Bit 4 INT0IE TX1IF TX1IE TX1IP -- -- -- Bit 3 RBIE SSP1IF SSP1IE SSP1IP BCL1IF BCL1IE BCL1IP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP LVDIF LVDIE LVDIP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3IF TMR3IE TMR3IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP Reset Values on Page: 63 65 65 65 65 65 65 65 65 65 66 66 64 64, 67 64, 67 64, 67 64, 67 64, 67 67 67 MSK3 SSPM3 RCEN ADMSK3 S (2) (2) GIE/GIEH PEIE/GIEL PMPIF(3) PMPIE(3) PMPIP (3) ADIF ADIE ADIP CM2IF CM2IE CM2IP BCL2IF BCL2IE BCL2IP TRISC6 TRISB6 PIR2 PIE2 IPR2 PIR3 PIE3 IPR3 TRISC TRISB SSP1BUF SSPxADD SSPxMSK(1) SSPxCON1 SSPxCON2 SSPxSTAT SSP2BUF SSP2ADD Legend: Note 1: 2: 3: OSCFIF OSCFIE OSCFIP SSP2IF SSP2IE SSP2IP TRISC7 TRISB7 RC2IF RC2IE RC2IP TRISC5 TRISB5 TX2IF TX2IE TX2IP TRISC4 TRISB4 TMR4IF TMR4IE TMR4IP TRISC3 TRISB3 CTMUIF CTMUIE CTMUIP TRISC2 TRISB2 TMR3GIF TMR3GIE TMR3GIP TRISC1 TRISB1 RTCIF RTCIE RTCIP TRISC0 TRISB0 MSSP1 Receive Buffer/Transmit Register MSSP1 Address Register (I2CTM Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) MSK7 WCOL GCEN GCEN SMP MSK6 SSPOV ACKSTAT CKE MSK5 SSPEN ACKDT (2) MSK4 CKP ACKEN ADMSK4 P MSK2 SSPM2 PEN ADMSK2 R/W (2) MSK1 SSPM1 RSEN ADMSK1 UA (2) MSK0 SSPM0 SEN SEN BF ACKSTAT ADMSK5 D/A MSSP2 Receive Buffer/Transmit Register MSSP2 Address Register (I2C Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) -- = unimplemented, read as `0'. Shaded cells are not used by the MSSPx module in I2CTM mode. SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I2C Slave mode operations in 7-Bit Masking mode. See Section 18.5.3.4 "7-Bit Address Masking Mode" for more details. Alternate bit definitions for use in I2C Slave mode operations only. These bits are only available on 44-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 319 PIC18F46J11 FAMILY NOTES: DS39932C-page 320 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 19.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The pins of EUSART1 and EUSART2 are multiplexed with the functions of PORTC (RC6/PMA5/TX1/CK1/RP17 and RC7/PMA4/RX1/DT1/SDO1/RP18) and remapped (RPn1/TX2/CK2 and RPn2/RX2/DT2), respectively. In order to configure these pins as an EUSART: * For EUSART1: - SPEN bit (RCSTA1<7>) must be set (= 1) - TRISC<7> bit must be set (= 1) - TRISC<6> bit must be cleared (= 0) for Asynchronous and Synchronous Master modes - TRISC<6> bit must be set (= 1) for Synchronous Slave mode * For EUSART2: - SPEN bit (RCSTA2<7>) must be set (= 1) - TRIS bit for RPn2/RX2/DT2 = 1 - TRIS bit for RPn1/TX2/CK2 = 0 for Asynchronous and Synchronous Master modes - TRISC<6> bit must be set (= 1) for Synchronous Slave mode Note: The EUSART control will automatically reconfigure the pin from input to output as needed. The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of two serial I/O modules. (Generically, the EUSART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs and so on. The Enhanced USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network bus (LIN bus) systems. All members of the PIC18F46J11 family are equipped with two independent EUSART modules, referred to as EUSART1 and EUSART2. They can be configured in the following modes: * Asynchronous (full-duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit Break character transmission * Synchronous - Master (half-duplex) with selectable clock polarity * Synchronous - Slave (half-duplex) with selectable clock polarity The TXx/CKx I/O pins have an optional open-drain output capability. By default, when this pin is used by the EUSART as an output, it will function as a standard push-pull CMOS output. The TXx/CKx I/O pins' open-drain, output feature can be enabled by setting the corresponding UxOD bit in the ODCON2 register. For more details, see Section 18.3.3 "Open-Drain Output Option". The operation of each Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTAx) * Receive Status and Control (RCSTAx) * Baud Rate Control (BAUDCONx) These are covered in detail in Register 19-1, Register 19-2 and Register 19-3, respectively. Note: Throughout this section, references to register and bit names that may be associated with a specific EUSART module are referred to generically by the use of `x' in place of the specific module number. Thus, "RCSTAx" might refer to the Receive Status register for either EUSART1 or EUSART2. (c) 2009 Microchip Technology Inc. DS39932C-page 321 PIC18F46J11 FAMILY REGISTER 19-1: R/W-0 CSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER (ACCESS FADh/FA8h) R/W-0 TXEN(1) R/W-0 SYNC R/W-0 SENDB R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0 TX9 R/W-0 CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care. BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39932C-page 322 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 19-2: R/W-0 SPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RCSTAx: RECEIVE STATUS AND CONTROL REGISTER (ACCESS FACh/F9Ch) R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 RX9 R/W-0 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-Bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-Bit (RX9 = 0): Don't care. FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREGx register and receiving next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2009 Microchip Technology Inc. DS39932C-page 323 PIC18F46J11 FAMILY REGISTER 19-3: R/W-0 ABDOVF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown BAUDCONx: BAUD RATE CONTROL REGISTER (ACCESS F7Eh/F7Ch) R-1 R/W-0 RXDTP R/W-0 TXCKP R/W-0 BRG16 U-0 -- R/W-0 WUE R/W-0 ABDEN bit 0 RCIDL ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active RXDTP: Data/Receive Polarity Select bit Asynchronous mode: 1 = Receive data (RXx) is inverted (active-low) 0 = Receive data (RXx) is not inverted (active-high) Synchronous mode: 1 = Data (DTx) is inverted (active-low) 0 = Data (DTx) is not inverted (active-high) TXCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TXx) is a low level 0 = Idle state for transmit (TXx) is a high level Synchronous mode: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator - SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator - SPBRGx only (Compatible mode), SPBRGHx value ignored Unimplemented: Read as `0' WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RXx pin - interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character; requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39932C-page 324 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 19.1 Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits, BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>), also control the baud rate. In Synchronous mode, BRGH is ignored. Table 19-1 provides the formula for computation of the baud rate for different EUSART modes, which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGHx:SPBRGx registers can be calculated using the formulas in Table 19-1. From this, the error in baud rate can be determined. An example calculation is provided in Example 19-1. Typical baud rates and error values for the various Asynchronous modes are provided in Table 19-2. It may be advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGHx:SPBRGx registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. 19.1.1 OPERATION IN POWER-MANAGED MODES The device clock is used to generate the desired baud rate. When one of the power-managed modes is entered, the new clock source may be operating at a different frequency. This may require an adjustment to the value in the SPBRGx register pair. 19.1.2 SAMPLING The data on the RXx pin (either RC7/PMA4/RX1/DT1/SDO1/RP18 or RPn2/RX2/DT2) is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RXx pin. TABLE 19-1: SYNC 0 0 0 0 1 1 BAUD RATE FORMULAS BRG16 0 0 1 1 0 1 BRGH 0 1 0 1 x x BRG/EUSART Mode 8-bit/Asynchronous 8-bit/Asynchronous 16-bit/Asynchronous 16-bit/Asynchronous 8-bit/Synchronous 16-bit/Synchronous FOSC/[4 (n + 1)] Baud Rate Formula FOSC/[64 (n + 1)] FOSC/[16 (n + 1)] Configuration Bits Legend: x = Don't care, n = value of SPBRGHx:SPBRGx register pair (c) 2009 Microchip Technology Inc. DS39932C-page 325 PIC18F46J11 FAMILY EXAMPLE 19-1: CALCULATING BAUD RATE ERROR For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG: Desired Baud Rate = Fosc/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((Fosc/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25 Calculated Baud Rate=16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate)/Desired Baud Rate = (9615 - 9600)/9600 = 0.16% TABLE 19-2: Name TXSTAx RCSTAx SPBRGHx SPBRGx REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 CSRC SPEN Bit 6 TX9 RX9 RCIDL Bit 5 TXEN SREN RXDTP Bit 4 SYNC CREN TXCKP Bit 3 SENDB ADDEN BRG16 Bit 2 BRGH FERR -- Bit 1 TRMT OERR WUE Bit 0 TX9D RX9D ABDEN Reset Values on Page: 65 65 66 66 65 BAUDCONx ABDOVF EUSARTx Baud Rate Generator Register High Byte EUSARTx Baud Rate Generator Register Low Byte Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the BRG. DS39932C-page 326 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 19-3: BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 20.000 MHz Actual Rate (K) -- 1.221 2.404 9.766 19.531 62.500 104.167 % Error -- 1.73 0.16 1.73 1.73 8.51 -9.58 SPBRG value (decimal) FOSC = 40.000 MHz Actual Rate (K) -- -- 2.441 9.615 19.531 56.818 125.000 % Error -- -- 1.73 0.16 1.73 -1.36 8.51 SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) -- 1.202 2.404 9.766 19.531 52.083 78.125 % Error -- 0.16 0.16 1.73 1.73 -9.58 -32.18 SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate (K) -- 1.201 2.403 9.615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 -- -- 255 64 31 10 4 -- 255 129 31 15 4 2 -- 129 64 15 7 2 1 -- 103 51 12 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 8.929 20.833 62.500 62.500 % Error 0.16 0.16 0.16 -6.99 8.51 8.51 -45.75 SPBRG value (decimal) FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 -- -- -- -- -- % Error -0.16 -0.16 -- -- -- -- -- SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 207 51 25 6 2 0 0 103 25 12 -- -- -- -- 51 12 -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) -- -- -- 9.766 19.231 58.140 113.636 % Error -- -- -- 1.73 0.16 0.94 -1.36 SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate (K) -- -- -- 9.615 19.231 56.818 113.636 % Error -- -- -- 0.16 0.16 -1.36 -1.36 SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) -- -- 2.441 9.615 19.531 56.818 125.000 % Error -- -- 1.73 0.16 1.73 -1.36 8.51 SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate (K) -- -- 2.403 9615. 19.230 55.555 -- % Error -- -- -0.16 -0.16 -0.16 3.55 -- SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 -- -- -- 255 129 42 21 -- -- -- 129 64 21 10 -- -- 255 64 31 10 4 -- -- 207 51 25 8 -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) -- 1.202 2.404 9.615 19.231 62.500 125.000 % Error -- 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value (decimal) FOSC = 2.000 MHz Actual Rate (K) -- 1.201 2.403 9.615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 -- 207 103 25 12 3 1 -- 103 51 12 -- -- -- 207 51 25 -- -- -- -- (c) 2009 Microchip Technology Inc. DS39932C-page 327 PIC18F46J11 FAMILY TABLE 19-3: BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.399 9.615 19.231 56.818 113.636 % Error 0.02 -0.03 -0.03 0.16 0.16 -1.36 -1.36 SPBRG value (decimal) FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.531 56.818 125.000 % Error 0.02 -0.03 0.16 0.16 1.73 -1.36 8.51 SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 55.555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 8332 2082 1040 259 129 42 21 4165 1041 520 129 64 21 10 2082 520 259 64 31 10 4 1665 415 207 51 25 8 -- SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 9.615 19.231 62.500 125.000 % Error 0.04 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value (decimal) FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 -- -- -- % Error -0.16 -0.16 -0.16 -0.16 -- -- -- SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 832 207 103 25 12 3 1 415 103 51 12 -- -- -- 207 51 25 -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.606 19.193 57.803 114.943 % Error 0.00 0.00 0.02 0.06 -0.03 0.35 -0.22 SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.596 19.231 57.471 116.279 % Error 0.00 0.02 0.02 -0.03 0.16 -0.22 0.94 SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.615 19.230 57.142 117.647 % Error -0.01 -0.04 -0.04 -0.16 -0.16 0.79 -2.12 SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 33332 8332 4165 1040 520 172 86 16665 4165 2082 520 259 86 42 8332 2082 1040 259 129 42 21 6665 1665 832 207 103 34 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.231 58.824 111.111 % Error 0.01 0.04 0.16 0.16 0.16 2.12 -3.55 SPBRG value (decimal) FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 55.555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 -- -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 -- -- SPBRG value (decimal) 0.3 1.2 2.4 9.6 19.2 57.6 115.2 3332 832 415 103 51 16 8 1665 415 207 51 25 8 -- 832 207 103 25 12 -- -- DS39932C-page 328 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 19.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 19-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RXx signal, the RXx signal is timing the BRG. In ABD mode, the internal BRG is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The ABD must receive a byte with the value, 55h (ASCII "U", which is also the LIN bus Sync character), in order to calculate the proper bit rate. The measurement is taken over both a low and high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRGx begins counting up, using the preselected clock source on the first rising edge of RXx. After eight bits on the RXx pin or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGHx:SPBRGx register pair. Once the 5th edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. If a rollover of the BRG occurs (an overflow from FFFFh to 0000h), the event is trapped by the ABDOVF status bit (BAUDCONx<7>). It is set in hardware by BRG rollovers and can be set or cleared by the user in software. ABD mode remains active after rollover events and the ABDEN bit remains set (Figure 19-2). While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRGx and SPBRGHx will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table 19-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCxIF interrupt is set once the fifth rising edge on RXx is detected. The value in the RCREGx needs to be read to clear the RCxIF interrupt. The contents of RCREGx should be discarded. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. TABLE 19-4: BRG16 0 0 1 1 Note: BRGH 0 1 0 1 BRG COUNTER CLOCK RATES BRG Counter Clock FOSC/512 FOSC/128 FOSC/128 FOSC/32 During the ABD sequence, SPBRGx and SPBRGHx are both used as a 16-bit counter, independent of BRG16 setting. 19.1.3.1 ABD and EUSART Transmission Since the BRG clock is reversed during ABD acquisition, the EUSART transmitter cannot be used during ABD. This means that whenever the ABDEN bit is set, TXREGx cannot be written to. Users should also ensure that ABDEN does not become set during a transmit sequence. Failing to do this may result in unpredictable EUSART operation. (c) 2009 Microchip Technology Inc. DS39932C-page 329 PIC18F46J11 FAMILY FIGURE 19-1: BRG Value RXx pin AUTOMATIC BAUD RATE CALCULATION XXXXh 0000h Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 001Ch Edge #5 Stop Bit BRG Clock Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx SPBRGHx XXXXh XXXXh 1Ch 00h Auto-Cleared Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. FIGURE 19-2: BRG Clock ABDEN bit RXx pin ABDOVF bit BRG OVERFLOW SEQUENCE Start Bit 0 FFFFh BRG Value XXXXh 0000h 0000h DS39932C-page 330 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 19.2 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTAx<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit BRG can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent but use the same data format and baud rate. The BRG produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH and BRG16 bits (TXSTAx<2> and BAUDCONx<3>). Parity is not supported by the hardware but can be implemented in software and stored as the ninth data bit. When operating in Asynchronous mode, the EUSART module consists of the following important elements: * * * * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-Bit Break Character Transmit Auto-Baud Rate Detection Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is empty and the TXxIF flag bit is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF will be set regardless of the state of TXxIE; it cannot be cleared in software. TXxIF is also not cleared immediately upon loading TXREGx, but becomes valid in the second instruction cycle following the load instruction. Polling TXxIF immediately following a load of TXREGx will return invalid results. While TXxIF indicates the status of the TXREGx register; another bit, TRMT (TXSTAx<1>), shows the status of the TSR register. TRMT is a read-only bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit, TXxIF, is set when enable bit, TXEN, is set. To set up an Asynchronous Transmission: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. If interrupts are desired, set enable bit, TXxIE. If 9-bit transmission is desired, set transmit bit, TX9. Can be used as address/data bit. Enable the transmission by setting bit, TXEN, which will also set bit, TXxIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Load data to the TXREGx register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 19.2.1 EUSART ASYNCHRONOUS TRANSMITTER 2. 3. 4. 5. 6. 7. 8. Figure 19-3 displays the EUSART transmitter block diagram. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREGx. The TXREGx register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREGx register (if available). FIGURE 19-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXxIE MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPEN *** TSR Register TXREGx Register 8 LSb 0 Pin Buffer and Control TXx pin BRG16 SPBRGHx SPBRGx Baud Rate Generator TX9 TX9D (c) 2009 Microchip Technology Inc. DS39932C-page 331 PIC18F46J11 FAMILY FIGURE 19-4: Write to TXREGx BRG Output (Shift Clock) TXx (pin) TXxIF bit (Transmit Buffer Reg. Empty Flag) ASYNCHRONOUS TRANSMISSION Word 1 Start bit 1 TCY bit 0 bit 1 Word 1 bit 7/8 Stop bit TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg FIGURE 19-5: Write to TXREGx ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) TXxIF bit (Interrupt Reg. Flag) 1 TCY 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Start bit bit 0 bit 1 Word 1 bit 7/8 Stop bit Start bit Word 2 bit 0 TRMT bit (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 19-5: Name INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTAx TXREGx TXSTAx BAUDCONx SPBRGHx SPBRGx ODCON2 REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 TMR0IE RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP Bit 4 INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXDTP Bit 3 RBIE SSP1IF SSP1IE SSP1IP TMR4IF TMR4IE TMR4IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP CTMUIF Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3GIF Bit 0 RBIF TMR1IF TMR1IE TMR1IP RTCCIF RTCCIE RTCCIP RX9D TX9D ABDEN Reset Values on Page: 63 65 65 65 65 65 65 65 65 BRGH -- TRMT WUE 65 66 66 65 U2OD U1OD 68 GIE/GIEH PEIE/GIEL PMPIF(1) PMPIE(1) PMPIP(1) SSP2IF SSP2IE SSP2IP SPEN CSRC ABDOVF ADIF ADIE ADIP BCL2IF BCL2IE BCL2IP RX9 TX9 RCIDL CTMUIE TMR3GIE CTMUIP TMR3GIP FERR OERR EUSARTx Transmit Register EUSARTx Baud Rate Generator Register High Byte EUSARTx Baud Rate Generator Register Low Byte -- -- -- -- Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission. Note 1: These bits are only available on 44-pin devices. DS39932C-page 332 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 19.2.2 EUSART ASYNCHRONOUS RECEIVER 19.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT The receiver block diagram is displayed in Figure 19-6. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. 3. If interrupts are desired, set enable bit, RCxIE. 4. If 9-bit reception is desired, set bit, RX9. 5. Enable the reception by setting bit, CREN. 6. Flag bit, RCxIF, will be set when reception is complete and an interrupt will be generated if enable bit, RCxIE, was set. 7. Read the RCSTAx register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREGx register. 9. If any error occurred, clear the error by clearing enable bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 1. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCxIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCxIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCxIE and GIE bits are set. 8. Read the RCSTAx register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREGx to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. FIGURE 19-6: EUSARTx RECEIVE BLOCK DIAGRAM CREN x64 Baud Rate CLK OERR FERR BRG16 SPBRGHx SPBRGx Baud Rate Generator / 64 or / 16 or /4 MSb Stop (8) 7 RSR Register *** 1 0 LSb Start RX9 Pin Buffer and Control RXx Data Recovery RX9D RCREGx Register FIFO SPEN 8 Interrupt RCxIF RCxIE Data Bus (c) 2009 Microchip Technology Inc. DS39932C-page 333 PIC18F46J11 FAMILY FIGURE 19-7: RXx (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN ASYNCHRONOUS RECEPTION Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 1 RCREGx Word 2 RCREGx Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set. TABLE 19-6: Name INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTAx RCREGx TXSTAx SPBRGHx SPBRGx REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 TMR0IE RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP Bit 4 INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXCKP Bit 3 RBIE SSP1IF SSP1IE SSP1IP TMR4IF TMR4IE TMR4IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP RTCCIF RTCCIE RTCCIP RX9D TX9D ABDEN Reset Values on Page: 63 65 65 65 65 65 65 65 65 BRGH -- TRMT WUE 65 66 66 65 GIE/GIEH PEIE/GIEL PMPIF(1) PMPIE(1) PMPIP(1) SSP2IF SSP2IE SSP2IP SPEN CSRC ADIF ADIE ADIP BCL2IF BCL2IE BCL2IP RX9 TX9 RCIDL CTMUIF TMR3GIF CTMUIE TMR3GIE CTMUIP TMR3GIP FERR OERR EUSARTx Receive Register BAUDCONx ABDOVF EUSARTx Baud Rate Generator Register High Byte EUSARTx Baud Rate Generator Register Low Byte Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception. Note 1: These bits are only available on 44-pin devices. 19.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the BRG is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RXx/DTx line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>). Once set, the typical receive sequence on RXx/DTx is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RXx/DTx line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN protocol.) Following a wake-up event, the module generates an RCxIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 19-8) and asynchronously if the device is in Sleep mode (Figure 19-9). The interrupt condition is cleared by reading the RCREGx register. DS39932C-page 334 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The WUE bit is automatically cleared once a low-to-high transition is observed on the RXx line following the wake-up event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. 19.2.4.2 Special Considerations Using the WUE Bit 19.2.4.1 Special Considerations Using Auto-Wake-up Since auto-wake-up functions by sensing rising edge transitions on RXx/DTx, information with any state changes before the Stop bit may signal a false End-Of-Character (EOC) and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all `0's. This can be 00h (8 bytes) for standard RS-232 devices or 000h (12 bits) for LIN bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., HS or HSPLL mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. The timing of WUE and RCxIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared after this when a rising edge is seen on RXx/DTx. The interrupt condition is then cleared by reading the RCREGx register. Ordinarily, the data in RCREGx will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set) and the RCxIF flag is set should not be used as an indicator of the integrity of the data in RCREGx. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. FIGURE 19-8: OSC1 WUE bit(1) RXx/DTx Line RCxIF AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Bit set by user Auto-Cleared Cleared due to user read of RCREGx Note 1: The EUSART remains in Idle while the WUE bit is set. FIGURE 19-9: OSC1 WUE bit(2) RXx/DTx Line RCxIF AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Bit set by user Auto-Cleared Note 1 Sleep Ends Cleared due to user read of RCREGx SLEEP Command Executed Note 1: 2: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. (c) 2009 Microchip Technology Inc. DS39932C-page 335 PIC18F46J11 FAMILY 19.2.5 BREAK CHARACTER SEQUENCE 19.2.5.1 Break and Sync Transmit Sequence The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve `0' bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>) are set while the Transmit Shift Register is loaded with data. Note that the value of data written to TXREGx will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). Note that the data value written to the TXREGx for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 19-10 for the timing of the Break character sequence. The following sequence will send a message frame header made up of a Break, followed by an Auto-Baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to set up the Break character. Load the TXREGx with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREGx to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode. When the TXREGx becomes empty, as indicated by the TXxIF, the next data byte can be written to TXREGx. 19.2.6 RECEIVING A BREAK CHARACTER The Enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 19.2.4 "Auto-Wake-up on Sync Break Character". By enabling this feature, the EUSART will sample the next two transitions on RXx/DTx, cause an RCxIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABDEN bit once the TXxIF interrupt is observed. FIGURE 19-10: Write to TXREGx BRG Output (Shift Clock) TXx (pin) SEND BREAK CHARACTER SEQUENCE Dummy Write Start Bit Bit 0 Bit 1 Break Bit 11 Stop Bit TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here SENDB bit (Transmit Shift Reg. Empty Flag) Auto-Cleared DS39932C-page 336 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 19.3 EUSART Synchronous Master Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF is set regardless of the state of enable bit, TXxIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register. While flag bit, TXxIF, indicates the status of the TXREGx register, another bit, TRMT (TXSTAx<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user must poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. To set up a Synchronous Master Transmission: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the required baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. If interrupts are desired, set enable bit, TXxIE. If 9-bit transmission is required, set bit, TX9. Enable the transmission by setting bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREGx register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. The Synchronous Master mode is entered by setting the CSRC bit (TXSTAx<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTAx<4>). In addition, enable bit, SPEN (RCSTAx<7>), is set in order to configure the TXx and RXx pins to CKx (clock) and DTx (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CKx line. Clock polarity is selected with the TXCKP bit (BAUDCONx<4>). Setting TXCKP sets the Idle state on CKx as high, while clearing the bit sets the Idle state as low. This option is provided to support Microwire devices with this module. 19.3.1 EUSART SYNCHRONOUS MASTER TRANSMISSION 2. 3. 4. 5. 6. 7. 8. The EUSART transmitter block diagram is shown in Figure 19-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREGx. The TXREGx register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREGx (if available). FIGURE 19-11: SYNCHRONOUS TRANSMISSION Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 7 bit 0 bit 1 bit 7 Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX1/DT1/ SDO1/RP18 RC6/TX1/CK1/RP17 pin (TXCKP = 0) RC6/TX1/CK1 pin (TXCKP = 1) Write to TXREG1 Reg TX1IF bit (Interrupt Flag) TRMT bit TXEN bit `1' bit 0 bit 1 bit 2 Word 1 Word 2 Write Word 1 Write Word 2 `1' Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. This example is equally applicable to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2). (c) 2009 Microchip Technology Inc. DS39932C-page 337 PIC18F46J11 FAMILY FIGURE 19-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) bit 0 bit 1 bit 2 bit 6 bit 7 RC7/RX1/DT1/ SDO1/RP18 pin RC6/TX1/CK1/RP17 pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2). TABLE 19-7: Name INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTAx TXREGx TXSTAx SPBRGHx SPBRGx ODCON2 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXCKP Bit 3 RBIE SSP1IF SSP1IE SSP1IP TMR4IF TMR4IE TMR4IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP RTCCIF Reset Values on Page: 63 65 65 65 65 65 65 65 65 BRGH -- TRMT WUE TX9D ABDEN 65 66 66 65 U2OD U1OD 68 GIE/GIEH PEIE/GIEL TMR0IE PMPIF(1) PMPIE(1) PMPIP(1) SSP2IF SSP2IE SSP2IP SPEN CSRC ADIF ADIE ADIP BCL2IF BCL2IE BCL2IP RX9 TX9 RCIDL RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP CTMUIF TMR3GIF CTMUIE TMR3GIE RTCCIE CTMUIP TMR3GIP RTCCIP FERR OERR RX9D EUSARTx Transmit Register BAUDCONx ABDOVF EUSARTx Baud Rate Generator Register High Byte EUSARTx Baud Rate Generator Register Low Byte -- -- -- -- Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission. Note 1: These pins are only available on 44-pin devices. DS39932C-page 338 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 19.3.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>) or the Continuous Receive Enable bit, CREN (RCSTAx<4>). Data is sampled on the RXx pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. 3. 4. 5. 6. Ensure bits, CREN and SREN, are clear. If interrupts are desired, set enable bit, RCxIE. If 9-bit reception is desired, set bit, RX9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 7. Interrupt flag bit, RCxIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCxIE, was set. 8. Read the RCSTAx register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREGx register. 10. If any error occurred, clear the error by clearing bit, CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 2. FIGURE 19-13: RC7/RX1/DT1/ SDO1/RP18 pin RC6/TX1/CK1/RP17 pin (TXCKP = 0) RC6/TX1/CK1/RP17 pin (TXCKP = 1) Write to bit SREN SREN bit CREN bit `0' RC1IF bit (Interrupt) Read RCREG1 SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 `0' Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2). (c) 2009 Microchip Technology Inc. DS39932C-page 339 PIC18F46J11 FAMILY TABLE 19-8: Name INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTAx RCREGx TXSTAx SPBRGHx SPBRGx ODCON2 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXCKP Bit 3 RBIE SSP1IF SSP1IE SSP1IP TMR4IF TMR4IE TMR4IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Reset Values on Page: 63 65 65 65 65 65 65 65 65 BRGH -- TRMT WUE TX9D ABDEN 65 66 66 65 U2OD U1OD 68 GIE/GIEH PEIE/GIEL TMR0IE PMPIF (1) ADIF ADIE ADIP BCL2IF BCL2IE BCL2IP RX9 TX9 RCIDL RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP PMPIE(1) PMPIP(1) SSP2IF SSP2IE SSP2IP SPEN CSRC CTMUIF TMR3GIF RTCCIF CTMUIE TMR3GIE RTCCIE CTMUIP TMR3GIP RTCCIP FERR OERR RX9D EUSARTx Receive Register BAUDCONx ABDOVF EUSARTx Baud Rate Generator Register High Byte EUSARTx Baud Rate Generator Register Low Byte -- -- -- -- Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception. Note 1: These pins are only available on 44-pin devices. DS39932C-page 340 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 19.4 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. Clear bits, CREN and SREN. If interrupts are desired, set enable bit, TXxIE. If 9-bit transmission is desired, set bit, TX9. Enable the transmission by setting enable bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREGx register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 2. 3. 4. 5. 6. 7. 8. 19.4.1 EUSART SYNCHRONOUS SLAVE TRANSMISSION The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep mode. If two words are written to the TXREGx and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in the TXREGx register. Flag bit, TXxIF, will not be set. When the first word has been shifted out of TSR, the TXREGx register will transfer the second word to the TSR and flag bit, TXxIF, will now be set. If enable bit, TXxIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. e) (c) 2009 Microchip Technology Inc. DS39932C-page 341 PIC18F46J11 FAMILY TABLE 19-9: Name INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTAx TXREGx TXSTAx SPBRGHx SPBRGx REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXCKP Bit 3 RBIE SSP1IF SSP1IE SSP1IP TMR4IF TMR4IE TMR4IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP CTMUIF Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3GIF Bit 0 RBIF TMR1IF TMR1IE TMR1IP RTCCIF RTCCIE RTCCIP RX9D TX9D ABDEN Reset Values on Page: 63 65 65 65 65 65 65 65 65 BRGH -- TRMT WUE 65 66 66 65 GIE/GIEH PEIE/GIEL TMR0IE PMPIF(1) PMPIE(1) PMPIP (1) ADIF ADIE ADIP BCL2IF BCL2IE BCL2IP RX9 TX9 RCIDL RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP SSP2IF SSP2IE SSP2IP SPEN CSRC CTMUIE TMR3GIE CTMUIP TMR3GIP FERR OERR EUSARTx Transmit Register BAUDCONx ABDOVF EUSARTx Baud Rate Generator Register High Byte EUSARTx Baud Rate Generator Register Low Byte Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission. Note 1: These pins are only available on 44-pin devices. DS39932C-page 342 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 19.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. If interrupts are desired, set enable bit, RCxIE. If 9-bit reception is desired, set bit, RX9. To enable reception, set enable bit, CREN. Flag bit, RCxIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCxIE, was set. Read the RCSTAx register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREGx register. If any error occurred, clear the error by clearing bit, CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit, SREN, which is a "don't care" in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSR register will transfer the data to the RCREGx register. If the RCxIE enable bit is set, the interrupt generated will wake the chip from the low-power mode. If the global interrupt is enabled, the program will branch to the interrupt vector. 2. 3. 4. 5. 6. 7. 8. 9. TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 RCSTAx RCREGx TXSTAx SPBRGHx SPBRGx Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP CREN SYNC TXCKP Bit 3 RBIE SSP1IF SSP1IE SSP1IP TMR4IF TMR4IE TMR4IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP CTMUIF Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3GIF Bit 0 RBIF TMR1IF TMR1IE TMR1IP RTCCIF RTCCIE RTCCIP RX9D TX9D ABDEN Reset Values on Page: 63 65 65 65 65 65 65 65 65 BRGH -- TRMT WUE 65 66 66 65 GIE/GIEH PEIE/GIEL TMR0IE PMPIF(1) PMPIE(1) PMPIP(1) SSP2IF SSP2IE SSP2IP SPEN CSRC ADIF ADIE ADIP BCL2IF BCL2IE BCL2IP RX9 TX9 RCIDL RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP SREN TXEN RXDTP CTMUIE TMR3GIE CTMUIP TMR3GIP FERR OERR EUSARTx Receive Register BAUDCONx ABDOVF EUSARTx Baud Rate Generator Register High Byte EUSARTx Baud Rate Generator Register Low Byte Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception. Note 1: These pins are only available on 44-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 343 PIC18F46J11 FAMILY NOTES: DS39932C-page 344 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 20.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE * * * * A/D Control Register 1 (ADCON1) A/D Port Configuration Register 2 (ANCON0) A/D Port Configuration Register 1 (ANCON1) A/D Result Registers (ADRESH and ADRESL) The Analog-to-Digital (A/D) Converter module has 10 inputs for the 28-pin devices and 13 for the 44-pin devices. Additionally, two internal channels are available for sampling the VDDCORE and VBG absolute reference voltage. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. The module has six registers: * A/D Control Register 0 (ADCON0) The ADCON0 register, in Register 20-1, controls the operation of the A/D module. The ADCON1 register, in Register 20-2, configures the A/D clock source, programmed acquisition time and justification. The ANCON0 and ANCON1 registers, in Register 20-3 and Register 20-4, configure the functions of the port pins. REGISTER 20-1: R/W-0 VCFG1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7 ADCON0: A/D CONTROL REGISTER 0 (ACCESS FC2h) R/W-0 CHS3(2) R/W-0 CHS2(2) R/W-0 CHS1(2) R/W-0 CHS0(2) R/W-0 GO/DONE R/W-0 ADON bit 0 R/W-0 VCFG0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = AVSS VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = AVDD CHS<3:0>: Analog Channel Select bits(2) 0000 = Channel 00 (AN0) 0001 = Channel 01 (AN1) 0010 = Channel 02 (AN2) 0011 = Channel 03 (AN3) 0100 = Channel 04 (AN4) 0101 = Channel 05 (AN5)(1) 0110 = Channel 06 (AN6)(1) 0111 = Channel 07 (AN7)(1) 1000 = Channel 08 (AN8) 1001 = Channel 09 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12) 1101 = (Reserved) 1110 = VDDCORE 1111 = VBG Absolute Reference (~1.2V)(3) GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled These channels are not implemented on 28-pin devices. Performing a conversion on unimplemented channels will return random values. For best accuracy, the band gap reference circuit should be enabled (ANCON1<7> = 1) at least 10 ms before performing a conversion on this channel. DS39932C-page 345 bit 6 bit 5-2 bit 1 bit 0 Note 1: 2: 3: (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 20-2: R/W-0 ADFM bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ADCON1: A/D CONTROL REGISTER 1 (ACCESS FC1h) R/W-0 ACQT2 R/W-0 ACQT1 R/W-0 ACQT0 R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 bit 0 R/W-0 ADCAL ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified ADCAL: A/D Calibration bit 1 = Calibration is performed on next A/D conversion 0 = Normal A/D Converter operation ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD ADCS<2:0>: A/D Conversion Clock Select bits 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. bit 6 bit 5-3 bit 2-0 Note 1: DS39932C-page 346 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The ANCON0 and ANCON1 registers are used to configure the operation of the I/O pin associated with each analog channel. Setting any one of the PCFG bits configures the corresponding pin to operate as a digital only I/O. Clearing a bit configures the pin to operate as an analog input for either the A/D Converter or the comparator module; all digital peripherals are disabled and digital inputs read as `0'. As a rule, I/O pins that are multiplexed with analog inputs default to analog operation on device Resets. In order to correctly perform A/D conversions on the VBG band gap reference (ADCON0<5:2> = 1111), the reference circuit must be powered on first. The VBGEN bit in the ANCON1 register allows the firmware to manually request that the band gap reference circuit should be enabled. For best accuracy, firmware should allow a settling time of at least 10 ms prior to performing the first acquisition on this channel after enabling the band gap reference. The reference circuit may already have been turned on if some other hardware module (such as the on-chip voltage regulator, comparators or HLVD) has already requested it. In this case, the initial turn-on settling time may have already elapsed and firmware does not need to wait as long before measuring VBG. Once the acquisition is complete, firmware may clear the VBGEN bit, which will save a small amount of power if no other modules are still requesting the VBG reference. REGISTER 20-3: R/W-0 PCFG7(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 ANCON0: A/D PORT CONFIGURATION REGISTER 2 (BANKED F48h) R/W-0 PCFG5(1) R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0 R/W-0 PCFG6(1) W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PCFG<7:0>: Analog Port Configuration bits (AN<7:0>) 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' These bits are not implemented on 28-pin devices. Note 1: REGISTER 20-4: R/W-0 VBGEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 r ANCON1: A/D PORT CONFIGURATION REGISTER 1 (BANKED F49h) U-0 -- R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 R/W-0 PCFG8 bit 0 r = Reserved W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown -- VBGEN: 1.2V Band Gap Reference Enable bit 1 = 1.2V band gap reference is powered on 0 = 1.2V band gap reference is turned off to save power (if no other modules are requesting it) Reserved: Always maintain as `0' for lowest power consumption Unimplemented: Read as `0' PCFG<12:8>: Analog Port Configuration bits (AN<12:8>) 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads `0' bit 6 bit 5 bit 4-0 (c) 2009 Microchip Technology Inc. DS39932C-page 347 PIC18F46J11 FAMILY The analog reference voltage is software selectable to either the device's positive and negative supply voltage (AVDD and AVSS), or the voltage and level on the RA3/AN3/VREF+/C1INB RA2/AN2/VREF-/CVREF/C2INB pins. The A/D Converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the Converter, which generates the result via successive approximation. Each port pin associated with the A/D Converter can be configured as an analog input or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0<1>) is cleared and the A/D Interrupt Flag bit, ADIF, is set. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. The value in the ADRESH:ADRESL register pair is not modified for a Power-on Reset (POR). These registers will contain unknown data after a POR. Figure 20-1 provides the block diagram of the A/D module. FIGURE 20-1: A/D BLOCK DIAGRAM CHS<3:0> 1111 1110 1100 1011 1010 1001 1000 0111 0110 VAIN (Input Voltage) 0101 0100 0011 0010 Reference Voltage VREF+ VREFVSS(2) VCFG<1:0> VDD(2) 0001 0000 VBG VDDCORE/VCAP AN12 AN11 AN10 AN9 AN8 AN7(1) AN6(1) AN5(1) AN4 AN3 AN2 AN1 AN0 10-Bit A/D Converter Note 1: Channels AN5, AN6 and AN7 are not available on 28-pin devices. 2: I/O pins have diode protection to VDD and VSS. DS39932C-page 348 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 20.1 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. The following steps should be followed to do an A/D conversion: 1. Configure the A/D module: * Configure the required ADC pins as analog pins using ANCON0, ANCON1 * Set voltage reference using ADCON0 * Select A/D input channel (ADCON0) * Select A/D acquisition time (ADCON1) * Select A/D conversion clock (ADCON1) * Turn on A/D module (ADCON0) 6. 7. 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (if required). Start conversion: * Set GO/DONE bit (ADCON0<1>) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit, ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before next acquisition starts. 3. 4. 5. FIGURE 20-2: ANALOG INPUT MODEL VDD VT = 0.6V RIC 1k Sampling Switch SS RSS RS ANx VAIN CPIN 5 pF VT = 0.6V ILEAKAGE 100 nA CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch SS = Sample/Hold Capacitance (from DAC) CHOLD RSS = Sampling Switch Resistance VDD 1 2 3 4 Sampling Switch (k) (c) 2009 Microchip Technology Inc. DS39932C-page 349 PIC18F46J11 FAMILY 20.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is illustrated in Figure 20-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. To calculate the minimum acquisition time, Equation 20-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Equation 20-3 provides the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assumptions: CHOLD Rs Conversion Error VDD Temperature = = = = 25 pF 2.5 k 1/2 LSb 3V Rss = 2 k 85C (system max.) EQUATION 20-1: TACQ = = ACQUISITION TIME Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF EQUATION 20-2: VHOLD or TC = = A/D MINIMUM CHARGING TIME (VREF - (VREF/2048)) * (1 - e(-TC/CHOLD(RIC + RSS + RS))) -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 20-3: TACQ TAMP TCOFF = = = 0.2 ms CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TAMP + TC + TCOFF (Temp - 25C)(0.02 s/C) (85C - 25C)(0.02 s/C) 1.2 s -(CHOLD)(RIC + RSS + RS) ln(1/2048) s -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s 1.05 s 0.2 s + 1.05 s + 1.2 s 2.45 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 s. TC = TACQ = DS39932C-page 350 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 20.2 Selecting and Configuring Automatic Acquisition Time TABLE 20-1: TAD vs. DEVICE OPERATING FREQUENCIES Maximum Device Frequency 2.86 MHz 5.71 MHz 11.43 MHz 22.86 MHz 45.71 MHz 48.0 MHz 1.00 MHz(1) AD Clock Source (TAD) Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC(2) Note 1: 2: ADCS<2:0> 000 100 001 101 010 110 011 The ADCON1 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT<2:0> bits (ADCON1<5:3>) remain in their Reset state (`000') and is compatible with devices that do not offer programmable acquisition times. If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. The RC source has a typical TAD time of 4 s. For device frequencies above 1 MHz, the device must be in Sleep mode for the entire conversion or the A/D accuracy may be out of specification. 20.4 Configuring Analog Port Pins The ANCON0, ANCON1 and TRISA registers control the operation of the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS<3:0> bits and the TRIS bits. Note 1: When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits. 20.3 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD (see parameter 130 in Table 28-28 for more information). Table 20-1 provides the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. (c) 2009 Microchip Technology Inc. DS39932C-page 351 PIC18F46J11 FAMILY 20.5 A/D Conversions 20.6 Use of the ECCP2 Trigger Figure 20-3 displays the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Figure 20-4 displays the operation of the A/D Converter after the GO/DONE bit has been set, the ACQT<2:0> bits are set to `010' and a 4 TAD acquisition time has been selected before the conversion starts. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. An A/D conversion can be started by the Special Event Trigger of the ECCP2 module. This requires that the CCP2M<3:0> bits (CCP2CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion, and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time is selected before the Special Event Trigger sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the Special Event Trigger will be ignored by the A/D module but will still reset the Timer1 (or Timer3) counter. FIGURE 20-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 20-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles 1 2 3 4 1 2 b9 3 b8 4 b7 TAD Cycles 5 b6 6 b5 7 b4 8 b3 9 b2 10 b1 11 b0 Automatic Acquisition Time Conversion starts (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) Next Q4: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. DS39932C-page 352 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 20.7 A/D Converter Calibration The A/D Converter in the PIC18F46J11 family of devices includes a self-calibration feature, which compensates for any offset generated within the module. The calibration process is automated and is initiated by setting the ADCAL bit (ADCON1<6>). The next time the GO/DONE bit is set, the module will perform a "dummy" conversion (that is, with reading none of the input channels) and store the resulting value internally to compensate for the offset. Thus, subsequent offsets will be compensated. Example 20-1 provides an example of a calibration routine. The calibration process assumes that the device is in a relatively steady-state operating condition. If A/D calibration is used, it should be performed after each device Reset or if there are other major changes in operating conditions. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and ADCS<2:0> bits in ADCON1 should be updated in accordance with the power-managed mode clock that will be used. After the power-managed mode is entered (either of the power-managed Run modes), an A/D acquisition or conversion may be started. Once an acquisition or conversion is started, the device should continue to be clocked by the same power-managed mode clock source until the conversion has been completed. If desired, the device may be placed into the corresponding power-managed Idle mode during the conversion. If the power-managed mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in the Sleep mode requires the A/D RC clock to be selected. If bits, ACQT<2:0>, are set to `000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN and SCS bits in the OSCCON register must have already been cleared prior to starting the conversion. 20.8 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. EXAMPLE 20-1: BCF BSF BSF BSF CALIBRATION BTFSC BRA BCF SAMPLE A/D CALIBRATION ROUTINE ANCON0,PCFG0 ADCON0,ADON ADCON1,ADCAL ADCON0,GO ADCON0,GO CALIBRATION ADCON1,ADCAL ;Make Channel 0 analog ;Enable A/D module ;Enable Calibration ;Start a dummy A/D conversion ; ;Wait for the dummy conversion to finish ; ;Calibration done, turn off calibration enable ;Proceed with the actual A/D conversion (c) 2009 Microchip Technology Inc. DS39932C-page 353 PIC18F46J11 FAMILY TABLE 20-2: Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 ADRESH ADRESL ADCON0 ANCON0 ADCON1 ANCON1 CCP2CON PORTA TRISA SUMMARY OF A/D REGISTERS Bit 7 Bit 6 Bit 5 TMR0IE RC1IF RC1IE RC1IP CM1IF CM1IE CM1IP Bit 4 INT0IE TX1IF TX1IE TX1IP -- -- -- Bit 3 RBIE SSP1IF SSP1IE SSP1IP BCL1IF BCL1IE BCL1IP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP LVDIF LVDIE LVDIP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3IF TMR3IE TMR3IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP Reset Values on Page: 63 65 65 65 65 65 65 64 64 CHS3 PCFG4 ACQT1 PCFG12 DC2B0 -- -- CHS1 PCFG3 ACQT0 PCFG11 CCP2M3 RA3 TRISA3 CHS0 PCFG2 ADCS2 PCFG10 CCP2M2 RA2 TRISA2 GO/DONE PCFG1 ADCS1 PCFG9 CCP2M1 RA1 TRISA1 ADON PCFG0 ADCS0 PCFG8 CCP2M0 RA0 TRISA0 64 68 64 68 65 66 66 GIE/GIEH PEIE/GIEL PMPIF(1) PMPIE PMPIP (1) (1) ADIF ADIE ADIP CM2IF CM2IE CM2IP OSCFIF OSCFIE OSCFIP A/D Result Register High Byte A/D Result Register Low Byte VCFG1 ADFM VBGEN P2M1 RA7 TRISA7 VCFG0 ADCAL r(2) P2M0 RA6 TRISA6 CHS3 ACQT2 -- DC2B1 RA5 TRISA5 PCFG7(1) PCFG6(1) PCFG5(1) Legend: -- = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. Note 1: These bits are only available on 44-pin devices. 2: Reserved. Always maintain as `0' for minimum power consumption. DS39932C-page 354 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 21.0 COMPARATOR MODULE 21.1 Registers The analog comparator module contains two comparators that can be independently configured in a variety of ways. The inputs can be selected from the analog inputs and two internal voltage references. The digital outputs are available at the pin level and can also be read through the control register. Multiple output and interrupt event generation is also available. Figure 21-1 provides a generic single comparator from the module. Key features of the module are: * * * * * Independent comparator control Programmable input configuration Output to both pin and register levels Programmable output polarity Independent interrupt generation for each comparator with configurable interrupt-on-change The CMxCON registers (Register 21-1) select the input and output configuration for each comparator, as well as the settings for interrupt generation. The CMSTAT register (Register 21-2) provides the output results of the comparators. The bits in this register are read-only. FIGURE 21-1: CCH<1:0> COMPARATOR SIMPLIFIED BLOCK DIAGRAM COUTx (CMSTAT<1:0>) CxINB VIRV 0 3 Interrupt Logic CMxIF EVPOL<4:3> CREF VIN- COE Cx Polarity Logic CxOUT CxINA CVREF 0 1 VIN+ CON CPOL (c) 2009 Microchip Technology Inc. DS39932C-page 355 PIC18F46J11 FAMILY REGISTER 21-1: R/W-0 CON bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CMxCON: COMPARATOR CONTROL x REGISTER (ACCESS FD2h/FD1h) R/W-0 CPOL R/W-1 EVPOL1 R/W-1 EVPOL0 R/W-1 CREF R/W-1 CCH1 R/W-1 CCH0 bit 0 COE R/W-0 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin (assigned in PPS module) 0 = Comparator output is internal only CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted EVPOL<1:0>: Interrupt Polarity Select bits 11 = Interrupt generation on any change of the output(1) 10 = Interrupt generation only on high-to-low transition of the output 01 = Interrupt generation only on low-to-high transition of the output 00 = Interrupt generation is disabled CREF: Comparator Reference Select bit (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CxINA pin CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects to VIRV 10 = For CM1CON, inverting input of comparator connects to C2INB pin; for CM2CON, reserved 01 = Reserved 00 = Inverting input of comparator connects to CxINB pin The CMxIF is automatically set any time this mode is selected and must be cleared by the application after the initial configuration. bit 6 bit 5 bit 4-3 bit 2 bit 1-0 Note 1: DS39932C-page 356 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 21-2: U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CMSTAT: COMPARATOR STATUS REGISTER (ACCESS F70h) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-1 COUT2 R-1 COUT1 bit 0 Unimplemented: Read as `0' COUT<2:1>: Comparator x Status bits If CPOL = 0 (non-inverted polarity): 1 = Comparator VIN+ > VIN0 = Comparator VIN+ < VINIf CPOL = 1 (inverted polarity): 1 = Comparator VIN+ < VIN0 = Comparator VIN+ > VIN- (c) 2009 Microchip Technology Inc. DS39932C-page 357 PIC18F46J11 FAMILY 21.2 Comparator Operation 21.3 Comparator Response Time A single comparator is shown in Figure 21-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input, VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input, VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 21-2 represent the uncertainty due to input offsets and response time. Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response to a comparator input change. Otherwise, the maximum delay of the comparators should be used (see Section 28.0 "Electrical Characteristics"). FIGURE 21-2: VIN+ VIN- SINGLE COMPARATOR + - 21.4 Analog Input Connection Considerations Output VINVIN+ Output Figure 21-3 provides a simplified circuit for an analog input. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. FIGURE 21-3: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k AIN VT = 0.6V RIC Comparator Input CPIN 5 pF VT = 0.6V ILEAKAGE 100 nA VA VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage DS39932C-page 358 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 21.5 Comparator Control and Configuration The external reference is used when CREF = 0 (CMxCON<2>) and VIN+ is connected to the CxINA pin. When external voltage references are used, the comparator module can be configured to have the reference sources externally. The reference signal must be between VSS and VDD, and can be applied to either pin of the comparator. The comparator module also allows the selection of an internally generated voltage reference (CVREF) from the comparator voltage reference module. This module is described in more detail in Section 21.0 "Comparator Module". The reference from the comparator voltage reference module is only available when CREF = 1. In this mode, the internal voltage reference is applied to the comparator's VIN+ pin. Note: The comparator input pin selected by CCH<1:0> must be configured as an input by setting both the corresponding TRIS and PCFG bits in the ANCON1 register. Each comparator has up to eight possible combinations of inputs: up to four external analog inputs, and one of two internal voltage references. Both comparators allow a selection of the signal from pin, CxINA, or the voltage from the comparator reference (CVREF) on the non-inverting channel. This is compared to either CxINB, CTMU or the microcontroller's fixed internal reference voltage (VIRV, 0.6V nominal) on the inverting channel. Table 21-1 provides the comparator inputs and outputs tied to fixed I/O pins. Figure 21-4 illustrates the available comparator configurations and their corresponding bit settings. TABLE 21-1: Comparator COMPARATOR INPUTS AND OUTPUTS Input or Output C1INA (VIN+) C1INB (VIN-) C1OUT C2INA(VIN+) I/O Pin RA0 RA3 Remapped RPn RA1 RA2 Remapped RPn 21.5.2 COMPARATOR ENABLE AND OUTPUT SELECTION 1 The comparator outputs are read through the CMSTAT register. The CMSTAT<0> reads the Comparator 1 output and CMSTAT<1> reads the Comparator 2 output. These bits are read-only. The comparator outputs may also be directly output to the RPn I/O pins by setting the COE bit (CMxCON<6>). When enabled, multiplexers in the output path of the pins switch to the output of the comparator. By default, the comparator's output is at logic high whenever the voltage on VIN+ is greater than on VIN-. The polarity of the comparator outputs can be inverted using the CPOL bit (CMxCON<5>). The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications, as discussed in Section 21.2 "Comparator Operation". 2 C2INB(VIN-) C2OUT 21.5.1 COMPARATOR ENABLE AND INPUT SELECTION Setting the CON bit of the CMxCON register (CMxCON<7>) enables the comparator for operation. Clearing the CON bit disables the comparator, resulting in minimum current consumption. The CCH<1:0> bits in the CMxCON register (CMxCON<1:0>) direct either one of three analog input pins, or the Internal Reference Voltage (VIRV), to the comparator VIN-. Depending on the comparator operating mode, either an external or internal voltage reference may be used. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly. (c) 2009 Microchip Technology Inc. DS39932C-page 359 PIC18F46J11 FAMILY FIGURE 21-4: COMPARATOR CONFIGURATIONS COE VINVIN+ Comparator Off CON = 0, CREF = x, CCH<1:0> = xx Cx Off (Read as `0') CxOUT pin Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 COE CxINB CxINA VINVIN+ Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 01 COE CxINC VINVIN+ Cx CxOUT pin CxINA Cx CxOUT pin Comparator CxIND > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 10 COE CxIND CxINA VINVIN+ Comparator VIRV > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 11 COE VIRV VINVIN+ Cx CxOUT pin CxINA Cx CxOUT pin Comparator CxINB > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 00 COE CxINB CVREF VINVIN+ Comparator CxINC > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 01 COE CxINC VINVIN+ Cx CxOUT pin CVREF Cx CxOUT pin Comparator CxIND > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 10 COE CxIND CVREF Note: VINVIN+ Comparator VIRV > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 11 COE VIRV VINVIN+ Cx CxOUT pin CVREF Cx CxOUT pin VIRV is the Internal Reference Voltage (see Table 28-2). DS39932C-page 360 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 21.6 Comparator Interrupts The comparator interrupt flag is set whenever any of the following occurs: - Low-to-high transition of the comparator output - High-to-low transition of the comparator output - Any change in the comparator output The comparator interrupt selection is done by the EVPOL<1:0> bits in the CMxCON register (CMxCON<4:3>). In order to provide maximum flexibility, the output of the comparator may be inverted using the CPOL bit in the CMxCON register (CMxCON<5>). This is functionally identical to reversing the inverting and non-inverting inputs of the comparator for a particular mode. An interrupt is generated on the low-to-high or high-tolow transition of the comparator output. This mode of interrupt generation is dependent on EVPOL<1:0> in the CMxCON register. When EVPOL<1:0> = 01 or 10, the interrupt is generated on a low-to-high or high-tolow transition of the comparator output. Once the interrupt is generated, it is required to clear the interrupt flag by software. When EVPOL<1:0> = 11, the comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMSTAT<1:0>, to determine the actual change that occurred. The CMxIF bits (PIR2<6:5>) are the Comparator Interrupt Flags. The CMxIF bits must be reset by clearing them. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. Table 21-2 provides the interrupt generation corresponding to comparator input voltages and EVPOL bit settings. Both the CMxIE bits (PIE2<6:5>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit (INTCON<7>) must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMxIF bits will still be set if an interrupt condition occurs. Figure 21-1 provides a simplified diagram of the interrupt section. TABLE 21-2: CPOL COMPARATOR INTERRUPT GENERATION EVPOL<1:0> 00 01 Comparator Input Change VIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINVIN+ > VINVIN+ < VINCOUTx Transition Low-to-High High-to-Low Low-to-High High-to-Low Low-to-High High-to-Low Low-to-High High-to-Low High-to-Low Low-to-High High-to-Low Low-to-High High-to-Low Low-to-High High-to-Low Low-to-High Interrupt Generated No No Yes No No Yes Yes Yes No No No Yes Yes No Yes Yes 0 10 11 00 01 1 10 11 (c) 2009 Microchip Technology Inc. DS39932C-page 361 PIC18F46J11 FAMILY 21.7 Comparator Operation During Sleep 21.8 Effects of a Reset A device Reset forces the CMxCON registers to their Reset state. This forces both comparators and the voltage reference to the OFF state. When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode when enabled. Each operational comparator will consume additional current. To minimize power consumption while in Sleep mode, turn off the comparators (CON = 0) before entering Sleep. If the device wakes up from Sleep, the contents of the CMxCON register are not affected. TABLE 21-3: Name INTCON PIR2 PIE2 IPR2 CMxCON CVRCON(1) CMSTAT ANCON0 PORTA TRISA REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 TMR0IE CM1IF CM1IE CM1IP CPOL CVRR -- PCFG5(1) RA5 TRISA5 Bit 4 INT0IE -- -- -- EVPOL1 CVRSS -- PCFG4 -- -- Bit 3 RBIE BCL1IF BCL1IE BCL1IP EVPOL0 CVR3 -- PCFG3 RA3 TRISA3 Bit 2 TMR0IF LVDIF LVDIE LVDIP CREF CVR2 -- PCFG2 RA2 TRISA2 Bit 1 INT0IF TMR3IF TMR3IE TMR3IP CCH1 CVR1 COUT2 PCFG1 RA1 TRISA1 Bit 0 RBIF CCP2IF CCP2IE CCP2IP CCH0 CVR0 COUT1 PCFG0 RA0 TRISA0 Reset Values on Page: 63 65 65 65 64 68 67 68 66 66 GIE/GIEH PEIE/GIEL OSCFIF OSCFIE OSCFIP CON CVREN -- PCFG7(1) RA7 TRISA7 CM2IF CM2IE CM2IP COE CVROE -- PCFG6(1) RA6 TRISA6 Legend: -- = unimplemented, read as `0', r = reserved. Shaded cells are not related to comparator operation. Note 1: These bits and/or registers are not implemented on 28-pin devices. DS39932C-page 362 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 22.0 COMPARATOR VOLTAGE REFERENCE MODULE Figure 22-1 provides a block diagram of the module. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ VDD CVRSS = 1 CVRSS = 0 8R R R R CVR<3:0> CVREN 16 Steps 16-to-1 MUX R CVREF R R R CVRR VREFCVRSS = 1 8R CVRSS = 0 (c) 2009 Microchip Technology Inc. DS39932C-page 363 PIC18F46J11 FAMILY 22.1 Configuring the Comparator Voltage Reference The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output (see Table 28-4 in Section 28.0 "Electrical Characteristics"). The comparator voltage reference module is controlled through the CVRCON register (Register 22-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution. The equations used to calculate the output of the comparator voltage reference are as follows: EQUATION 22-1: CALCULATING OUTPUT OF THE COMPARATOR VOLTAGE REFERENCE When CVRR = 1 and CVRSS = 0: CVREF = ((CVR<3:0>)/24) x (CVRSRC) When CVRR = 0 and CVRSS = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) x (CVRSRC) When CVRR = 1 and CVRSS = 1: CVREF = ((CVR<3:0>)/24) x (CVRSRC) + VREFWhen CVRR = 0 and CVRSS = 1: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) x (CVRSRC) +VREF-) REGISTER 22-1: R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER (BANKED F53h) R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 R/W-0 CVR0 bit 0 R/W-0 CVROE(1) W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF/C2INB pin 0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF/C2INB pin CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) - (VREF-) 0 = Comparator reference source, CVRSRC = AVDD - AVSS CVR<3:0>: Comparator VREF Value Selection bits (0 (CVR<3:0>) 15) When CVRR = 1: CVREF = ((CVR<3:0>)/24) * (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) * (CVRSRC) CVROE overrides the TRIS bit setting. (c) 2009 Microchip Technology Inc. bit 6 bit 5 bit 4 bit 3-0 Note 1: DS39932C-page 364 PIC18F46J11 FAMILY 22.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (see Figure 22-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 28.0 "Electrical Characteristics". The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. See Figure 22-2 for an example buffering technique. 22.4 Operation During Sleep 22.3 Connection Considerations When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. The voltage reference module operates independently of the comparator module. The output of the reference generator may be connected to the RA2 pin if the CVROE bit is set. Enabling the voltage reference output onto RA2 when it is configured as a digital input will increase current consumption. Connecting RA2 as a digital output with CVRSS enabled will also increase current consumption. 22.5 Effects of a Reset A device Reset disables the voltage reference by clearing bit, CVREN (CVRCON<7>). This Reset also disconnects the reference from the RA2 pin by clearing bit, CVROE (CVRCON<6>) and selects the high-voltage range by clearing bit, CVRR (CVRCON<5>). The CVR value select bits are also cleared. FIGURE 22-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F46J11 CVREF Module R(1) Voltage Reference Output Impedance RA2 + - CVREF Output Note 1: R is dependent upon the Comparator Voltage Reference Configuration bits, CVRCON<5> and CVRCON<3:0>. TABLE 22-1: Name CVRCON CM1CON CM2CON TRISA ANCON0 ANCON1 REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 7 CVREN CON CON TRISA7 VBGEN Bit 6 CVROE COE COE TRISA6 r Bit 5 CVRR CPOL CPOL TRISA5 -- Bit 4 CVRSS EVPOL1 EVPOL1 -- PCFG4 PCFG12 Bit 3 CVR3 EVPOL0 EVPOL0 TRISA3 PCFG3 PCFG11 Bit 2 CVR2 CREF CREF TRISA2 PCFG2 PCFG10 Bit 1 CVR1 CCH1 CCH1 TRISA1 PCFG1 PCFG9 Bit 0 CVR0 CCH0 CCH0 TRISA0 PCFG0 PCFG8 Reset Values on Page: 68 64 64 66 68 68 PCFG7(1) PCFG6(1) PCFG5(1) Legend: -- = unimplemented, read as `0', r = reserved. Shaded cells are not used with the comparator voltage reference. Note 1: These bits are only available on 44-pin devices. (c) 2009 Microchip Technology Inc. DS39932C-page 365 PIC18F46J11 FAMILY NOTES: DS39932C-page 366 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 23.0 HIGH/LOW VOLTAGE DETECT (HLVD) The High/Low-Voltage Detect Control register (Register 23-1) completely controls the operation of the HLVD module. This allows the circuitry to be "turned off" by the user under software control, which minimizes the current consumption for the device. Figure 23-1 provides a block diagram for the HLVD module. PIC18F46J11 family devices (including PIC18LF46J11 family devices) have a High/Low Voltage Detect (HLVD) module for monitoring the absolute voltage on VDD or the HLVDIN pin. This is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. If the module detects an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. REGISTER 23-1: R/W-0 VDIRMAG bit 7 Legend: R = Readable bit -n = Value at POR bit 7 HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER (ACCESS F85h) R-0 R-0 IRVST R/W-0 HLVDEN R/W-0 HLVDL3(1) R/W-0 HLVDL2(1) R/W-0 HLVDL1(1) R/W-0 HLVDL0(1) bit 0 BGVST W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) BGVST: Band Gap Reference Voltages Stable Status Flag bit 1 = Indicates internal band gap voltage references is stable 0 = Indicates internal band gap voltage reference is not stable IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled HLVDL<3:0>: Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting See Table 28-7 in Section 28.0 "Electrical Characteristics" for specifications. The VDIRMAG bit determines the overall operation of the module. When VDIRMAG is cleared, the module monitors for drops in VDD below a predetermined set point. When the bit is set, the module monitors for rises in VDD above the set point. bit 6 bit 5 bit 4 bit 3-0 Note 1: The module is enabled by setting the HLVDEN bit. Each time the module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit that indicates when the circuit is stable. The module can generate an interrupt only after the circuit is stable and IRVST is set. (c) 2009 Microchip Technology Inc. DS39932C-page 367 PIC18F46J11 FAMILY 23.1 Operation When the HLVD module is enabled, a comparator uses an internally generated reference voltage as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. The "trip point" voltage is the voltage level at which the device detects a high or low-voltage event, depending on the configuration of the module. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the LVDIF bit. The trip point voltage is software programmable to any one of 16 values. The trip point is selected by programming the HLVDL<3:0> bits (HLVDCON<3:0>). Additionally, the HLVD module allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits, HLVDL<3:0>, are set to `1111'. In this state, the comparator input is multiplexed from the external input pin, HLVDIN. This gives users flexibility because it allows them to configure the HLVD interrupt to occur at any voltage in the valid operating range. FIGURE 23-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL<3:0> HLVDCON Register VDIRMAG HLVDIN HLVDEN 16-to-1 MUX Set LVDIF HLVDEN Internal Voltage Reference 1.2V Typical DS39932C-page 368 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 23.2 1. 2. 3. HLVD Setup 23.4 HLVD Start-up Time To set up the HLVD module: Disable the module by clearing the HLVDEN bit (HLVDCON<4>). Write the value to the HLVDL<3:0> bits that selects the desired HLVD trip point. Set the VDIRMAG bit to detect one of the following: * High voltage (VDIRMAG = 1) * Low voltage (VDIRMAG = 0) Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD Interrupt Flag, LVDIF (PIR2<2>), which may have been set from a previous interrupt. If interrupts are desired, enable the HLVD interrupt by setting the HLVDIE and GIE/GIEH bits (PIE2<2> and INTCON<7>). An interrupt will not be generated until the IRVST bit is set. The internal reference voltage of the HLVD module, specified in electrical specification parameter D420 (see Table 28-7 in Section 28.0 "Electrical Characteristics"), may be used by other internal circuitry, such as the Programmable Brown-out Reset (BOR). If the HLVD or other circuits using the voltage reference are disabled to lower the device's current consumption, the reference voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. This start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical specification parameter 36 (Table 28-13). The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval. Refer to Figure 23-2 or Figure 23-3. 4. 5. 6. 23.3 Current Consumption When the module is enabled, the HLVD comparator and voltage divider are enabled and will consume static current. The total current consumption, when enabled, is specified in electrical specification parameter D022B (IHLVD) (Section 28.2 "DC Characteristics: PowerDown and Supply Current PIC18F46J50 Family (Industrial)"). Depending on the application, the HLVD module does not need to operate constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the HLVD module may be disabled. (c) 2009 Microchip Technology Inc. DS39932C-page 369 PIC18F46J11 FAMILY FIGURE 23-2: CASE 1: VDD VHLVD LVDIF Enable HLVD IRVST TIRVST Internal Reference is stable CASE 2: VDD VHLVD LVDIF Enable HLVD IRVST Internal Reference is stable LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since HLVD condition still exists TIRVST LVDIF cleared in software LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) LVDIF may not be set DS39932C-page 370 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 23-3: CASE 1: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) LVDIF may not be set VHLVD VDD LVDIF Enable HLVD IRVST TIRVST LVDIF cleared in software Internal Reference is stable CASE 2: VHLVD VDD LVDIF Enable HLVD IRVST Internal Reference is stable LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since HLVD condition still exists TIRVST 23.5 Applications FIGURE 23-4: In many applications, it is desirable to have the ability to detect a drop below, or rise above, a particular threshold. For general battery applications, Figure 23-4 provides a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an ISR, which would allow the application to perform "housekeeping tasks" and perform a controlled shutdown before the device voltage exits the valid operating range at TB. The HLVD, thus, would give the application a time window, represented by the difference between TA and TB, to safely exit. VA VB Voltage TYPICAL HIGH/ LOW-VOLTAGE DETECT APPLICATION Time TA TB Legend: VA = HLVD trip point VB = Minimum valid device operating voltage (c) 2009 Microchip Technology Inc. DS39932C-page 371 PIC18F46J11 FAMILY 23.6 Operation During Sleep 23.7 Effects of a Reset When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. TABLE 23-1: Name HLVDCON INTCON PIR2 PIE2 IPR2 REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Bit 7 Bit 6 BGVST CM1IF CM1IE CM1IP Bit 5 IRVST TMR0IE CM2IF CM2IE CM2IP Bit 4 HLVDEN INT0IE -- -- -- Bit 3 HLVDL3 RBIE BCLIF BCLIE BCLIP Bit 2 HLVDL2 TMR0IF LVDIF LVDIE LVDIP Bit 1 HLVDL1 INT0IF TMR3IF TMR3IE TMR3IP Bit 0 HLVDL0 RBIF CCP2IF CCP2IE CCP2IP Reset Values on page 66 63 65 65 65 VDIRMAG OSCFIF OSCFIE OSCFIP GIE/GIEH PEIE/GIEL Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the HLVD module. DS39932C-page 372 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 24.0 CHARGE TIME MEASUREMENT UNIT (CTMU) Control of response to edges Time measurement resolution of 1 nanosecond High precision time measurement Time delay of external or internal signal asynchronous to system clock * Accurate current source suitable for capacitive measurement The CTMU works in conjunction with the A/D Converter to provide up to 13 channels for time or charge measurement, depending on the specific device and the number of A/D channels available. When configured for time delay, the CTMU is connected to one of the analog comparators. The level-sensitive input edge sources can be selected from four sources: two external inputs or ECCP1/ECCP2 Special Event Triggers. Figure 24-1 provides a block diagram of the CTMU. * * * * The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. By working with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses with a specific time delay. The CTMU is ideal for interfacing with capacitive-based sensors. The module includes the following key features: * Up to 13 channels available for capacitive or time measurement input * On-chip precision current source * Four-edge input trigger sources * Polarity control for each edge source * Control of edge sequence FIGURE 24-1: CTMU BLOCK DIAGRAM CTMUCON EDGEN EDGSEQEN EDG1SELx EDG1POL EDG2SELx EDG2POL CTMUICON ITRIM<5:0> IRNG<1:0> EDG1STAT EDG2STAT TGEN IDISSEN Current Source CTEDG1 CTEDG2 Edge Control Logic Current Control CTMU Control Logic ECCP2 ECCP1 A/D Converter Comparator 2 Input Pulse Generator CTPLS Comparator 2 Output (c) 2009 Microchip Technology Inc. DS39932C-page 373 PIC18F46J11 FAMILY 24.1 CTMU Operation The CTMU works by using a fixed current source to charge a circuit. The type of circuit depends on the type of measurement being made. In the case of charge measurement, the current is fixed, and the amount of time the current is applied to the circuit is fixed. The amount of voltage read by the A/D is then a measurement of the capacitance of the circuit. In the case of time measurement, the current, as well as the capacitance of the circuit, is fixed. In this case, the voltage read by the A/D is then representative of the amount of time elapsed from the time the current source starts and stops charging the circuit. If the CTMU is being used as a time delay, both capacitance and current source are fixed, as well as the voltage supplied to the comparator circuit. The delay of a signal is determined by the amount of time it takes the voltage to charge to the comparator threshold voltage. Current trim is provided by the ITRIM<5:0> bits (CTMUICON<7:2>). These six bits allow trimming of the current source in steps of approximately 2% per step. Note that half of the range adjusts the current source positively and the other half reduces the current source. A value of `000000' is the neutral position (no change). A value of `100000' is the maximum negative adjustment (approximately -62%) and `011111' is the maximum positive adjustment (approximately +62%). 24.1.3 EDGE SELECTION AND CONTROL 24.1.1 THEORY OF OPERATION CTMU measurements are controlled by edge events occurring on the module's two input channels. Each channel, referred to as Edge 1 and Edge 2, can be configured to receive input pulses from one of the edge input pins (CTEDG1 and CTEDG2) or ECCPx Special Event Triggers. The input channels are level-sensitive, responding to the instantaneous level on the channel rather than a transition between levels. The inputs are selected using the EDG1SEL and EDG2SEL bit pairs (CTMUCONL<3:2 and 6:5>). In addition to source, each channel can be configured for event polarity using the EDGE2POL and EDGE1POL bits (CTMUCONL<7,4>). The input channels can also be filtered for an edge event sequence (Edge 1 occurring before Edge 2) by setting the EDGSEQEN bit (CTMUCONH<2>). The operation of the CTMU is based on the equation for charge: dV C = I -----dT More simply, the amount of charge measured in coulombs in a circuit is defined as current in amperes (I) multiplied by the amount of time in seconds that the current flows (t). Charge is also defined as the capacitance in farads (C) multiplied by the voltage of the circuit (V). It follows that: I t = C V. The CTMU module provides a constant, known current source. The A/D Converter is used to measure (V) in the equation, leaving two unknowns: capacitance (C) and time (t). The above equation can be used to calculate capacitance or time, by either the relationship using the known fixed capacitance of the circuit: t = (C V) I or by: C = (I t) V using a fixed time that the current source is applied to the circuit. 24.1.4 EDGE STATUS The CTMUCON register also contains two status bits: EDG2STAT and EDG1STAT (CTMUCONL<1:0>). Their primary function is to show if an edge response has occurred on the corresponding channel. The CTMU automatically sets a particular bit when an edge response is detected on its channel. The level-sensitive nature of the input channels also means that the status bits become set immediately if the channel's configuration is changed and is the same as the channel's current state. The module uses the edge status bits to control the current source output to external analog modules (such as the A/D Converter). Current is only supplied to external modules when only one (but not both) of the status bits is set, and shuts current off when both bits are either set or cleared. This allows the CTMU to measure current only during the interval between edges. After both status bits are set, it is necessary to clear them before another measurement is taken. Both bits should be cleared simultaneously, if possible, to avoid re-enabling the CTMU current source. In addition to being set by the CTMU hardware, the edge status bits can also be set by software. This is also the user's application to manually enable or disable the current source. Setting either one (but not both) of the bits enables the current source. Setting or clearing both bits at once disables the source. 24.1.2 CURRENT SOURCE At the heart of the CTMU is a precision current source, designed to provide a constant reference for measurements. The level of current is user-selectable across three ranges or a total of two orders of magnitude, with the ability to trim the output in 2% increments (nominal). The current range is selected by the IRNG<1:0> bits (CTMUICON<9:8>), with a value of `00' representing the lowest range. DS39932C-page 374 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 24.1.5 INTERRUPTS The CTMU sets its interrupt flag (PIR3<2>) whenever the current source is enabled, then disabled. An interrupt is generated only if the corresponding interrupt enable bit (PIE3<2>) is also set. If edge sequencing is not enabled (i.e., Edge 1 must occur before Edge 2), it is necessary to monitor the edge status bits and determine which edge occurred last and caused the interrupt. Depending on the type of measurement or pulse generation being performed, one or more additional modules may also need to be initialized and configured with the CTMU module: * Edge Source Generation: In addition to the external edge input pins, both Timer1 and the Output Compare/PWM1 module can be used as edge sources for the CTMU. * Capacitance or Time Measurement: The CTMU module uses the A/D Converter to measure the voltage across a capacitor that is connected to one of the analog input channels. * Pulse Generation: When generating system clock independent output pulses, the CTMU module uses Comparator 2 and the associated comparator voltage reference. 24.2 CTMU Module Initialization The following sequence is a general guideline used to initialize the CTMU module: 1. Select the current source range using the IRNG bits (CTMUICON<1:0>). 2. Adjust the current source trim using the ITRIM bits (CTMUICON<7:2>). 3. Configure the edge input sources for Edge 1 and Edge 2 by setting the EDG1SEL and EDG2SEL bits (CTMUCONL<3:2 and 6:5>). 4. Configure the input polarities for the edge inputs using the EDG1POL and EDG2POL bits (CTMUCONL<4,7>). The default configuration is for negative edge polarity (high-to-low transitions). 5. Enable edge sequencing using the EDGSEQEN bit (CTMUCONH<2>). By default, edge sequencing is disabled. 6. Select the operating mode (Measurement or Time Delay) with the TGEN bit. The default mode is Time/Capacitance Measurement. 7. Discharge the connected circuit by setting the IDISSEN bit (CTMUCONH<1>); after waiting a sufficient time for the circuit to discharge, clear IDISSEN. 8. Disable the module by clearing the CTMUEN bit (CTMUCONH<7>). 9. Enable the module by setting the CTMUEN bit. 10. Clear the Edge Status bits: EDG2STAT and EDG1STAT (CTMUCONL<1:0>). 11. Enable both edge inputs by setting the EDGEN bit (CTMUCONH<3>). 24.3 Calibrating the CTMU Module The CTMU requires calibration for precise measurements of capacitance and time, as well as for accurate time delay. If the application only requires measurement of a relative change in capacitance or time, calibration is usually not necessary. An example of this type of application would include a capacitive touch switch, in which the touch circuit has a baseline capacitance, and the added capacitance of the human body changes the overall capacitance of a circuit. If actual capacitance or time measurement is required, two hardware calibrations must take place: the current source needs calibration to set it to a precise current, and the circuit being measured needs calibration to measure and/or nullify all other capacitance other than that to be measured. 24.3.1 CURRENT SOURCE CALIBRATION The current source on board the CTMU module has a range of 60% nominal for each of three current ranges. Therefore, for precise measurements, it is possible to measure and adjust this current source by placing a high precision resistor, RCAL, onto an unused analog channel. An example circuit is shown in Figure 24-2. The current source measurement is performed using the following steps: 1. 2. 3. 4. 5. 6. Initialize the A/D Converter. Initialize the CTMU. Enable the current source by setting EDG1STAT (CTMUCONL<0>). Issue settling time delay. Perform A/D conversion. Calculate the current source current using I = V/ RCAL, where RCAL is a high precision resistance and V is measured by performing an A/D conversion. (c) 2009 Microchip Technology Inc. DS39932C-page 375 PIC18F46J11 FAMILY The CTMU current source may be trimmed with the trim bits in CTMUICON using an iterative process to get an exact desired current. Alternatively, the nominal value without adjustment may be used; it may be stored by the software for use in all subsequent capacitive or time measurements. To calculate the value for RCAL, the nominal current must be chosen, and then the resistance can be calculated. For example, if the A/D Converter reference voltage is 3.3V, use 70% of full scale, or 2.31V as the desired approximate voltage to be read by the A/D Converter. If the range of the CTMU current source is selected to be 0.55 A, the resistor value needed is calculated as RCAL = 2.31V/0.55 A, for a value of 4.2 M. Similarly, if the current source is chosen to be 5.5 A, RCAL would be 420,000, and 42,000 if the current source is set to 55 A. A value of 70% of full-scale voltage is chosen to make sure that the A/D Converter was in a range that is well above the noise floor. Keep in mind that if an exact current is chosen, that is to incorporate the trimming bits from CTMUICON, the resistor value of RCAL may need to be adjusted accordingly. RCAL may also be adjusted to allow for available resistor values. RCAL should be of the highest precision available, keeping in mind the amount of precision needed for the circuit that the CTMU will be used to measure. A recommended minimum would be 0.1% tolerance. The following examples show one typical method for performing a CTMU current calibration. Example 24-1 demonstrates how to initialize the A/D Converter and the CTMU; this routine is typical for applications using both modules. Example 24-2 demonstrates one method for the actual calibration routine. FIGURE 24-2: CTMU CURRENT SOURCE CALIBRATION CIRCUIT PIC18F46J11 Device Current Source CTMU A/D Converter ANx RCAL A/D MUX DS39932C-page 376 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY EXAMPLE 24-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.h" /**************************************************************************/ /*Setup CTMU *****************************************************************/ /**************************************************************************/ void setup(void) { //CTMUCON - CTMU Control register CTMUCONH = 0x00; //make sure CTMU is disabled CTMUCONL = 0x90; //CTMU continues to run when emulator is stopped,CTMU continues //to run in idle mode,Time Generation mode disabled, Edges are blocked //No edge sequence order, Analog current source not grounded, trigger //output disabled, Edge2 polarity = positive level, Edge2 source = //source 0, Edge1 polarity = positive level, Edge1 source = source 0, //CTMUICON - CTMU Current Control Register CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment /**************************************************************************/ //Setup AD converter; /**************************************************************************/ TRISA=0x04; //set channel 2 as an input // Configured AN2 as an analog channel // ANCON0 ANCON0 = 0XFB; // ANCON1 ANCON1 = 0X1F; // ADCON1 ADCON1bits.ADFM=1; ADCON1bits.ADCAL=0; ADCON1bits.ACQT=1; ADCON1bits.ADCS=2; // // // // Resulst format 1= Right justified Normal A/D conversion operation Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD Clock conversion bits 6= FOSC/64 2=FOSC/32 ANCON1bits.VBGEN=1; // ADCON0 ADCON0bits.VCFG0 =0; ADCON0bits.VCFG1 =0; ADCON0bits.CHS=2; ADCON0bits.ADON=1; } // Turn on the Bandgap needed for Rev A0 parts // Vref+ = AVdd // Vref- = AVss // Select ADC channel // Turn on ADC (c) 2009 Microchip Technology Inc. DS39932C-page 377 PIC18F46J11 FAMILY EXAMPLE 24-2: CURRENT CALIBRATION ROUTINE //@ 8MHz = 125uS. //R value is 4200000 (4.2M) //scaled so that result is in //1/100th of uA //for unsigned conversion 10 sig bits //Vdd connected to A/D Vr+ #include "p18cxxx.h" #define COUNT 500 #define DELAY for(i=0;i //index for loop //float values stored for calcs //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; CTMUCONLbits.EDG1STAT = 0; CTMUCONLbits.EDG2STAT = 0; for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; DELAY; CTMUCONHbits.IDISSEN = 0; CTMUCONLbits.EDG1STAT = 1; DELAY; CTMUCONLbits.EDG1STAT = 0; PIR1bits.ADIF = 0; ADCON0bits.GO=1; while(!PIR1bits.ADIF); Vread = ADRES; PIR1bits.ADIF = 0; VTot += Vread; } Vavg = (float)(VTot/10.000); Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; } //Average of 10 readings //CTMUISrc is in 1/100ths of uA //Enable the CTMU // Set Edge status bits to zero //drain charge on the circuit //wait 125us //end drain of circuit //Begin charging the circuit //using CTMU current source //wait for 125us //Stop charging circuit //make sure A/D Int not set //and begin A/D conv. //Wait for A/D convert complete //Get the value from the A/D //Clear A/D Interrupt Flag //Add the reading to the total DS39932C-page 378 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 24.3.2 CAPACITANCE CALIBRATION There is a small amount of capacitance from the internal A/D Converter sample capacitor as well as stray capacitance from the circuit board traces and pads that affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by making sure the desired capacitance to be measured has been removed. The measurement is then performed using the following steps: 1. 2. 3. 4. 5. 6. Initialize the A/D Converter and the CTMU. Set EDG1STAT (= 1). Wait for a fixed delay of time t. Clear EDG1STAT. Perform an A/D conversion. Calculate the stray and A/D sample capacitances: C OFFSET = C STRAY + CAD = ( I t ) V where I is known from the current source measurement step, t is a fixed delay and V is measured by performing an A/D conversion. This measured value is then stored and used for calculations of time measurement or subtracted for capacitance measurement. For calibration, it is expected that the capacitance of CSTRAY + CAD is approximately known. CAD is approximately 4 pF. An iterative process may need to be used to adjust the time, t, that the circuit is charged to obtain a reasonable voltage reading from the A/D Converter. The value of t may be determined by setting COFFSET to a theoretical value, then solving for t. For example, if CSTRAY is theoretically calculated to be 11 pF, and V is expected to be 70% of VDD, or 2.31V, then t would be: (4 pF + 11 pF) * 2.31V/0.55 A or 63 s. See Example 24-3 for a typical routine for CTMU capacitance calibration. (c) 2009 Microchip Technology Inc. DS39932C-page 379 PIC18F46J11 FAMILY EXAMPLE 24-3: CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define #define #define #define bits #define #define COUNT 25 ETIME COUNT*2.5 DELAY for(i=0;i //drain charge on the circuit //wait 125us //end drain of circuit //Begin charging the circuit //using CTMU current source //wait for 125us //Stop charging circuit //make sure A/D Int not set //and begin A/D conv. //Wait for A/D convert complete Vread = ADRES; PIR1bits.ADIF = 0; VTot += Vread; } Vavg = (float)(VTot/10.000); Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; CTMUCap = (CTMUISrc*ETIME/Vcal)/100; } //Get the value from the A/D //Clear A/D Interrupt Flag //Add the reading to the total //Average of 10 readings //CTMUISrc is in 1/100ths of uA DS39932C-page 380 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 24.4 Measuring Capacitance with the CTMU 24.4.2 RELATIVE CHARGE MEASUREMENT An application may not require precise capacitance measurements. For example, when detecting a valid press of a capacitance-based switch, detecting a relative change of capacitance is of interest. In this type of application, when the switch is open (or not touched), the total capacitance is the capacitance of the combination of the board traces, the A/D Converter, etc. A larger voltage will be measured by the A/D Converter. When the switch is closed (or is touched), the total capacitance is larger due to the addition of the capacitance of the human body to the above listed capacitances, and a smaller voltage will be measured by the A/D Converter. Detecting capacitance changes is easily accomplished with the CTMU using these steps: 1. 2. 3. 4. 5. Initialize the A/D Converter and the CTMU. Set EDG1STAT. Wait for a fixed delay. Clear EDG1STAT. Perform an A/D conversion. There are two separate methods of measuring capacitance with the CTMU. The first is the absolute method, in which the actual capacitance value is desired. The second is the relative method, in which the actual capacitance is not needed, rather an indication of a change in capacitance is required. 24.4.1 ABSOLUTE CAPACITANCE MEASUREMENT For absolute capacitance measurements, both the current and capacitance calibration steps found in Section 24.3 "Calibrating the CTMU Module" should be followed. Capacitance measurements are then performed using the following steps: 1. 2. 3. 4. 5. 6. 7. Initialize the A/D Converter. Initialize the CTMU. Set EDG1STAT. Wait for a fixed delay, T. Clear EDG1STAT. Perform an A/D conversion. Calculate the total capacitance, CTOTAL = (I * T)/V, where I is known from the current source measurement step (see Section 24.3.1 "Current Source Calibration"), T is a fixed delay and V is measured by performing an A/D conversion. Subtract the stray and A/D capacitance (COFFSET from Section 24.3.2 "Capacitance Calibration") from CTOTAL to determine the measured capacitance. 8. The voltage measured by performing the A/D conversion is an indication of the relative capacitance. Note that in this case, no calibration of the current source or circuit capacitance measurement is needed. See Example 24-4 for a sample software routine for a capacitive touch switch. (c) 2009 Microchip Technology Inc. DS39932C-page 381 PIC18F46J11 FAMILY EXAMPLE 24-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define #define #define #define COUNT 500 DELAY for(i=0;i //storage for reading //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; CTMUCONLbits.EDG1STAT = 0; CTMUCONLbits.EDG2STAT = 0; CTMUCONHbits.IDISSEN = 1; DELAY; CTMUCONHbits.IDISSEN = 0; CTMUCONLbits.EDG1STAT = 1; DELAY; CTMUCONLbits.EDG1STAT = 0; PIR1bits.ADIF = 0; ADCON0bits.GO=1; while(!PIR1bits.ADIF); Vread = ADRES; // Enable the CTMU // Set Edge status bits to zero //drain charge on the circuit //wait 125us //end drain of circuit //Begin charging the circuit //using CTMU current source //wait for 125us //Stop charging circuit //make sure A/D Int not set //and begin A/D conv. //Wait for A/D convert complete //Get the value from the A/D if(Vread < OPENSW - TRIP) { switchState = PRESSED; } else if(Vread > OPENSW - TRIP + HYST) { switchState = UNPRESSED; } } DS39932C-page 382 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 24.5 Measuring Time with the CTMU Module It is assumed that the time measured is small enough that the capacitance, COFFSET, provides a valid voltage to the A/D Converter. For the smallest time measurement, always set the A/D Channel Select register (AD1CHS) to an unused A/D channel; the corresponding pin for which is not connected to any circuit board trace. This minimizes added stray capacitance, keeping the total circuit capacitance close to that of the A/D Converter itself (4-5 pF). To measure longer time intervals, an external capacitor may be connected to an A/D channel and this channel selected when making a time measurement. Time can be precisely measured after the ratio (C/I) is measured from the current and capacitance calibration step by following these steps: 1. 2. 3. 4. 5. Initialize the A/D Converter and the CTMU. Set EDG1STAT. Set EDG2STAT. Perform an A/D conversion. Calculate the time between edges as T = (C/I) * V, where I is calculated in the current calibration step (Section 24.3.1 "Current Source Calibration"), C is calculated in the capacitance calibration step (Section 24.3.2 "Capacitance Calibration") and V is measured by performing the A/D conversion. FIGURE 24-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC18F46J11 Device CTMU CTEDG1 CTEDG2 EDG1 EDG2 Output Pulse A/D Converter CAD RPR Current Source ANX (c) 2009 Microchip Technology Inc. DS39932C-page 383 PIC18F46J11 FAMILY 24.6 Creating a Delay with the CTMU Module An example use of this feature is for interfacing with variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the pulse width output on CTPLS will vary. The CTPLS output pin can be connected to an input capture pin and the varying pulse width is measured to determine the humidity in the application. Follow these steps to use this feature: 1. 2. 3. 4. 5. Initialize Comparator 2. Initialize the comparator voltage reference. Initialize the CTMU and enable time delay generation by setting the TGEN bit. Set EDG1STAT. When CPULSE charges to the value of the voltage reference trip point, an output pulse is generated on CTPLS. A unique feature on board the CTMU module is its ability to generate system clock independent output pulses based on an external capacitor value. This is accomplished using the internal comparator voltage reference module, Comparator 2 input pin and an external capacitor. The pulse is output onto the CTPLS pin. To enable this mode, set the TGEN bit. See Figure 24-4 for an example circuit. CPULSE is chosen by the user to determine the output pulse width on CTPLS. The pulse width is calculated by T = (CPULSE/I)*V, where I is known from the current source measurement step (Section 24.3.1 "Current Source Calibration") and V is the internal reference voltage (CVREF). FIGURE 24-4: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC18F46J11 Device CTEDG1 EDG1 CTMU CTPLS Current Source Comparator C2INB C2 CPULSE CVREF 24.7 24.7.1 Operation During Sleep/Idle Modes SLEEP MODE AND DEEP SLEEP MODES module is performing an operation when Idle mode is invoked, in this case, the results will be similar to those with Sleep mode. 24.8 Effects of a Reset on CTMU When the device enters any Sleep mode, the CTMU module current source is always disabled. If the CTMU is performing an operation that depends on the current source when Sleep mode is invoked, the operation may not terminate correctly. Capacitance and time measurements may return erroneous values. Upon Reset, all registers of the CTMU are cleared. This leaves the CTMU module disabled, its current source is turned off and all configuration options return to their default settings. The module needs to be re-initialized following any Reset. If the CTMU is in the process of taking a measurement at the time of Reset, the measurement will be lost. A partial charge may exist on the circuit that was being measured, and should be properly discharged before the CTMU makes subsequent attempts to make a measurement. The circuit is discharged by setting and then clearing the IDISSEN bit (CTMUCONH<1>) while the A/D Converter is connected to the appropriate channel. 24.7.2 IDLE MODE The behavior of the CTMU in Idle mode is determined by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL is cleared, the module will continue to operate in Idle mode. If CTMUSIDL is set, the module's current source is disabled when the device enters Idle mode. If the DS39932C-page 384 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 24.9 Registers There are three control registers for the CTMU: * CTMUCONH * CTMUCONL * CTMUICON The CTMUCONH and CTMUCONL registers (Register 24-1 and Register 24-2) contain control bits for configuring the CTMU module edge source selection, edge source polarity selection, edge sequencing, A/D trigger, analog circuit capacitor discharge and enables. The CTMUICON register (Register 24-3) has bits for selecting the current source range and current source trim. REGISTER 24-1: R/W-0 CTMUEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 CTMUCONH: CTMU CONTROL REGISTER HIGH (ACCESS FB3h) U-0 -- R/W-0 CTMUSIDL R/W-0 TGEN R/W-0 EDGEN R/W-0 EDGSEQEN R/W-0 IDISSEN U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as `0' CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded Reserved: Write as `0' bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2009 Microchip Technology Inc. DS39932C-page 385 PIC18F46J11 FAMILY REGISTER 24-2: R/W-0 EDG2POL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CTMUCONL: CTMU CONTROL REGISTER LOW (ACCESS FB2h) R/W-0 EDG2SEL0 R/W-0 EDG1POL R/W-0 EDG1SEL1 R/W-0 EDG1SEL0 R/W-0 EDG2STAT R/W-0 EDG1STAT bit 0 R/W-0 EDG2SEL1 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTEDG1 pin 10 = CTEDG2 pin 01 = ECCP1 Special Event Trigger 00 = ECCP2 Special Event Trigger EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTEDG1 pin 10 = CTEDG2 pin 01 = ECCP1 Special Event Trigger 00 = ECCP2 Special Event Trigger EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred bit 6-5 bit 4 bit 3-2 bit 1 bit 0 DS39932C-page 386 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 24-3: R/W-0 ITRIM5 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CTMUICON: CTMU CURRENT CONTROL REGISTER (ACCESS FB1h) R/W-0 ITRIM3 R/W-0 ITRIM2 R/W-0 ITRIM1 R/W-0 ITRIM0 R/W-0 IRNG1 R/W-0 IRNG0 bit 0 R/W-0 ITRIM4 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current IRNG<1:0>: Current Source Range Select bits 11 = 100 x Base current 10 = 10 x Base current 01 = Base current level (0.55 A nominal) 00 = Current source disabled bit 1-0 TABLE 24-1: Name CTMUCONH CTMUICON Legend: REGISTERS ASSOCIATED WITH CTMU MODULE Bit 7 Bit 6 -- EDG2SEL1 ITRIM4 Bit 5 CTMUSIDL EDG2SEL0 ITRIM3 Bit 4 TGEN EDG1POL ITRIM2 Bit 3 EDGEN EDG1SEL1 ITRIM1 Bit 2 EDGSEQEN ITRIM0 Bit 1 IDISSEN IRNG1 Bit 0 -- IRNG0 Reset Values on page: 65 65 65 CTMUEN ITRIM5 CTMUCONL EDG2POL EDG1SEL0 EDG2STAT EDG1STAT -- = unimplemented, read as `0'. Shaded cells are not used during ECCP operation. (c) 2009 Microchip Technology Inc. DS39932C-page 387 PIC18F46J11 FAMILY NOTES: DS39932C-page 388 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 25.0 SPECIAL FEATURES OF THE CPU 25.1.1 CONSIDERATIONS FOR CONFIGURING THE PIC18F46J11 FAMILY DEVICES PIC18F46J11 family devices include several features intended to maximize reliability and minimize cost through elimination of external components. These are: * Oscillator Selection * Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Fail-Safe Clock Monitor (FSCM) * Two-Speed Start-up * Code Protection * In-Circuit Serial Programming (ICSP) The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 2.0 "Oscillator Configurations". A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, the PIC18F46J11 family of devices have a configurable Watchdog Timer (WDT), which is controlled in software. The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. Two-Speed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits. Unlike some previous PIC18 microcontrollers, devices of the PIC18F46J11 family do not use persistent memory registers to store configuration information. The Configuration registers, CONFIG1L through CONFIG4H, are implemented as volatile memory. Immediately after power-up, or after a device Reset, the microcontroller hardware automatically loads the CONFIG1L through CONFIG4L registers with configuration data stored in nonvolatile Flash program memory. The last four words of Flash program memory, known as the Flash Configuration Words (FCW), are used to store the configuration data. Table 25-1 provides the Flash program memory, which will be loaded into the corresponding Configuration register. When creating applications for these devices, users should always specifically allocate the location of the FCW for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The four Most Significant bits (MSb) of the FCW corresponding to CONFIG1H, CONFIG2H, CONFIG3H and CONFIG4H should always be programmed to `1111'. This makes these FCWs appear to be NOP instructions in the remote event that their locations are ever executed by accident. To prevent inadvertent configuration changes during code execution, the Configuration registers, CONFIG1L through CONFIG4L, are loaded only once per power-up or Reset cycle. User's firmware can still change the configuration by using self-reprogramming to modify the contents of the FCW. Modifying the FCW will not change the active contents being used in the CONFIG1L through CONFIG4H registers until after the device is reset. 25.1 Configuration Bits The Configuration bits can be programmed to select various device configurations. The configuration data is stored in the last four words of Flash program memory; Figure 5-1 depicts this. The configuration data gets loaded into the volatile Configuration registers, CONFIG1L through CONFIG4H, which are readable and mapped to program memory starting at location 300000h. Table 25-2 provides a complete list. A detailed explanation of the various bit functions is provided in Register 25-1 through Register 25-6. (c) 2009 Microchip Technology Inc. DS39932C-page 389 PIC18F46J11 FAMILY TABLE 25-1: MAPPING OF THE FLASH CONFIGURATION WORDS TO THE CONFIGURATION REGISTERS Configuration Register Address 300000h 300001h 300002h 300003h 300004h 300005h 300006h 300007h Flash Configuration Byte Address XXXF8h XXXF9h XXXFAh XXXFBh XXXFCh XXXFDh XXXFEh XXXFFh Configuration Register (Volatile) CONFIG1L CONFIG1H CONFIG2L CONFIG2H CONFIG3L CONFIG3H CONFIG4L CONFIG4H TABLE 25-2: File Name CONFIGURATION BITS AND DEVICE IDs Bit 7 DEBUG --(2) IESO --(2) --(2) WPCFG --(2) DEV2 DEV10 Bit 6 XINST --(2) FCMEN --(2) --(2) WPEND --(2) DEV1 DEV9 Bit 5 STVREN --(2) -- --(2) --(2) WPFP5 --(2) DEV0 DEV8 Bit 4 -- --(2) LPT1OSC --(2) --(2) WPFP4 --(2) REV4 DEV7 Bit 3 -- -- T1DIG WDTPS3 MSSPMSK WPFP3 -- REV3 DEV6 Bit 2 -- CP0 FOSC2 WDTPS2 -- WPFP2 -- REV2 DEV5 Bit 1 -- -- FOSC1 WDTPS1 -- WPFP1 -- REV1 DEV4 Bit 0 WDTEN -- FOSC0 WDTPS0 IOL1WAY WPFP0 WPDIS REV0 DEV3 Default/ Unprog. Value(1) 111- ---1 1111 -1-11-1 1111 1111 1111 1111 1--1 1111 1111 1111 ---1 xxx0 0000(3) 0100 00xx(3) 300000h CONFIG1L 300001h CONFIG1H 300002h CONFIG2L 300003h CONFIG2H 300005h CONFIG3H 300006h CONFIG4L 300007h CONFIG4H 3FFFFEh DEVID1 3FFFFFh DEVID2 Legend: Note 1: 2: 3: 300004h CONFIG3L DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 DSWDTEN DSBOREN RTCOSC DSWDTOSC 1111 1111 x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as `0'. Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the configuration bytes maintain their previously programmed states. The value of these bits in program memory should always be programmed to `1'. This ensures that the location is executed as a NOP if it is accidentally executed. See Register 25-9 and Register 25-10 for DEVID values. These registers are read-only and cannot be programmed by the user. DS39932C-page 390 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 25-1: R/WO-1 DEBUG bit 7 Legend: R = Readable bit -n = Value at Reset bit 7 WO = Write-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 STVREN U-0 -- U-1 -- U-1 -- U-1 -- R/WO-1 WDTEN bit 0 XINST R/WO-1 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled Unimplemented: Read as `0' WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) bit 6 bit 5 bit 4-1 bit 0 (c) 2009 Microchip Technology Inc. DS39932C-page 391 PIC18F46J11 FAMILY REGISTER 25-2: U-1 -- bit 7 Legend: R = Readable bit -n = Value at Reset bit 7-4 bit 3 bit 2 WO = Write-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-1 -- U-1 -- U-1 -- U-0 -- R/WO-1 CP0 U-0 -- U-0 -- bit 0 Unimplemented: Program the corresponding Flash Configuration bit to `1' Unimplemented: Maintain as `0' CP0: Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is code-protected Unimplemented: Maintain as `0' bit 1-0 DS39932C-page 392 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 25-3: R/WO-1 IESO bit 7 Legend: R = Readable bit -n = Value at Reset bit 7 WO = Write-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 -- R/WO-1 LPT1OSC R/WO-1 T1DIG R/WO-1 FOSC2 R/WO-1 FOSC1 R/WO-1 FOSC0 bit 0 R/WO-1 FCMEN IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up disabled FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled Unimplemented: Read as `0' LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 oscillator configured for high-power operation 0 = Timer1 oscillator configured for low-power operation T1DIG: Secondary Clock Source T1OSCEN Enforcement bit 1 = Secondary oscillator clock source may be selected (OSCCON<1:0> = 01) regardless of the T1OSCEN (T1CON<3>) state 0 = Secondary oscillator clock source may not be selected unless T1CON<3> = 1 FOSC<2:0>: Oscillator Selection bits 111 = ECPLL oscillator with PLL software controlled, CLKO on RA6 110 = EC oscillator with CLKO on RA6 101 = HSPLL oscillator with PLL software controlled 100 = HS oscillator 011 = INTOSCPLLO, internal oscillator with PLL software controlled, CLKO on RA6, port function on RA7 010 = INTOSCPLL, internal oscillator with PLL software controlled, port function on RA6 and RA7 001 = INTOSCO internal oscillator block (INTRC/INTOSC) with CLKO on RA6, port function on RA7 000 = INTOSC internal oscillator block (INTRC/INTOSC), port function on RA6 and RA7 bit 6 bit 5 bit 4 bit 3 bit 2-0 (c) 2009 Microchip Technology Inc. DS39932C-page 393 PIC18F46J11 FAMILY REGISTER 25-4: U-1 -- bit 7 Legend: R = Readable bit -n = Value at Reset bit 7-4 bit 3-0 WO = Write-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-1 -- U-1 -- U-1 -- R/WO-1 WDTPS3 R/WO-1 WDTPS2 R/WO-1 WDTPS1 R/WO-1 WDTPS0 bit 0 Unimplemented: Program the corresponding Flash Configuration bit to `1' WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 DS39932C-page 394 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 25-5: R/WO-1 DSWDTPS3 bit 7 Legend: R = Readable bit -n = Value at Reset bit 7-4 WO = Write-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown (1) CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 bit 0 DSWDTPS2(1) DSWDTPS1(1) DSWDTPS0(1) DSWDTEN(1) DSBOREN(1) RTCOSC DSWDTOSC(1) DSWDTPS<3:0>: Deep Sleep Watchdog Timer Postscale Select bits(1) The DSWDT prescaler is 32. This creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) 1110 = 1:536,870,912 (6.4 days) 1101 = 1:134,217,728 (38.5 hours) 1100 = 1:33,554,432 (9.6 hours) 1011 = 1:8,388,608 (2.4 hours) 1010 = 1:2,097,152 (36 minutes) 1001 = 1:524,288 (9 minutes) 1000 = 1:131,072 (135 seconds) 0111 = 1:32,768 (34 seconds) 0110 = 1:8,192 (8.5 seconds) 0101 = 1:2,048 (2.1 seconds) 0100 = 1:512 (528 ms) 0011 = 1:128 (132 ms) 0010 = 1:32 (33 ms) 0001 = 1:8 (8.3 ms) 0000 = 1:2 (2.1 ms) DSWDTEN: Deep Sleep Watchdog Timer Enable bit(1) 1 = DSWDT enabled 0 = DSWDT disabled DSBOREN: Deep Sleep BOR Enable bit(1) 1 = BOR enabled in Deep Sleep (when using PIC18FXXJXX device) 0 = BOR disabled in Deep Sleep (does not affect operation in non Deep Sleep modes) RTCOSC: RTCC Reference Clock Select bit 1 = RTCC uses T1OSC/T1CKI as reference clock 0 = RTCC uses INTRC as reference clock DSWDTOSC: DSWDT Reference Clock Select bit(1) 1 = DSWDT uses INTRC as reference clock 0 = DSWDT uses T1OSC/T1CKI as reference clock Deep Sleep bits are not available on "LF" devices. bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2009 Microchip Technology Inc. DS39932C-page 395 PIC18F46J11 FAMILY REGISTER 25-6: U-1 -- bit 7 Legend: R = Readable bit -n = Value at Reset bit 7-4 bit 3 WO = Write-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-1 -- U-1 -- U-1 -- R/WO-1 MSSPMSK U-0 -- U-0 -- R/WO-1 IOL1WAY bit 0 Unimplemented: Program the corresponding Flash Configuration bit to `1' MSSPMSK: MSSP 7-Bit Address Masking Mode Enable bit 1 = 7-Bit Address Masking mode enabled 0 = 5-Bit Address Masking mode enabled Unimplemented: Read as `0' IOL1WAY: IOLOCK One-Way Set Enable bit 1 = IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the unlock sequence has been completed bit 2-1 bit 0 REGISTER 25-7: R/WO-1 WPCFG bit 7 Legend: R = Readable bit -n = Value at Reset bit 7 CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/WO-1 WPFP5(2) R/WO-1 WPFP4(3) R/WO-1 WPFP3 R/WO-1 WPFP2 R/WO-1 WPFP1 R/WO-1 WPFP0 bit 0 R/WO-1 WPEND WO = Write-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown WPCFG: Write/Erase Protect Configuration Region Select bit (valid when WPDIS = 0) 1 = Configuration Words page is not erase/write-protected, regardless of WPEND and WPFP<5:0> settings(1) 0 = Configuration Words page is erase/write-protected, regardless of WPEND and WPFP<5:0>(1) WPEND: Write/Erase Protect Region Select bit (valid when WPDIS = 0) 1 = Flash pages WPFP<5:0> to (Configuration Words page) are write/erase protected 0 = Flash pages 0 to WPFP<5:0> are erase/write-protected WPFP<5:0>: Write/Erase Protect Page Start/End Location bits(2,3) Used with WPEND bit to define which pages in Flash will be erase/write-protected. The "Configuration Words page" contains the FCWs and is the last page of implemented Flash memory on a given device. Each page consists of 1,024 bytes. For example, on a device with 64 Kbytes of Flash, the first page is 0 and the last page (Configuration Words page) is 63 (3Fh). Not available on 32K devices. Not available on 32K and 16K devices. bit 6 bit 5-0 Note 1: 2: 3: DS39932C-page 396 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY REGISTER 25-8: U-1 -- bit 7 Legend: R = Readable bit -n = Value at Reset bit 7-4 bit 3-1 bit 0 WO = Write-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CONFIG4H: CONFIGURATION REGISTER 4 HIGH (BYTE ADDRESS 300007h) U-1 -- U-1 -- U-1 -- U-0 -- U-0 -- U-0 -- R/WO-1 WPDIS bit 0 Unimplemented: Program the corresponding Flash Configuration bit to `1' Unimplemented: Read as `0' WPDIS: Write-Protect Disable bit 1 = WPFP<5:0>, WPEND and WPCFG bits ignored; all Flash memory may be erased or written 0 = WPFP<5:0>, WPEND and WPCFG bits enabled; erase/write-protect active for the selected region(s) REGISTER 25-9: R DEV2 bit 7 Legend: R = Readable bit -n = Value at Reset bit 7-5 DEVID1: DEVICE ID REGISTER 1 FOR PIC18F46J11 FAMILY DEVICES (BYTE ADDRESS 3FFFFEh) R DEV1 R DEV0 R REV4 R REV3 R REV2 R REV1 R REV0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DEV<2:0>: Device ID bits These bits are used with DEV<10:3> bits in Device ID Register 2 to identify the part number. See Register 25-10. REV<4:0>: Revision ID bits These bits are used to indicate the device revision. bit 4-0 (c) 2009 Microchip Technology Inc. DS39932C-page 397 PIC18F46J11 FAMILY REGISTER 25-10: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F46J11 FAMILY DEVICES (BYTE ADDRESS 3FFFFFh) R DEV10 bit 7 Legend: R = Readable bit -n = Value at Reset bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R DEV9 R DEV8 R DEV7 R DEV6 R DEV5 R DEV4 R DEV3 bit 0 DEV<10:3>: Device ID bits These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. DEV<10:3> (DEVID2<7:0>) 0100 1110 0100 1110 0100 1101 0100 1101 0100 1101 0100 1101 0100 1110 0100 1110 0100 1110 0100 1110 0100 1110 0100 1110 DEV<2:0> (DEVID2<7:5>) 001 000 111 110 101 100 111 110 101 100 011 010 Device PIC18F46J11 PIC18F45J11 PIC18F44J11 PIC18F26J11 PIC18F25J11 PIC18F24J11 PIC18LF46J11 PIC18LF45J11 PIC18LF44J11 PIC18LF26J11 PIC18LF25J11 PIC18LF24J11 DS39932C-page 398 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 25.2 Watchdog Timer (WDT) PIC18F46J11 family devices have both a conventional WDT circuit and a dedicated, Deep Sleep capable Watchdog Timer. When enabled, the conventional WDT operates in normal Run, Idle and Sleep modes. This data sheet section describes the conventional WDT circuit. The dedicated, Deep Sleep capable WDT can only be enabled in Deep Sleep mode. This timer is described in Section 3.6.4 "Deep Sleep Watchdog Timer (DSWDT)". The conventional WDT is driven by the INTRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by the WDTPS bits in Configuration Register 2H. Available periods range from about 4 ms to 135 seconds (2.25 minutes depending on voltage, temperature and WDT postscaler). The WDT and postscaler are cleared whenever a SLEEP or CLRWDT instruction is executed, or a clock failure (primary or Timer1 oscillator) has occurred. Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: When a CLRWDT instruction is executed, the postscaler count will be cleared. 25.2.1 CONTROL REGISTER The WDTCON register (Register 25-11) is a readable and writable register. The SWDTEN bit enables or disables WDT operation. This allows software to override the WDTEN Configuration bit and enable the WDT only if it has been disabled by the Configuration bit. LVDSTAT is a read-only status bit that is continuously updated and provides information about the current level of VDDCORE. This bit is only valid when the on-chip voltage regulator is enabled. FIGURE 25-1: SWDTEN WDT BLOCK DIAGRAM Enable WDT INTRC Control /128 Wake-up from Power-Managed Modes Programmable Postscaler 1:1 to 1:32,768 4 Reset WDT Reset WDT Counter INTRC Oscillator CLRWDT All Device Resets WDTPS<3:0> Sleep WDT (c) 2009 Microchip Technology Inc. DS39932C-page 399 PIC18F46J11 FAMILY REGISTER 25-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ACCESS FC0h) R/W-1 REGSLP(2) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-x LVDSTAT(2) R-x ULPLVL U-0 -- R/W-0 DS(2) R/W-0 ULPEN R/W-0 ULPSINK R/W-0 SWDTEN(1) bit 0 REGSLP: Voltage Regulator Low-Power Operation Enable bit(2) 1 = On-chip regulator enters low-power operation when device enters Sleep mode 0 = On-chip regulator is active even in Sleep mode LVDSTAT: Low-Voltage Detect Status bit(2) 1 = VDDCORE > 2.45V nominal 0 = VDDCORE < 2.45V nominal ULPLVL: Ultra Low-Power Wake-up Output bit (not valid unless ULPEN = 1) 1 = Voltage on RA0 > ~0.5V 0 = Voltage on RA0 < ~0.5V Unimplemented: Read as `0' DS: Deep Sleep Wake-up Status bit (used in conjunction with RCON, POR and BOR bits to determine Reset source)(2) 1 = If the last exit from POR was caused by a normal wake-up from Deep Sleep 0 = If the last exit from POR was a result of hard cycling VDD, or if the Deep Sleep BOR was enabled and detected, a (VDD < VDSBOR) and (VDD < VPOR) condition ULPEN: Ultra Low-Power Wake-up Module Enable bit 1 = Ultra Low-Power Wake-up module is enabled; ULPLVL bit indicates comparator output 0 = Ultra Low-Power Wake-up module is disabled ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit 1 = Ultra Low-Power Wake-up current sink is enabled (if ULPEN = 1) 0 = Ultra Low-Power Wake-up current sink is disabled SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off This bit has no effect if the Configuration bit, WDTEN, is enabled. Not available on devices where the on-chip voltage regulator is disabled ("LF" devices). bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: TABLE 25-3: Name RCON WDTCON SUMMARY OF WATCHDOG TIMER REGISTERS Bit 7 IPEN Bit 6 -- Bit 5 CM Bit 4 RI -- Bit 3 TO DS Bit 2 PD Bit 1 POR Bit 0 BOR Reset Values on Page: 64 64 REGSLP LVDSTAT ULPLVL ULPEN ULPSINK SWDTEN Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Watchdog Timer. DS39932C-page 400 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 25.3 On-Chip Voltage Regulator Note 1: The on-chip voltage regulator is only available in parts designated with an "F", such as PIC18F25J11. The on-chip regulator is disabled on devices with "LF" in their part number. 2: The VDDCORE/VCAP pin must never be left floating. On "F" devices, it must be connected to a capacitor, of size CEFC, to ground. On "LF" devices, VDDCORE/VCAP must be connected to a power supply source between 2.0V and 2.7V. The digital core logic of the PIC18F46J11 family devices is designed on an advanced manufacturing process, which requires 2.0V to 2.7V. The digital core logic obtains power from the VDDCORE/VCAP power supply pin. However, in many applications it may be inconvenient to run the I/O pins at the same core logic voltage, as it would restrict the ability of the device to interface with other, higher voltage devices, such as those run at a nominal 3.3V. Therefore, all PIC18F46J11 family devices implement a dual power supply rail topology. The core logic obtains power from the VDDCORE/VCAP pin, while the general purpose I/O pins obtain power from the VDD pin of the microcontroller, which may be supplied with a voltage between 2.15V to 3.6V ("F" devices) or 2.0V to 3.6V ("LF" devices). This dual supply topology allows the microcontroller to interface with standard 3.3V logic devices, while running the core logic at a lower voltage of nominally 2.5V. In order to make the microcontroller more convenient to use, an integrated 2.5V low dropout, low quiescent current linear regulator has been integrated on the die inside PIC18F46J11 family devices. This regulator is designed specifically to supply the core logic of the device. It allows PIC18F46J11 family devices to effectively run from a single power supply rail, without the need for external regulators. The on-chip voltage regulator is always enabled on "F" devices. The VDDCORE/VCAP pin serves simultaneously as the regulator output pin and the core logic supply power input pin. A capacitor should be connected to the VDDCORE/VCAP pin to ground and is necessary for regulator stability. For example connections for PIC18F and PIC18LF devices, see Figure 25-2. On "LF" devices, the on-chip regulator is always disabled. This allows the device to save a small amount of quiescent current consumption, which may be advantageous in some types of applications, such as those which will entirely be running at a nominal 2.5V. On PIC18LF46J11 family devices, the VDDCORE/VCAP pin still serves as the core logic power supply input pin, and therefore, must be connected to a 2.0V to 2.7V supply rail at the application circuit board level. On these devices, the I/O pins may still optionally be supplied with a voltage between 2.0V to 3.6V, provided that VDD is always greater than, or equal to, VDDCORE/VCAP. For example connections for PIC18F and PIC18LF devices, see Figure 25-2. Note: In parts designated with an "LF", such as PIC18LF46J11, VDDCORE must never exceed VDD. The specifications for core voltage and capacitance are listed in Section 28.3 "DC Characteristics: PIC18F46J50 Family (Industrial)". 25.3.1 VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION When it is enabled, the on-chip regulator provides a constant voltage of 2.5V nominal to the digital core logic. The regulator can provide this level from a VDD of about 2.5V, all the way up to the device's VDDMAX. It does not have the capability to boost VDD levels below 2.5V. When the VDD supply input voltage drops too low to regulate to 2.5V, the regulator enters Tracking mode. In Tracking mode, the regulator output follows VDD, with a typical voltage drop of 100 mV or less. The on-chip regulator includes a simple, Low-Voltage Detect (LVD) circuit. This circuit is separate and independent of the High/Low-Voltage Detect (HLVD) module described in Section 23.0 "High/Low Voltage Detect (HLVD)". The on-chip regulator LVD circuit continuously monitors the VDDCORE voltage level and updates the LVDSTAT bit in the WDTCON register. The LVD detect threshold is set slightly below the normal regulation set point of the on-chip regulator. Application firmware may optionally poll the LVDSTAT bit to determine when it is safe to run at the maximum rated frequency, so as not to inadvertently violate the voltage versus frequency requirements provided by Figure 28-1. The VDDCORE monitoring LVD circuit is only active when the on-chip regulator is enabled. On "LF" devices, the Analog-to-Digital Converter and the HLVD module can still be used to provide firmware with VDD and VDDCORE voltage level information. (c) 2009 Microchip Technology Inc. DS39932C-page 401 PIC18F46J11 FAMILY FIGURE 25-2: CONNECTIONS FOR THE ON-CHIP REGULATOR 3.3V PIC18FXXJ11 VDD VDDCORE/VCAP CEFC VSS 25.3.2 ON-CHIP REGULATOR AND BOR PIC18FXXJ11 Devices (Regulator Enabled): When the on-chip regulator is enabled, PIC18F46J11 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a minimum output level; the regulator Reset circuitry will generate a Brown-out Reset (BOR). This event is captured by the BOR flag bit (RCON<0>). The operation of the BOR is described in more detail in Section 4.4 "Brown-out Reset (BOR)" and Section 4.4.1 "Detecting BOR". The brown-out voltage levels are specific in Section 28.1 "DC Characteristics: Supply Voltage PIC18F46J11 Family (Industrial)". PIC18LFXXJ11 Devices (Regulator Disabled): 2.5V PIC18LFXXJ11 VDD VDDCORE/VCAP VSS OR 2.5V 3.3V PIC18LFXXJ11 VDD VDDCORE/VCAP VSS 25.3.3 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE should not exceed VDD by 0.3 volts. 25.3.4 OPERATION IN SLEEP MODE When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD. This includes when the device is in Sleep mode, even though the core digital logic does not require much power. To provide additional savings in applications where power resources are critical, the regulator can be configured to automatically enter a lower quiescent draw standby mode whenever the device goes into Sleep mode. This feature is controlled by the REGSLP bit (WDTCON<7>, Register 25-11). If this bit is set upon entry into Sleep mode, the regulator will transition into a lower power state. In this state, the regulator still provides a regulated output voltage necessary to maintain SRAM state information, but consumes less quiescent current. Substantial Sleep mode power savings can be obtained by setting the REGSLP bit, but device wake-up time will increase in order to insure the regulator has enough time to stabilize. DS39932C-page 402 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 25.4 Two-Speed Start-up The Two-Speed Start-up feature helps to minimize the latency period, from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO Configuration bit. Two-Speed Start-up should be enabled only if the primary oscillator mode is HS or HSPLL (Crystal-Based) modes. Since the EC and ECPLL modes do not require an Oscillator Start-up Timer (OST) delay, Two-Speed Start-up should be disabled. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a Power-on Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. FIGURE 25-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL) Q1 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 PLL Clock Output CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event PC + 2 OSTS bit Set Clock Transition PC + 4 PC + 6 Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 25.4.1 SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP 25.5 Fail-Safe Clock Monitor While using the INTRC oscillator in Two-Speed Start-up, the device still obeys the normal command sequences for entering power-managed modes, including serial SLEEP instructions (refer to Section 3.1.4 "Multiple Sleep Commands"). In practice, this means that user code can change the SCS<1:0> bit settings or issue SLEEP instructions before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to Sleep before the device starts to operate from the primary oscillator. User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. Clock monitoring (shown in Figure 25-4) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral device clock and the sample clock are presented as inputs to the clock monitor latch. The clock monitor is set on the falling edge of the device clock source but cleared on the rising edge of the sample clock. (c) 2009 Microchip Technology Inc. DS39932C-page 403 PIC18F46J11 FAMILY FIGURE 25-4: FSCM BLOCK DIAGRAM Clock Monitor Latch (edge-triggered) Peripheral Clock S Q be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shutdown. See Section 3.1.4 "Multiple Sleep Commands" and Section 25.4.1 "Special Considerations for Using Two-Speed Start-up" for more details. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible. INTRC Source (32 s) / 64 488 Hz (2.048 ms) C Q Clock Failure Detected 25.5.1 FSCM AND THE WATCHDOG TIMER Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while the clock monitor is still set, and a clock failure has been detected (Figure 25-5), the following results: * The FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>); * The device clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source - this is the Fail-safe condition); and * The WDT is reset. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing-sensitive applications. In these cases, it may Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTRC clock when a clock failure is detected; this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, Fail-Safe Clock Monitor events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. FIGURE 25-5: Sample Clock Device Clock Output Clock Monitor Output (Q) OSCFIF FSCM TIMING DIAGRAM Oscillator Failure Failure Detected Clock Monitor Test Note: Clock Monitor Test Clock Monitor Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS39932C-page 404 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 25.5.2 EXITING FAIL-SAFE OPERATION The Fail-Safe Clock Monitor condition is terminated by either a device Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 2H (with any required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTRC oscillator provides the device clock until the primary clock source becomes ready (similar to a Two-Speed Start-up). The clock source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The FSCM then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTRC oscillator. The OSCCON register will remain in its Reset state until a power-managed mode is entered. out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. Note: The same logic that prevents false oscillator failure interrupts on POR, or wake-up from Sleep, will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. 25.5.3 FSCM INTERRUPTS IN POWER-MANAGED MODES As noted in Section 25.4.1 "Special Considerations for Using Two-Speed Start-up", it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power-managed mode is selected, the primary clock is disabled. By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. FSCM of the power-managed clock source resumes in the power-managed mode. If an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTRC multiplexer. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTRC source. 25.6 Program Verification and Code Protection For all devices in the PIC18F46J11 family of devices, the on-chip program memory space is treated as a single block. Code protection for this block is controlled by one Configuration bit, CP0. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. 25.6.1 CONFIGURATION REGISTER PROTECTION 25.5.4 POR OR WAKE-UP FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or low-power Sleep mode. When the primary device clock is either the EC or INTRC modes, monitoring can begin immediately following these events. For HS or HSPLL modes, the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FSCM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the device clock and functions until the primary clock is stable (the OST and PLL timers have timed The Configuration registers are protected against untoward changes or reads in two ways. The primary protection is the write-once feature of the Configuration bits, which prevents reconfiguration once the bit has been programmed during a power cycle. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. This is seen by the user as a Configuration Mismatch (CM) Reset. The data for the Configuration registers is derived from the FCW in program memory. When the CP0 bit is set, the source data for device configuration is also protected as a consequence. (c) 2009 Microchip Technology Inc. DS39932C-page 405 PIC18F46J11 FAMILY 25.7 In-Circuit Serial Programming (ICSP) 25.8 In-Circuit Debugger When the DEBUG Configuration bit is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 25-4 lists the resources required by the background debugger. PIC18F46J11 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. TABLE 25-4: I/O pins: Stack: DEBUGGER RESOURCES RB6, RB7 2 levels 512 bytes 10 bytes Program Memory: Data Memory: DS39932C-page 406 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 26.0 INSTRUCTION SET SUMMARY The PIC18F46J11 family of devices incorporates the standard set of 75 PIC18 core instructions, and an extended set of eight new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. The Literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The Control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the Program Counter (PC) is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 26-1 provides the general formats that the instructions can have. All examples use the convention `nnh' to represent a hexadecimal number. The instruction set summary, provided in Table 26-2, lists the standard instructions recognized by the Microchip MPASMTM Assembler. Section 26.1.1 "Standard Instruction Set" provides a description of each instruction. 26.1 Standard Instruction Set The standard PIC18 instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 26-2 lists the byte-oriented, bit-oriented, literal and control operations. Table 26-1 provides the opcode field descriptions. Most Byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a') The file register designator, `f', specifies which file register is to be used by the instruction. The destination designator, `d', specifies where the result of the operation is to be placed. If `d' is `0', the result is placed in the WREG register. If `d' is `1', the result is placed in the file register specified in the instruction. All Bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a') The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator, `f', represents the number of the file in which the bit is located. (c) 2009 Microchip Technology Inc. DS39932C-page 407 PIC18F46J11 FAMILY TABLE 26-1: Field a OPCODE FIELD DESCRIPTIONS Description RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7) Bank Select Register. Used to select the current RAM bank ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative Destination select bit: d = 0: store result in WREG d = 1: store result in file register f Destination: either the WREG register or the specified register file location 8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h) 12-bit register file address (000h to FFFh). This is the source address 12-bit register file address (000h to FFFh). This is the destination address Global Interrupt Enable bit Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) Label name The mode of the TBLPTR register for the table read and table write instructions Used only with table read and table write instructions No Change to register (such as TBLPTR with table reads and writes) Post-Increment register (such as TBLPTR with table reads and writes) Post-Decrement register (such as TBLPTR with table reads and writes) Pre-Increment register (such as TBLPTR with table reads and writes) The relative address (2's complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions Program Counter Program Counter Low Byte Program Counter High Byte Program Counter High Byte Latch Program Counter Upper Byte Latch Power-Down bit Product of Multiply High Byte Product of Multiply Low Byte Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) 21-Bit Table Pointer (points to a program memory location) 8-Bit Table Latch Time-out bit Top-of-Stack Unused or Unchanged Watchdog Timer Working register (accumulator) Don't care (`0' or `1'). The assembler will generate code with x = 0; it is the recommended form of use for compatibility with all Microchip software tools 7-bit offset value for Indirect Addressing of register files (source) 7-bit offset value for Indirect Addressing of register files (destination) bbb BSR C, DC, Z, OV, N d dest f fs fd GIE k label mm * *+ *+* n PC PCL PCH PCLATH PCLATU PD PRODH PRODL s TBLPTR TABLAT TO TOS u WDT WREG x zs zd { } [text] (text) [expr] Optional argument Indicates Indexed Addressing The contents of text Specifies bit n of the register indicated by the pointer, expr Assigned to Register bit field In the set of User-defined term (font is Courier New) DS39932C-page 408 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY EXAMPLE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Example Instruction 0 f (FILE #) ADDWF MYREG, W, B 15 10 OPCODE 9 d 87 a Byte-oriented file register operations d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 12 11 1111 f (Destination FILE #) 0 f (Source FILE #) 0 MOVFF MYREG1, MYREG2 f = 12-bit file register address Bit-oriented file register operations 15 12 11 98 7 f (FILE #) 0 BSF MYREG, bit, B OPCODE b (BIT #) a b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 OPCODE k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 OPCODE 15 1111 12 11 n<19:8> (literal) 87 n<7:0> (literal) 0 0 GOTO Label 8 7 k (literal) 0 MOVLW 7Fh n = 20-bit immediate value 15 OPCODE 15 1111 S = Fast bit 15 OPCODE 15 OPCODE 87 n<7:0> (literal) 11 10 n<10:0> (literal) 0 BC MYFUNC 0 BRA MYFUNC 12 11 n<19:8> (literal) 87 S n<7:0> (literal) 0 0 CALL MYFUNC (c) 2009 Microchip Technology Inc. DS39932C-page 409 PIC18F46J11 FAMILY TABLE 26-2: Mnemonic, Operands PIC18F46J11 FAMILY INSTRUCTION SET Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB SUBWF SUBWFB SWAPF TSTFSZ XORWF Note 1: f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, Skip = Compare f with WREG, Skip > Compare f with WREG, Skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f 1st word Move fs (source) to fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with Borrow Subtract WREG from f Subtract WREG from f with Borrow Swap Nibbles in f Test f, Skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None None None C, DC, Z, OV, N C, Z, N Z, N C, Z, N Z, N None C, DC, Z, OV, N 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 ffff C, DC, Z, OV, N ffff C, DC, Z, OV, N ffff None ffff None ffff Z, N 1, 2 4 1, 2 2: 3: 4: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39932C-page 410 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 26-2: Mnemonic, Operands BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL CLRWDT DAW GOTO NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP Note 1: f, b, a f, b, a f, b, a f, b, a f, b, a n n n n n n n n n n, s -- -- n -- -- -- -- n s k s -- Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call Subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to Address 1st word 2nd word No Operation No Operation Pop Top of Return Stack (TOS) Push Top of Return Stack (TOS) Relative Call Software Device Reset Return from Interrupt Enable Return with Literal in WREG Return from Subroutine Go into Standby mode 1 1 1 (2 or 3) 1 (2 or 3) 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1001 1000 1011 1010 0111 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 bbba bbba bbba bbba bbba 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 ffff ffff ffff ffff ffff nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 ffff ffff ffff ffff ffff nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None None None None None None TO, PD C None 1, 2 1, 2 3, 4 3, 4 1, 2 PIC18F46J11 FAMILY INSTRUCTION SET (CONTINUED) Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes CONTROL OPERATIONS None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD 4 2: 3: 4: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. (c) 2009 Microchip Technology Inc. DS39932C-page 411 PIC18F46J11 FAMILY TABLE 26-2: Mnemonic, Operands LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: k k k f, k k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtract WREG from Literal Exclusive OR Literal with WREG Table Read Table Read with Post-Increment Table Read with Post-Decrement Table Read with Pre-Increment Table Write Table Write with Post-Increment Table Write with Post-Decrement Table Write with Pre-Increment 1 1 1 2 1 1 1 2 1 1 2 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 1000 1001 1010 1011 1100 1101 1110 1111 C, DC, Z, OV, N Z, N Z, N None None None None None C, DC, Z, OV, N Z, N None None None None None None None None PIC18F46J11 FAMILY INSTRUCTION SET (CONTINUED) Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes DATA MEMORY PROGRAM MEMORY OPERATIONS 2 2: 3: 4: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39932C-page 412 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 26.1.1 ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description: STANDARD INSTRUCTION SET ADD Literal to W ADDLW 0 k 255 (W) + k W N, OV, C, DC, Z 0000 1111 kkkk kkkk The contents of W are added to the 8-bit literal `k' and the result is placed in W. 1 1 Q1 Q2 Read literal `k' ADDLW Q3 Process Data 15h Q4 Write to W Operation: Status Affected: Encoding: Description: k ADDWF Syntax: Operands: ADD W to f ADDWF 0 f 255 d [0,1] a [0,1] (W) + (f) dest N, OV, C, DC, Z 0010 01da ffff ffff Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' ADDWF 17h 0C2h 0D9h 0C2h Q3 Process Data REG, 0, 0 Q4 Write to destination 1 1 f {,d {,a}} Words: Cycles: Q Cycle Activity: Decode Example: Before Instruction W = 10h After Instruction W= 25h Example: Before Instruction W = REG = After Instruction W = REG = Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). (c) 2009 Microchip Technology Inc. DS39932C-page 413 PIC18F46J11 FAMILY ADDWFC Syntax: Operands: ADD W and Carry bit to f ADDWFC 0 f 255 d [0,1] a [0,1] (W) + (f) + (C) dest N,OV, C, DC, Z 0010 00da ffff ffff Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' ADDWFC 1 02h 4Dh 0 02h 50h Q3 Process Data REG, 0, 1 Q4 Write to destination 1 1 f {,d {,a}} ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description: AND Literal with W ANDLW 0 k 255 (W) .AND. k W N, Z 0000 1011 kkkk kkkk The contents of W are ANDed with the 8-bit literal `k'. The result is placed in W. 1 1 Q1 Decode Q2 Read literal `k' ANDLW A3h 03h Q3 Process Data 05Fh Q4 Write to W k Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Example: Before Instruction W = After Instruction W = Example: Before Instruction Carry bit = REG = W = After Instruction Carry bit = REG = W = DS39932C-page 414 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY ANDWF Syntax: Operands: AND W with f ANDWF 0 f 255 d [0,1] a [0,1] (W) .AND. (f) dest N, Z 0001 01da ffff ffff The contents of W are ANDed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' ANDWF 17h C2h 02h C2h Q3 Process Data REG, 0, 0 Q4 Write to destination 1 1 No operation If No Jump: Q1 Decode Q2 Read literal `n' HERE = = = = = Q3 Process Data BC 5 Q4 No operation Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC No operation f {,d {,a}} BC Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Carry BC n -128 n 127 if Carry bit is `1', (PC) + 2 + 2n PC None 1110 0010 nnnn nnnn If the Carry bit is '1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2) Operation: Status Affected: Encoding: Description: Example: Example: Before Instruction W = REG = After Instruction W = REG = Before Instruction PC After Instruction If Carry PC If Carry PC address (HERE) 1; address (HERE + 12) 0; address (HERE + 2) (c) 2009 Microchip Technology Inc. DS39932C-page 415 PIC18F46J11 FAMILY BCF Syntax: Operands: Bit Clear f BCF f, b {,a} BN Syntax: Operands: Operation: Status Affected: Encoding: bbba ffff ffff Description: Branch if Negative BN n 0 f 255 0b7 a [0,1] 0 f None 1001 Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. -128 n 127 if Negative bit is `1', (PC) + 2 + 2n PC None 1110 0110 nnnn nnnn If the Negative bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode 1 1(2) Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' BCF Q3 Process Data FLAG_REG, Q4 Write register `f' 7, 0 Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = = Q3 Process Data No operation Q3 Process Data BN Jump Q4 Write to PC No operation Q4 No operation No operation If No Jump: Q1 Decode Example: Before Instruction FLAG_REG = C7h After Instruction FLAG_REG = 47h Example: Before Instruction PC After Instruction If Negative PC If Negative PC address (HERE) 1; address (Jump) 0; address (HERE + 2) DS39932C-page 416 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY BNC Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Carry BNC n BNN Syntax: Operands: Operation: Status Affected: 0011 nnnn nnnn Encoding: Description: Branch if Not Negative BNN n -128 n 127 if Carry bit is `0', (PC) + 2 + 2n PC None 1110 If the Carry bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. -128 n 127 if Negative bit is `0', (PC) + 2 + 2n PC None 1110 0111 nnnn nnnn If the Negative bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 1 1(2) Words: Cycles: Q Cycle Activity: If Jump: Q2 Q3 Process Data No operation Q3 Process Data BNC Jump Q4 Write to PC No operation Q4 No operation Q1 Decode No operation If No Jump: Q2 Q1 Decode 1 1(2) Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = = Q3 Process Data No operation Q3 Process Data BNN Jump Q4 Write to PC No operation Q4 No operation Read literal `n' No operation Read literal `n' HERE = = = = = Example: Example: Before Instruction PC After Instruction If Carry PC If Carry PC address (HERE) 0; address (Jump) 1; address (HERE + 2) Before Instruction PC After Instruction If Negative PC If Negative PC address (HERE) 0; address (Jump) 1; address (HERE + 2) (c) 2009 Microchip Technology Inc. DS39932C-page 417 PIC18F46J11 FAMILY BNOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Overflow BNOV n BNZ Syntax: Operands: Operation: Status Affected: 0101 nnnn nnnn Encoding: Description: Branch if Not Zero BNZ n -128 n 127 if Overflow bit is `0', (PC) + 2 + 2n PC None 1110 If the Overflow bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. -128 n 127 if Zero bit is `0', (PC) + 2 + 2n PC None 1110 0001 nnnn nnnn If the Zero bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 1 1(2) Words: Cycles: Q Cycle Activity: If Jump: Q2 Q3 Process Data No operation Q3 Process Data BNOV Jump address (HERE) 0; address (Jump) 1; address (HERE + 2) Q4 Write to PC No operation Q4 No operation Q1 Decode No operation If No Jump: Q2 Q1 Decode 1 1(2) Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = = Q3 Process Data No operation Q3 Process Data BNZ Jump Q4 Write to PC No operation Q4 No operation Read literal `n' No operation Read literal `n' HERE = = = = = Example: Example: Before Instruction PC After Instruction If Overflow PC If Overflow PC Before Instruction PC After Instruction If Zero PC If Zero PC address (HERE) 0; address (Jump) 1; address (HERE + 2) DS39932C-page 418 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY BRA Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch BRA n BSF Syntax: Operands: Bit Set f BSF f, b {,a} -1024 n 1023 (PC) + 2 + 2n PC None 1101 0nnn nnnn nnnn Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2 Q1 Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC No operation 0 f 255 0b7 a [0,1] 1 f None 1000 bbba ffff ffff Bit `b' in register `f' is set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Decode No operation Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' BSF = = Q3 Process Data Q4 Write register `f' Example: HERE = = BRA Jump Before Instruction PC After Instruction PC address (HERE) address (Jump) Example: FLAG_REG, 7, 1 0Ah 8Ah Before Instruction FLAG_REG After Instruction FLAG_REG (c) 2009 Microchip Technology Inc. DS39932C-page 419 PIC18F46J11 FAMILY BTFSC Syntax: Operands: Bit Test File, Skip if Clear BTFSC f, b {,a} 0 f 255 0b7 a [0,1] skip if (f) = 0 None 1011 bbba ffff ffff If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE FALSE TRUE = = = = = Q3 Process Data Q3 No operation Q3 No operation No operation BTFSC : : Q4 No operation If skip: Q1 No operation Q1 No operation No operation Example: Q4 No operation Q4 No operation No operation Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE FALSE TRUE = = = = = Q3 No operation Q3 No operation No operation BTFSS : : Q4 No operation Q4 No operation No operation Q1 Decode Q2 Read register `f' Q3 Process Data Q4 No operation Words: Cycles: BTFSS Syntax: Operands: Bit Test File, Skip if Set BTFSS f, b {,a} 0 f 255 0b<7 a [0,1] skip if (f) = 1 None 1010 bbba ffff ffff If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: Q Cycle Activity: Q1 Decode If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: FLAG, 1, 0 FLAG, 1, 0 Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC address (HERE) 0; address (TRUE) 1; address (FALSE) Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC address (HERE) 0; address (FALSE) 1; address (TRUE) DS39932C-page 420 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY BTG Syntax: Operands: Bit Toggle f BTG f, b {,a} 0 f 255 0b<7 a [0,1] (f) f None 0111 bbba ffff ffff Bit `b' in data memory location `f' is inverted. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' BTG Q3 Process Data PORTC, 4, 0 Example: Q4 Write register `f' 1 1 BOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Overflow BOV n -128 n 127 if Overflow bit is `1', (PC) + 2 + 2n PC None 1110 0100 nnnn nnnn If the Overflow bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 1 1(2) Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = = Q3 Process Data No operation Q3 Process Data BOV Jump Q4 Write to PC No operation Q4 No operation Example: Before Instruction: PORTC = 0111 0101 [75h] After Instruction: PORTC = 0110 0101 [65h] Before Instruction PC After Instruction If Overflow PC If Overflow PC address (HERE) 1; address (Jump) 0; address (HERE + 2) (c) 2009 Microchip Technology Inc. DS39932C-page 421 PIC18F46J11 FAMILY BZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Zero BZ n CALL Syntax: Operands: Operation: nnnn nnnn Subroutine Call CALL k {,s} 0 k 1048575 s [0,1] (PC) + 4 TOS, k PC<20:1>; if s = 1, (W) WS, (STATUS) STATUSS, (BSR) BSRS None 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8 -128 n 127 if Zero bit is `1', (PC) + 2 + 2n PC None 1110 0000 If the Zero bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 1 1(2) Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = = Q3 Process Data No operation Q3 Process Data BZ Jump Q4 Write to PC No operation Words: Q4 No operation Cycles: Q Cycle Activity: Q1 Decode Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2 Q2 Read literal `k'<7:0>, No operation HERE Q3 Push PC to stack No operation CALL Q4 Read literal 'k'<19:8>, Write to PC No operation Example: Before Instruction PC After Instruction If Zero PC If Zero PC address (HERE) 1; address (Jump) 0; address (HERE + 2) No operation Example: THERE,1 Before Instruction PC = After Instruction PC = TOS = WS = BSRS = STATUSS = address (HERE) address (THERE) address (HERE + 4) W BSR STATUS DS39932C-page 422 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Clear f CLRF f {,a} CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer CLRWDT None 000h WDT, 000h WDT postscaler, 1 TO, 1 PD TO, PD 0000 0000 0000 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. 1 1 Q1 Decode Q2 No operation CLRWDT = = = = = ? 00h 0 1 1 Q3 Process Data Q4 No operation 0 f 255 a [0,1] 000h f, 1Z Z 0110 101a ffff ffff Status Affected: Encoding: Description: Clears the contents of the specified register. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' CLRF = = 5Ah 00h Q3 Process Data FLAG_REG,1 Q4 Write register `f' Example: Before Instruction WDT Counter After Instruction WDT Counter WDT Postscaler TO PD Example: Before Instruction FLAG_REG After Instruction FLAG_REG (c) 2009 Microchip Technology Inc. DS39932C-page 423 PIC18F46J11 FAMILY COMF Syntax: Operands: Complement f COMF f {,d {,a}} CPFSEQ Syntax: Operands: Operation: Compare f with W, Skip if f = W CPFSEQ 0 f 255 a [0,1] (f) - (W), skip if (f) = (W) (unsigned comparison) None 0110 001a ffff ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register `f' Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation f {,a} 0 f 255 d [0,1] a [0,1] f dest N, Z 0001 11da ffff ffff The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' COMF 13h 13h ECh Q3 Process Data REG, 0, 0 Q4 Write to destination Example: Before Instruction REG = After Instruction REG = W = Q Cycle Activity: Q1 Decode If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NEQUAL EQUAL = = = = = = CPFSEQ REG, 0 : : HERE ? ? W; Address (EQUAL) W; Address (NEQUAL) Before Instruction PC Address W REG After Instruction If REG PC If REG PC DS39932C-page 424 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY CPFSGT Syntax: Operands: Operation: Compare f with W, Skip if f > W CPFSGT 0 f 255 a [0,1] (f) - (W), skip if (f) > (W) (unsigned comparison) None 0110 010a ffff ffff Compares the contents of data memory location `f' to the contents of the W by performing an unsigned subtraction. If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE NLESS LESS = = < = = Q3 No operation Q3 No operation No operation Q4 No operation Q4 No operation No operation Words: Cycles: f {,a} CPFSLT Syntax: Operands: Operation: Compare f with W, Skip if f < W CPFSLT 0 f 255 a [0,1] (f) - (W), skip if (f) < (W) (unsigned comparison) None 0110 000a ffff ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Decode Q2 Read register `f' Q3 Process Data Q4 No operation f {,a} Status Affected: Encoding: Description: Status Affected: Encoding: Description: Q Cycle Activity: Q Cycle Activity: Q1 Decode If skip: Q2 Read register `f' If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NGREATER GREATER = = > = = CPFSLT REG, 1 : : Address (HERE) ? W; Address (LESS) W; Address (NLESS) CPFSGT REG, 0 : : Before Instruction PC W After Instruction If REG PC If REG PC Address (HERE) ? W; Address (GREATER) W; Address (NGREATER) Before Instruction PC W After Instruction If REG PC If REG PC (c) 2009 Microchip Technology Inc. DS39932C-page 425 PIC18F46J11 FAMILY DAW Syntax: Operands: Operation: Decimal Adjust W Register DAW None If [W<3:0> > 9] or [DC = 1] then, (W<3:0>) + 6 W<3:0>; else, (W<3:0>) W<3:0> If [W<7:4> > 9] or [C = 1] then, (W<7:4>) + 6 W<7:4>, C = 1; else, (W<7:4>) W<7:4> Status Affected: Encoding: Description: C 0000 0000 0000 0111 DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. 1 1 Words: Q2 Read register W DAW A5h 0 0 05h 1 0 Q3 Process Data Q4 Write W Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' DECF 01h 0 00h 1 Q3 Process Data CNT, 1, 0 Q4 Write to destination Q1 Decode DECF Syntax: Operands: Decrement f DECF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) - 1 dest C, DC, N, OV, Z 0000 01da ffff ffff Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Example 1: Before Instruction W = C = DC = After Instruction W = C = DC = Example 2: Before Instruction W = C = DC = After Instruction W = C = DC = Example: Before Instruction CNT = Z = After Instruction CNT = Z = CEh 0 0 34h 1 0 DS39932C-page 426 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY DECFSZ Syntax: Operands: Decrement f, Skip if 0 DECFSZ f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result = 0 None 0010 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE CONTINUE Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2) Q3 No operation Q3 No operation No operation DECFSZ GOTO Q4 No operation Q4 No operation No operation CNT, 1, 1 LOOP If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE ZERO NZERO = = = = = Q3 No operation Q3 No operation No operation DCFSNZ : : ? TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) Q4 No operation Q4 No operation No operation Q2 Read register `f' Q3 Process Data Q4 Write to destination Words: Cycles: DCFSNZ Syntax: Operands: Decrement f, Skip if not 0 DCFSNZ 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result 0 None 0100 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q4 Write to destination f {,d {,a}} Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: Q Cycle Activity: Q Cycle Activity: Q1 Decode Q2 Read register `f' If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: TEMP, 1, 0 Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC (c) 2009 Microchip Technology Inc. DS39932C-page 427 PIC18F46J11 FAMILY GOTO Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Unconditional Branch GOTO k 0 k 1048575 k PC<20:1> None 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Operation: Status Affected: Encoding: Description: INCF Syntax: Operands: Increment f INCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) + 1 dest C, DC, N, OV, Z 0010 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. 2 2 Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k'<7:0>, No operation Q3 No operation No operation Q4 Read literal `k'<19:8>, Write to PC No operation Words: Cycles: Q Cycle Activity: Q1 Decode No operation Example: 1 1 Q2 Read register `f' INCF FFh 0 ? ? 00h 1 1 1 Q3 Process Data CNT, 1, 0 Q4 Write to destination GOTO THERE After Instruction PC = Address (THERE) Example: Before Instruction CNT = Z = C = DC = After Instruction CNT = Z = C = DC = DS39932C-page 428 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY INCFSZ Syntax: Operands: Increment f, Skip if 0 INCFSZ 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result = 0 None 0011 11da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. (default) If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE NZERO ZERO Q3 Process Data Q3 No operation Q3 No operation No operation INCFSZ : : Q4 Write to destination If skip: Q1 No operation Q1 No operation No operation Example: Q4 No operation Q4 No operation No operation CNT, 1, 0 Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE ZERO NZERO Q3 No operation Q3 No operation No operation INFSNZ Q4 No operation Q4 No operation No operation Q1 Decode Q2 Read register `f' Q3 Process Data Q4 Write to destination Words: Cycles: f {,d {,a}} INFSNZ Syntax: Operands: Increment f, Skip if not 0 INFSNZ 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result 0 None 0100 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. f {,d {,a}} Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: Q Cycle Activity: Q1 Decode If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: REG, 1, 0 Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO) Before Instruction PC = After Instruction REG = If REG PC = If REG = PC = Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO) (c) 2009 Microchip Technology Inc. DS39932C-page 429 PIC18F46J11 FAMILY IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR Literal with W IORLW k 0 k 255 (W) .OR. k W N, Z 0000 1001 kkkk kkkk The contents of W are ORed with the eight-bit literal `k'. The result is placed in W. 1 1 Q1 Decode Q2 Read literal `k' IORLW 9Ah BFh Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' IORWF 13h 91h 13h 93h Q3 Process Data RESULT, 0, 1 Q4 Write to destination Q3 Process Data 35h Q4 Write to W Operation: Status Affected: Encoding: Description: IORWF Syntax: Operands: Inclusive OR W with f IORWF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (W) .OR. (f) dest N, Z 0001 00da ffff ffff Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Words: Cycles: Q Cycle Activity: Example: Before Instruction W = After Instruction W = Example: Before Instruction RESULT = W = After Instruction RESULT = W = DS39932C-page 430 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY LFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' MSB Q3 Process Data Q4 Write literal `k' MSB to FSRfH Write literal `k' to FSRfL Load FSR LFSR f, k 0f2 0 k 4095 k FSRf None 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Operation: Status Affected: Encoding: Description: MOVF Syntax: Operands: Move f MOVF f {,d {,a}} 0 f 255 d [0,1] a [0,1] f dest N, Z 0101 00da ffff ffff The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. The 12-bit literal `k' is loaded into the file select register pointed to by `f'. 2 2 Decode Read literal `k' LSB Process Data Example: After Instruction FSR2H FSR2L LFSR 2, 3ABh = = 03h ABh Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' MOVF = = = = Q3 Process Data REG, 0, 0 22h FFh 22h 22h Q4 Write W Example: Before Instruction REG W After Instruction REG W (c) 2009 Microchip Technology Inc. DS39932C-page 431 PIC18F46J11 FAMILY MOVFF Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: Move f to f MOVFF fs,fd 0 fs 4095 0 fd 4095 (fs) fd None 1100 1111 ffff ffff ffff ffff ffffs ffffd MOVLB Syntax: Operands: Operation: Status Affected: Encoding: Description: Move Literal to Low Nibble in BSR MOVLW k 0 k 255 k BSR None 0000 0001 kkkk kkkk The eight-bit literal `k' is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains `0' regardless of the value of k7:k4. 1 1 Q1 Decode Q2 Read literal `k' MOVLB 02h 05h Q3 Process Data 5 Q4 Write literal `k' to BSR The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register Words: Cycles: Q Cycle Activity: Example: Before Instruction BSR Register = After Instruction BSR Register = Words: Cycles: Q Cycle Activity: Q1 Decode 2 2 Q2 Read register `f' (src) No operation No dummy read Q3 Process Data No operation Q4 No operation Write register `f' (dest) Decode Example: MOVFF = = = = REG1, REG2 33h 11h 33h 33h Before Instruction REG1 REG2 After Instruction REG1 REG2 DS39932C-page 432 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' MOVLW 5Ah Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' MOVWF 4Fh FFh 4Fh 4Fh Q3 Process Data REG, 0 Q4 Write register `f' Q3 Process Data 5Ah Q4 Write to W 1 1 Move Literal to W MOVLW k 0 k 255 kW None 0000 1110 kkkk kkkk The eight-bit literal `k' is loaded into W. Operation: Status Affected: Encoding: Description: MOVWF Syntax: Operands: Move W to f MOVWF 0 f 255 a [0,1] (W) f None 0110 111a ffff ffff Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 f {,a} Example: After Instruction W = Example: Before Instruction W = REG = After Instruction W = REG = (c) 2009 Microchip Technology Inc. DS39932C-page 433 PIC18F46J11 FAMILY MULLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Multiply Literal with W MULLW k MULWF Syntax: Operands: Operation: 1101 kkkk kkkk Status Affected: Encoding: Description: Multiply W with f MULWF 0 f 255 a [0,1] (W) x (f) PRODH:PRODL None 0000 001a ffff ffff An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Q2 Read literal `k' Q3 Process Data Q4 Write registers PRODH: PRODL If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' Q3 Process Data Q4 Write registers PRODH: PRODL 1 1 f {,a} 0 k 255 (W) x k PRODH:PRODL None 0000 An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Example: Before Instruction W PRODH PRODL After Instruction W PRODH PRODL MULLW = = = = = = 0C4h E2h ? ? E2h ADh 08h Example: Before Instruction W REG PRODH PRODL After Instruction W REG PRODH PRODL MULWF = = = = = = = = REG, 1 C4h B5h ? ? C4h B5h 8Ah 94h DS39932C-page 434 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY NEGF Syntax: Operands: Operation: Status Affected: Encoding: Description: Negate f NEGF f {,a} NOP Syntax: Operands: Operation: Status Affected: Encoding: ffff ffff Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 No operation Q3 No operation Q4 No operation 1 1 110a No Operation NOP None No operation None 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx 0 f 255 a [0,1] (f) + 1 f N, OV, C, DC, Z 0110 Location `f' is negated using two's complement. The result is placed in the data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. No operation. Example: None. Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' NEGF Q3 Process Data REG, 1 Q4 Write register `f' Example: Before Instruction REG = After Instruction REG = 0011 1010 [3Ah] 1100 0110 [C6h] (c) 2009 Microchip Technology Inc. DS39932C-page 435 PIC18F46J11 FAMILY POP Syntax: Operands: Operation: Status Affected: Encoding: Description: Pop Top of Return Stack POP None (TOS) bit bucket None 0000 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1 Q1 Decode Q2 No operation POP GOTO Q3 POP TOS value Q4 No operation Example: NEW = = = = 0031A2h 014332h 014332h NEW PUSH Syntax: Operands: Operation: Status Affected: Encoding: Description: Push Top of Return Stack PUSH None (PC + 2) TOS None 0000 0000 0000 0101 The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. 1 1 Q1 Decode Q2 PUSH PC + 2 onto return stack PUSH = = = = = 345Ah 0124h 0126h 0126h 345Ah Q3 No operation Q4 No operation Words: Cycles: Q Cycle Activity: Words: Cycles: Q Cycle Activity: Example: Before Instruction TOS Stack (1 level down) After Instruction TOS PC Before Instruction TOS PC After Instruction PC TOS Stack (1 level down) DS39932C-page 436 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY RCALL Syntax: Operands: Operation: Status Affected: Encoding: Description: Relative Call RCALL n RESET Syntax: Operands: Operation: Status Affected: 1nnn nnnn nnnn Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Start reset RESET Reset Value Reset Value Q3 No operation Q4 No operation Reset RESET None Reset all registers and flags that are affected by a MCLR Reset. All 0000 0000 1111 1111 This instruction provides a way to execute a MCLR Reset in software. 1 1 -1024 n 1023 (PC) + 2 TOS, (PC) + 2 + 2n PC None 1101 Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2 Q1 Q2 Read literal `n' PUSH PC to stack Q3 Process Data Q4 Write to PC Words: Cycles: Q Cycle Activity: Decode Example: After Instruction Registers = Flags* = No operation Example: No operation HERE No operation RCALL Jump No operation Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2) (c) 2009 Microchip Technology Inc. DS39932C-page 437 PIC18F46J11 FAMILY RETFIE Syntax: Operands: Operation: Return from Interrupt RETFIE {s} s [0,1] (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged GIE/GIEH, PEIE/GIEL. 0000 0000 0001 000s Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' No operation Q3 Process Data No operation Q4 POP PC from stack, write to W No operation Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low-priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Example: Q2 No operation Q3 No operation Q4 POP PC from stack Set GIEH or GIEL No operation Example: No operation RETFIE 1 = = = = = TOS WS BSRS STATUSS 1 No operation No operation CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; Before Instruction W = After Instruction W = W contains table offset value W now has table value Q1 Decode RETLW Syntax: Operands: Operation: Return Literal to W RETLW k 0 k 255 k W, (TOS) PC, PCLATU, PCLATH are unchanged None 0000 1100 kkkk kkkk W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2 Status Affected: Encoding: Description: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: No operation W = offset Begin table After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL End of table 07h value of kn DS39932C-page 438 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY RETURN Syntax: Operands: Operation: Return from Subroutine RETURN {s} s [0,1] (TOS) PC; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged None 0000 0000 0001 001s Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Q1 Decode No operation Q2 No operation No operation Q3 Process Data No operation Q4 POP PC from stack No operation Words: Cycles: Q Cycle Activity: Example: RETURN Q1 Decode Q2 Read register `f' RLCF Q3 Process Data Q4 Write to destination After Instruction: PC = TOS RLCF Syntax: Operands: Rotate Left f through Carry RLCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Example: Before Instruction REG = C = After Instruction REG = W = C = REG, 0, 0 1110 0110 0 1110 0110 1100 1100 1 (c) 2009 Microchip Technology Inc. DS39932C-page 439 PIC18F46J11 FAMILY RLNCF Syntax: Operands: Rotate Left f (No Carry) RLNCF 0 f 255 d [0,1] a [0,1] (f 0 f 255 d [0,1] a [0,1] (f Operation: Status Affected: Encoding: Description: Operation: 1010 1011 0101 0111 Before Instruction REG = C = After Instruction REG = W = C = 1110 0110 0 1110 0110 0111 0011 0 DS39932C-page 440 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY RRNCF Syntax: Operands: Rotate Right f (No Carry) RRNCF f {,d {,a}} SETF Syntax: Operands: Operation: Status Affected: Encoding: ffff Description: Set f SETF f {,a} 0 f 255 d [0,1] a [0,1] (f 0 f 255 a [0,1] FFh f None 0110 100a ffff ffff The contents of the specified register are set to FFh. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' SETF = = 5Ah FFh Q3 Process Data REG,1 Q4 Write register `f' Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register `f' RRNCF Q3 Process Data REG, 1, 0 Q4 Write to destination Example: Before Instruction REG After Instruction REG Example 1: Before Instruction REG = After Instruction REG = Example 2: 1101 0111 1110 1011 REG, 0, 0 RRNCF Before Instruction W = REG = After Instruction W = REG = ? 1101 0111 1110 1011 1101 0111 (c) 2009 Microchip Technology Inc. DS39932C-page 441 PIC18F46J11 FAMILY SLEEP Syntax: Operands: Operation: Enter Sleep Mode SLEEP None 00h WDT, 0 WDT postscaler, 1 TO, 0 PD TO, PD 0000 0000 0000 0011 The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. The Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Words: Cycles: Q Cycle Activity: Q1 Decode Q2 No operation SLEEP Q3 Process Data Q4 Go to Sleep Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' Q3 Process Data Q4 Write to destination 1 1 SUBFWB Syntax: Operands: Subtract f from W with Borrow SUBFWB 0 f 255 d [0,1] a [0,1] (W) - (f) - (C) dest N, OV, C, DC, Z 0101 01da ffff ffff Subtract register `f' and Carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 f {,d {,a}} Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: Example: Before Instruction TO = ? ? PD = After Instruction 1 TO = 0 PD = If WDT causes wake-up, this bit is cleared. Example 1: SUBFWB REG, 1, 0 Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive SUBFWB REG, 1, 0 Example 3: Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39932C-page 442 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: Before Instruction W = C = After Instruction W = C = Z = N = Example 3: Before Instruction W = C = After Instruction W = C = Z = N = Q2 Read literal `k' SUBLW 01h ? 01h 1 0 0 SUBLW 02h ? 00h 1 1 0 SUBLW 03h ? FFh 0 0 1 ; (2's complement) ; result is negative ; result is zero ; result is positive Words: 02h Cycles: Q Cycle Activity: Q1 Decode Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Q2 Read register `f' SUBWF 3 2 ? 1 2 1 0 0 SUBWF 2 2 ? 2 0 1 1 0 SUBWF 1 2 ? FFh ;(2's complement) 2 0 ; result is negative 0 1 Q3 Process Data REG, 1, 0 Q4 Write to destination Q3 Process Data 02h Q4 Write to W Subtract W from Literal SUBLW k 0 k 255 k - (W) W N, OV, C, DC, Z 0000 1000 kkkk kkkk W is subtracted from the eight-bit literal `k'. The result is placed in W. 1 1 Operation: Status Affected: Encoding: Description: SUBWF Syntax: Operands: Subtract W from f SUBWF 0 f 255 d [0,1] a [0,1] (f) - (W) dest N, OV, C, DC, Z 0101 11da ffff ffff Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 f {,d {,a}} 02h ; result is positive REG, 0, 0 ; result is zero REG, 1, 0 (c) 2009 Microchip Technology Inc. DS39932C-page 443 PIC18F46J11 FAMILY SUBWFB Syntax: Operands: Subtract W from f with Borrow SUBWFB 0 f 255 d [0,1] a [0,1] (f) - (W) - (C) dest N, OV, C, DC, Z 0101 10da ffff ffff Status Affected: Encoding: Description: Subtract W and the Carry flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W C Z N = = = = 1 1 Q2 Read register `f' SUBWFB 19h 0Dh 1 0Ch 0Dh 1 0 0 Q3 Process Data REG, 1, 0 (0001 1001) (0000 1101) (0000 1011) (0000 1101) ; result is positive Example: Q4 Write to destination Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' SWAPF 53h 35h Q3 Process Data REG, 1, 0 Q4 Write to destination f {,d {,a}} SWAPF Syntax: Operands: Swap f SWAPF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> None 0011 10da ffff ffff The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Operation: Status Affected: Encoding: Description: Operation: Before Instruction REG = After Instruction REG = SUBWFB REG, 0, 0 1Bh 1Ah 0 1Bh 00h 1 1 0 SUBWFB 03h 0Eh 1 F5h 0Eh 0 0 1 (0001 1011) (0001 1010) (0001 1011) ; result is zero REG, 1, 0 (0000 0011) (0000 1101) (1111 0100) ; [2's comp] (0000 1101) ; result is negative DS39932C-page 444 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TBLRD Syntax: Operands: Operation: Table Read TBLRD ( *; *+; *-; +*) None if TBLRD *, (Prog Mem (TBLPTR)) TABLAT, TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) - 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR, (Prog Mem (TBLPTR)) TABLAT 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* TBLRD Example 1: Table Read (Continued) TBLRD *+ ; = = = = = +* ; = = = = = = AAh 01A357h 12h 34h 34h 01A358h 55h 00A356h 34h 34h 00A357h Before Instruction TABLAT TBLPTR MEMORY(00A356h) After Instruction TABLAT TBLPTR Example 2: TBLRD Before Instruction TABLAT TBLPTR MEMORY(01A357h) MEMORY(01A358h) After Instruction TABLAT TBLPTR Status Affected: None Encoding: Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR<0> = 0: Least Significant Byte of Program Memory Word TBLPTR<0> = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: Cycles: Q Cycle Activity: Q1 Decode No operation 1 2 Q2 No operation No operation (Read Program Memory) Q3 No operation No operation Q4 No operation No operation (Write TABLAT) (c) 2009 Microchip Technology Inc. DS39932C-page 445 PIC18F46J11 FAMILY TBLWT Syntax: Operands: Operation: Table Write TBLWT ( *; *+; *-; +*) None if TBLWT*, (TABLAT) Holding Register, TBLPTR - No Change; if TBLWT*+, (TABLAT) Holding Register, (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register, (TBLPTR) - 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR, (TABLAT) Holding Register None 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* TBLWT Example 1: Table Write (Continued) TBLWT *+; Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2: TBLWT +*; Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h Status Affected: Encoding: Description: This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 5.0 "Memory Organization" for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR<0> = 0: Least Significant Byte of Program Memory Word TBLPTR<0> = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * * * * no change post-increment post-decrement pre-increment Words: Cycles: Q Cycle Activity: 1 2 Q1 Decode Q2 Q3 Q4 No No No operation operation operation No No No No operation operation operation operation (Write to (Read Holding TABLAT) Register) DS39932C-page 446 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TSTFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Test f, Skip if 0 TSTFSZ f {,a} 0 f 255 a [0,1] skip if f = 0 None 0110 011a ffff ffff If `f' = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE NZERO ZERO = = = = Q3 No operation Q3 No operation No operation TSTFSZ : : Q4 No operation Q4 No operation No operation Q2 Read register `f' Q3 Process Data Q4 No operation XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR Literal with W XORLW k 0 k 255 (W) .XOR. k W N, Z 0000 1010 kkkk kkkk The contents of W are XORed with the 8-bit literal `k'. The result is placed in W. 1 1 Q1 Decode Q2 Read literal `k' XORLW B5h 1Ah Q3 Process Data 0AFh Q4 Write to W Words: Cycles: Q Cycle Activity: Example: Before Instruction W = After Instruction W = Q Cycle Activity: If skip and followed by 2-word instruction: CNT, 1 Before Instruction PC After Instruction If CNT PC If CNT PC Address (HERE) 00h, Address (ZERO) 00h, Address (NZERO) (c) 2009 Microchip Technology Inc. DS39932C-page 447 PIC18F46J11 FAMILY XORWF Syntax: Operands: Exclusive OR W with f XORWF 0 f 255 d [0,1] a [0,1] (W) .XOR. (f) dest N, Z 0001 10da ffff ffff Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' XORWF AFh B5h 1Ah B5h Q3 Process Data REG, 1, 0 Q4 Write to destination 1 1 f {,d {,a}} Operation: Status Affected: Encoding: Description: Example: Before Instruction REG = W = After Instruction REG = W = DS39932C-page 448 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 26.2 Extended Instruction Set In addition to the standard 75 instructions of the PIC18 instruction set, the PIC18F46J11 family of devices also provides an optional extension to the core CPU functionality. The added features include eight additional instructions that augment Indirect and Indexed Addressing operations and the implementation of Indexed Literal Offset Addressing for many of the standard PIC18 instructions. The additional features of the extended instruction set are enabled by default on unprogrammed devices. Users must properly set or clear the XINST Configuration bit during programming to enable or disable these features. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers (FSR), or use them for Indexed Addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: * Dynamic allocation and deallocation of software stack space when entering and leaving subroutines * Function Pointer invocation * Software Stack Pointer manipulation * Manipulation of variables located in a software stack A summary of the instructions in the extended instruction set is provided in Table 26-3. Detailed descriptions are provided in Section 26.2.2 "Extended Instruction Set". The opcode field descriptions in Table 26-1 (page 408) apply to both the standard and extended PIC18 instruction sets. Note: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. 26.2.1 EXTENDED INSTRUCTION SYNTAX Most of the extended instructions use indexed arguments, using one of the FSRs and some offset to specify a source or destination register. When an argument for an instruction serves as part of Indexed Addressing, it is enclosed in square brackets ("[ ]"). This is done to indicate that the argument is used as an index or offset. The MPASMTM Assembler will flag an error if it determines that an index or offset value is not bracketed. When the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 26.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands". Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces ("{ }"). TABLE 26-3: Mnemonic, Operands ADDFSR ADDULNK CALLW MOVSF MOVSS PUSHL SUBFSR SUBULNK f, k k EXTENSIONS TO THE PIC18 INSTRUCTION SET Description Add Literal to FSR Add Literal to FSR2 and Return Call Subroutine using WREG Move zs (source) to 1st word fd (destination) 2nd word Move zs (source) to 1st word zd (destination) 2nd word Store Literal at FSR2, Decrement FSR2 Subtract Literal from FSR Subtract Literal from FSR2 and Return Cycles 1 2 2 2 2 1 1 2 16-Bit Instruction Word MSb 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk LSb kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk Status Affected None None None None -- None -- None -- None None zs, fd zs, zd k f, k k (c) 2009 Microchip Technology Inc. DS39932C-page 449 PIC18F46J11 FAMILY 26.2.2 ADDFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' Q3 Process Data Q4 Write to FSR EXTENDED INSTRUCTION SET Add Literal to FSR ADDFSR f, k 0 k 63 f [ 0, 1, 2 ] FSR(f) + k FSR(f) None 1110 1000 ffkk kkkk The 6-bit literal `k' is added to the contents of the FSR specified by `f'. 1 1 Status Affected: Encoding: Description: ADDULNK Syntax: Operands: Operation: Add Literal to FSR2 and Return ADDULNK k 0 k 63 FSR2 + k FSR2, (TOS) PC None 1110 1000 11kk kkkk The 6-bit literal `k' is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. Words: 03FFh 0422h Cycles: Q Cycle Activity: Q1 Decode No Operation Q2 Read literal `k' No Operation Q3 Process Data No Operation Q4 Write to FSR No Operation 1 2 Example: ADDFSR 2, 23h Before Instruction FSR2 = After Instruction FSR2 = Example: ADDULNK 23h 03FFh 0100h 0422h (TOS) Before Instruction FSR2 = PC = After Instruction FSR2 = PC = Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS39932C-page 450 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY CALLW Syntax: Operands: Operation: Subroutine Call using WREG CALLW None (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU None 0000 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, STATUS or BSR. Words: Cycles: Q Cycle Activity: Q1 Decode No operation Q2 Read WREG No operation Q3 Push PC to stack No operation Q4 No operation No operation Words: Cycles: Q Cycle Activity: Q1 Decode Example: HERE CALLW Decode address (HERE) 10h 00h 06h 001006h address (HERE + 2) 10h 00h 06h Example: Before Instruction PC = PCLATH = PCLATU = W = After Instruction PC = TOS = PCLATH = PCLATU = W = Q2 Q3 Q4 Read source reg Write register `f' (dest) Determine Determine source addr source addr No operation No dummy read No operation 1 2 MOVSF Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: Move Indexed to f MOVSF [zs], fd 0 zs 127 0 fd 4095 ((FSR2) + zs) fd None 1110 1111 1011 ffff 0zzz ffff zzzzs ffffd Status Affected: Encoding: Description The contents of the source register are moved to destination register `fd'. The actual address of the source register is determined by adding the 7-bit literal offset `zs', in the first word, to the value of FSR2. The address of the destination register is specified by the 12-bit literal `fd' in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. 2 2 MOVSF = = = = = = [05h], REG2 80h 33h 11h 80h 33h 33h Before Instruction FSR2 Contents of 85h REG2 After Instruction FSR2 Contents of 85h REG2 (c) 2009 Microchip Technology Inc. DS39932C-page 451 PIC18F46J11 FAMILY MOVSS Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (dest.) Description Move Indexed to Indexed MOVSS [zs], [zd] 0 zs 127 0 zd 127 ((FSR2) + zs) ((FSR2) + zd) None 1110 1111 1011 xxxx 1zzz xzzz zzzzs zzzzd PUSHL Syntax: Operands: Operation: Status Affected: Encoding: Description: Store Literal at FSR2, Decrement FSR2 PUSHL k 0 k 255 k (FSR2), FSR2 - 1 FSR2 None 1110 1010 kkkk kkkk The 8-bit literal `k' is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read `k' Q3 Process data Q4 Write to destination 1 1 The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets `zs' or `zd', respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. If the resultant destination address points to an Indirect Addressing register, the instruction will execute as a NOP. Example: PUSHL 08h = = = = 01ECh 00h 01EBh 08h Before Instruction FSR2H:FSR2L Memory (01ECh) After Instruction FSR2H:FSR2L Memory (01ECh) Words: Cycles: Q Cycle Activity: Q1 Decode Decode 2 2 Q2 Q3 Q4 Read source reg Write to dest reg Determine Determine source addr source addr Determine dest addr Determine dest addr Example: MOVSS [05h], [06h] = = = = = = 80h 33h 11h 80h 33h 33h Before Instruction FSR2 Contents of 85h Contents of 86h After Instruction FSR2 Contents of 85h Contents of 86h DS39932C-page 452 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY SUBFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract Literal from FSR SUBFSR f, k 0 k 63 f [ 0, 1, 2 ] FSRf - k FSRf None 1110 1001 ffkk kkkk The 6-bit literal `k' is subtracted from the contents of the FSR specified by `f'. 1 1 Q1 Decode Q2 Read register `f' Q3 Process Data Q4 Write to destination Words: Example: Before Instruction FSR2 = After Instruction FSR2 = SUBFSR 2, 23h 03FFh 03DCh Cycles: Q Cycle Activity: Q1 Decode No Operation Q2 Read register `f' No Operation Q3 Process Data No Operation Q4 Write to destination No Operation Status Affected: Encoding: Description: SUBULNK Syntax: Operands: Operation: Subtract Literal from FSR2 and Return SUBULNK k 0 k 63 FSR2 - k FSR2, (TOS) PC None 1110 1001 11kk kkkk The 6-bit literal `k' is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. 1 2 Words: Cycles: Q Cycle Activity: Example: Before Instruction FSR2 = PC = After Instruction FSR2 = PC = SUBULNK 23h 03FFh 0100h 03DCh (TOS) (c) 2009 Microchip Technology Inc. DS39932C-page 453 PIC18F46J11 FAMILY 26.2.3 BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely 26.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands Note: In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 5.6.1 "Indexed Addressing with Literal Offset"). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (a = 0) or in a GPR bank designated by the BSR (a = 1). When the extended instruction set is enabled and a = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument - that is, all byte-oriented and bit-oriented instructions, or almost half of the core PIC18 instructions - may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward-compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 26.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands"). Although the Indexed Literal Offset mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset mode are provided on the following page to show how execution is affected. The operand conditions provided in the examples are applicable to all instructions of these types. When the extended instruction set is enabled, the file register argument `f' in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value `k'. As already noted, this occurs only when `f' is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets ("[ ]"). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within the brackets, will generate an error in the MPASM Assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be `0'. This is in contrast to standard operation (extended instruction set disabled) when `a' is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler. The destination argument `d' functions as before. In the latest versions of the MPASM Assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing. 26.2.4 CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18F46J11 family, it is very important to consider the type of code. A large, re-entrant application that is written in C and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39932C-page 454 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description: ADD W to Indexed (Indexed Literal Offset mode) ADDWF 0 k 95 d [0,1] (W) + ((FSR2) + k) dest N, OV, C, DC, Z 0010 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value `k'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read `k' Q3 Process Data [OFST] ,0 = = = = = = 17h 2Ch 0A00h 20h 37h 20h SETF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read `k' Q3 Process Data [OFST] 2Ch 0A00h 00h FFh Q4 Write register Set Indexed (Indexed Literal Offset mode) SETF [k] 0 k 95 FFh ((FSR2) + k) None 0110 1000 kkkk kkkk The contents of the register indicated by FSR2, offset by `k', are set to FFh. 1 1 Q4 Write to destination Example: BSF = = = = [FLAG_OFST], 7 0Ah 0A00h 55h D5h Before Instruction FLAG_OFST FSR2 Contents of 0A0Ah After Instruction Contents of 0A0Ah 1 1 [k] {,d} BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' Q3 Process Data Q4 Write to destination Bit Set Indexed (Indexed Literal Offset mode) BSF [k], b 0 f 95 0b7 1 ((FSR2) + k) None 1000 bbb0 kkkk kkkk Bit `b' of the register indicated by FSR2, offset by the value `k', is set. 1 1 Example: ADDWF Before Instruction W OFST FSR2 Contents of 0A2Ch After Instruction W Contents of 0A2Ch Example: SETF = = = = Before Instruction OFST FSR2 Contents of 0A2Ch After Instruction Contents of 0A2Ch (c) 2009 Microchip Technology Inc. DS39932C-page 455 PIC18F46J11 FAMILY 26.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB(R) IDE TOOLS The latest versions of Microchip's software tools have been designed to fully support the extended instruction set for the PIC18F46J11 family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is `0', disabling the extended instruction set and Indexed Literal Offset Addressing. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: * A menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project * A command line option * A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information. DS39932C-page 456 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 27.0 DEVELOPMENT SUPPORT 27.1 The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. (c) 2009 Microchip Technology Inc. DS39932C-page 457 PIC18F46J11 FAMILY 27.2 MPASM Assembler 27.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process MPLAB ASM30 Assembler, Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 27.6 MPLAB SIM Software Simulator 27.3 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 27.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS39932C-page 458 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 27.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 27.9 MPLAB ICD 2 In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application. 27.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. 27.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. (c) 2009 Microchip Technology Inc. DS39932C-page 459 PIC18F46J11 FAMILY 27.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. 27.13 Demonstration, Development and Evaluation Boards A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 27.12 PICkit 2 Development Programmer The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers. DS39932C-page 460 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 28.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ........................................... -0.3V to 6.0V Voltage on any combined digital and analog pin with respect to VSS (except VDD)........................ -0.3V to (VDD + 0.3V) Voltage on VDDCORE with respect to VSS................................................................................................... -0.3V to 2.75V Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Maximum output current sunk by any PORTB, PORTC and RA6 I/O pin...............................................................25 mA Maximum output current sunk by any PORTA (except RA6), PORTD and PORTE I/O pin......................................4 mA Maximum output current sourced by any PORTB, PORTC and RA6 I/O pin .........................................................25 mA Maximum output current sourced by any PORTA (except RA6), PORTD and PORTE I/O pin ................................4 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. FIGURE 28-1: PIC18F46J11 FAMILY VDD FREQUENCY GRAPH (INDUSTRIAL) 4.0V 3.6V 3.5V 3.0V PIC18F46J11 Family Valid Operating Range 2.5V 2.15V 2.35V Voltage (VDD) 0 8 MHz 48 MHz (c) 2009 Microchip Technology Inc. DS39932C-page 461 PIC18F46J11 FAMILY FIGURE 28-2: PIC18LF46J11 VDDCORE FREQUENCY GRAPH (INDUSTRIAL)(1) 3.00V 2.75V Voltage (VDDCORE) 2.50V 2.25V 2.00V PIC18LF46J11 Family Valid Operating Range 2.35V 2.75V 0 Note 1: 8 MHz Frequency 48 MHz VDD and VDDCORE must be maintained so that VDDCORE VDD. DS39932C-page 462 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 28.1 DC Characteristics: Supply Voltage PIC18F46J11 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Supply Voltage Min 2.15 2.0 2.0 VDD - 0.3 1.5 -- Typ -- -- -- -- -- -- -- Max 3.6 3.6 2.75 VDD + 0.3 VSS + 0.3 -- 0.7 Units V V V V V V V See Section 4.3 "Power-on Reset (POR)" for details Conditions PIC18F4XJ11, PIC18F2XJ11 PIC18LF4XJ11, PIC18LF2XJ11 PIC18LF4XJ11, PIC18LF2XJ11 PIC18F46J11 Family Param No. D001 D001B D001C D001D D002 D003 Symbol VDD VDDCORE External Supply for Microcontroller Core AVDD AVSS VDR VPOR Analog Supply Voltage RAM Data Retention Voltage(1) VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal VDDCORE Brown-out Reset Voltage VDD Brown-out Reset Voltage Analog Ground Potential VSS - 0.3 D004 SVDD 0.05 -- -- V/ms See Section 4.3 "Power-on Reset (POR)" for details V V PIC18F4XJ11, PIC18F2XJ11 only (not used on "LF" devices) DSBOREN = 1 on "LF" device, or "F" device In Deep Sleep D005 D006 Note 1: VBOR VDSBOR -- -- 2.0 1.8 -- -- This is the limit to which VDDCORE can be lowered in Sleep mode, or during a device Reset, without losing RAM data. (c) 2009 Microchip Technology Inc. DS39932C-page 463 PIC18F46J11 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Typ Max Units Conditions PIC18LFXXJ11 Family PIC18FXXJ11 Family Param No. Device Power-Down Current (IPD)(1) - Sleep mode PIC18LFXXJ11 0.011 0.054 0.51 2.0 PIC18LFXXJ11 0.029 0.11 0.63 2.30 PIC18FXXJ11 2.5 3.1 3.9 5.6 PIC18FXXJ11 4.1 3.3 4.1 6.0 PIC18FXXJ11 1 13 108 428 PIC18FXXJ11 3 28 170 588 Note 1: 1.4 1.4 6 10.2 1.5 1.5 8 12.6 5 5 8 16 7 7 10 19 25 100 250 1000 50 150 389 2000 A A A A A A A A A A A A A A A A nA nA nA nA nA nA nA nA -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C VDD = 3.3V, VDDCORE = 10 F Capacitor VDDCORE = 10 F Capacitor VDD = 3.3V, VDDCORE = 10 F Capacitor VDD = 2.15V, VDDCORE = 10 F Capacitor VDD = 2.5V, VDDCORE = 2.5V Sleep mode, REGSLP = 1 VDD = 2.0V, VDDCORE = 2.0V Power-Down Current (IPD)(1) - Deep Sleep mode VDD = 2.15V, Deep Sleep mode 2: 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39932C-page 464 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Typ Max Units Conditions PIC18LFXXJ11 Family PIC18FXXJ11 Family Param No. Device Supply Current (IDD)(2) PIC18LFXXJ11 5.2 6.2 8.6 14.2 14.2 19.0 16.5 16.5 22.4 77 77 93 84 84 108 1.5 1.5 1.6 1.7 1.7 1.9 2.6 2.6 2.8 2.9 2.9 3.0 A A A A A A A A A A A A mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 2.0V, VDDCORE = 2.0V VDD = 2.5V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F VDD = 2.0V, VDDCORE = 2.0 VDD = 2.5V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F FOSC = 4 MHz, RC_RUN mode, Internal RC Oscillator PIC18LFXXJ11 7.6 8.5 11.3 PIC18FXXJ11 37 48 60 FOSC = 31 kHz, RC_RUN mode, Internal RC Oscillator, INTSRC = 0 PIC18FXXJ11 52 61 70 PIC18LFXXJ11 1.1 1.1 1.2 PIC18LFXXJ11 1.5 1.6 1.6 PIC18FXXJ11 1.3 1.4 1.4 PIC18FXXJ11 1.6 1.6 1.6 Note 1: 2: 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. (c) 2009 Microchip Technology Inc. DS39932C-page 465 PIC18F46J11 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Typ Max Units Conditions PIC18LFXXJ11 Family PIC18FXXJ11 Family Param No. Device Supply Current (IDD)(2) PIC18LFXXJ11 1.9 2.0 2.0 3.6 3.8 3.8 4.8 4.8 4.9 4.2 4.2 4.5 5.1 5.1 5.4 9.4 9.4 17.2 10.5 10.5 19.5 75 75 92 82 82 105 mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 2.0V, VDDCORE = 2.0V VDD = 2.5V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F VDD = 2.0V, VDDCORE = 2.0V VDD = 2.5V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F FOSC = 8 MHz, RC_RUN mode, Internal RC Oscillator PIC18LFXXJ11 2.8 2.8 2.8 PIC18FXXJ11 2.3 2.3 2.4 PIC18FXXJ11 2.8 2.8 2.8 PIC18LFXXJ11 1.9 2.3 4.5 PIC18LFXXJ11 2.4 2.8 5.4 PIC18FXXJ11 33.3 43.8 55.3 PIC18FXXJ11 36.1 44.5 56.3 Note 1: FOSC = 31 kHz, RC_IDLE mode, Internal RC Oscillator, INTSRC = 0 2: 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39932C-page 466 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Typ Max Units Conditions PIC18LFXXJ11 Family PIC18FXXJ11 Family Param No. Device Supply Current (IDD)(2) PIC18LFXXJ11 0.531 0.980 0.571 0.980 0.608 PIC18LFXXJ11 0.625 0.681 0.725 PIC18FXXJ11 0.613 0.680 0.730 PIC18FXXJ11 0.673 0.728 0.779 PIC18LFXXJ11 0.750 0.797 0.839 PIC18LFXXJ11 0.91 0.96 1.01 PIC18FXXJ11 0.87 0.93 0.98 PIC18FXXJ11 0.95 1.01 1.06 Note 1: 1.12 1.14 1.14 1.25 1.21 1.21 1.30 1.27 1.27 1.45 1.4 1.5 1.6 2.4 2.4 2.5 2.1 2.1 2.3 2.6 2.6 2.7 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 2.0V, VDDCORE = 2.0V VDD = 2.5V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F VDD = 2.0V, VDDCORE = 2.0V VDD = 2.5V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F FOSC = 8 MHz, RC_IDLE mode, Internal RC Oscillator FOSC = 4 MHz, RC_IDLE mode, Internal RC Oscillator 2: 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. (c) 2009 Microchip Technology Inc. DS39932C-page 467 PIC18F46J11 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Typ Max Units Conditions PIC18LFXXJ11 Family PIC18FXXJ11 Family Param No. Device Supply Current (IDD)(2) PIC18LFXXJ11 0.879 0.881 0.891 PIC18LFXXJ11 1.35 1.30 1.27 PIC18FXXJ11 1.09 1.09 1.11 PIC18FXXJ11 1.36 1.36 1.41 PIC18LFXXJ11 10.9 10.6 10.6 PIC18FXXJ11 12.9 12.8 12.7 Note 1: 1.25 1.25 1.36 1.70 1.70 1.82 1.60 1.60 1.70 1.95 1.89 1.92 14.8 14.8 15.2 23.2 22.7 22.7 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 2.0V, VDDCORE = 2.0V VDD = 2.0V, VDDCORE = 2.0V FOSC = 4 MHz, PRI_RUN mode, EC Oscillator VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F VDD = 2.5V, VDDCORE = 2.5V FOSC = 48 MHz, PRI_RUN mode, EC Oscillator VDD = 3.3V, VDDCORE = 10 F 2: 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39932C-page 468 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Typ Max Units Conditions PIC18LFXXJ11 Family PIC18FXXJ11 Family Param No. Device Supply Current (IDD)(2) PIC18LFXXJ11 0.285 0.700 0.300 0.700 0.336 0.750 PIC18LFXXJ11 0.372 0.397 0.495 1.00 1.00 1.10 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 2.0V, VDDCORE = 2.0V VDD = 2.5V, VDDCORE = 2.5V FOSC = 4 MHz, PRI_IDLE mode, EC Oscillator VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F VDD = 2.5V, VDDCORE = 2.5V VDD = 3.3V, VDDCORE = 10 F PIC18FXXJ11 0.357 0.850 0.383 0.850 0.407 0.900 PIC18FXXJ11 0.449 0.488 0.554 PIC18LFXXJ11 4.5 4.5 4.6 PIC18FXXJ11 4.9 5.0 5.1 Note 1: 1.30 1.20 1.20 6.5 6.5 6.5 12.4 11.5 11.5 FOSC = 48 MHz PRI_IDLE mode, EC oscillator 2: 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. (c) 2009 Microchip Technology Inc. DS39932C-page 469 PIC18F46J11 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Typ 5.2 5.1 5.1 PIC18FXXJ11 5.3 5.2 5.2 PIC18LFXXJ11 9.3 9.2 9.0 PIC18FXXJ11 9.7 9.6 9.6 PIC18LFXXJ11 12.4 12.2 12.1 PIC18FXXJ11 14.3 14.2 14.2 Note 1: Max 6.5 6.4 6.4 7.5 7.4 7.4 12.0 11.8 11.8 17.5 17.2 17.2 13.5 13.5 13.9 24.1 23.0 23.0 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C Conditions VDD = 2.5V, VDDCORE = 2.5V VDD = 3.3V, VDDCORE = 10 F VDD = 2.5V, VDDCORE = 2.5V VDD = 3.3V, VDDCORE = 10 F VDD = 2.5V, VDDCORE = 2.5V VDD = 3.3V, VDDCORE = 10 F PIC18LFXXJ11 Family PIC18FXXJ11 Family Param No. Device PIC18LFXXJ11 FOSC = 16 MHz (PRI_RUN mode, 4 MHz Internal Oscillator with PLL FOSC = 32 MHz, PRI_RUN mode, 8 MHz Internal Oscillator with PLL FOSC = 48 MHz, PRI_RUN mode, 12 MHz External Oscillator with PLL 2: 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39932C-page 470 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Typ Max 45 45 61 95 95 105 110 110 150 31 31 50 87 89 97 100 100 140 Units A A A A A A A A A A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C Conditions VDD = 2.5V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F VDD = 2.5V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F FOSC = 32 kHz(3) SEC_IDLE mode, LPT1OSC = 0 FOSC = 32 kHz(3) SEC_RUN mode, LPT1OSC = 0 PIC18LFXXJ11 Family PIC18FXXJ11 Family Param No. Device PIC18LFXXJ11 12.5 11.7 5.2 PIC18FXXJ11 40.2 50.2 61.9 PIC18LFXXJ11 44.4 53.1 55.8 PIC18FXXJ11 4.5 3.8 4.1 PIC18FXXJ11 34.7 44.6 56.5 PIC18LFXXJ11 37.3 45.7 54.6 Note 1: 2: 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. (c) 2009 Microchip Technology Inc. DS39932C-page 471 PIC18F46J11 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Typ Max Units Conditions PIC18LFXXJ11 Family PIC18FXXJ11 Family Param No. D022 (IWDT) Device D022B (IHLVD) Module Differential Currents (IWDT, IOSCB, IAD) 8 A -40C Watchdog Timer 0.86 0.97 8 A +25C 0.98 10.4 A +85C 0.71 7 A -40C 0.82 7 A +25C 0.65 10 A +85C 1.54 12.1 A -40C 1.33 12.1 A +25C 1.16 13.6 A +85C 8 A -40C High/Low-Voltage Detect 3.9 4.7 8 A +25C 5.4 9 A +85C 2.7 6 A -40C 3.2 6 A +25C 3.6 8 A +85C 3.5 9 A -40C 4.1 9 A +25C 4.5 12 A +85C VDD = 2.5V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F VDD = 2.5V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 10 F VDD = 3.3V, VDDCORE = 10 F PIC18LFXXJ11 PIC18FXXJ11 PIC18FXXJ11 PIC18LFXXJ11 PIC18FXXJ11 PIC18FXXJ11 D025 (IOSCB) Note 1: 2: 3: Real-Time Clock/Calendar 0.67 4.0 A -40C 4.5 A +25C with Low-Power 0.83 VDD = 2.15V, VDDCORE = 10 F 4.5 A +60C Timer1 Oscillator 0.95 1.10 4.5 A +85C 0.75 4.5 A -40C PIC18FXXJ11 VDD = 2.5V, 0.92 5.0 A +25C 32.768 kHz, T1OSCEN = 1, VDDCORE = 10 F 1.04 5.0 A +60C LPT1OSC = 0 1.21 5.0 A +85C 0.94 6.5 A -40C VDD = 3.3V, 1.11 6.5 A +25C VDDCORE = 10 F 1.24 8.0 A +60C 1.43 8.0 A +85C The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39932C-page 472 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F46J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Typ Max Units Conditions PIC18LFXXJ11 Family PIC18FXXJ11 Family Param No. D026 (IAD) Device Note 1: 2: 3: A/D Converter 3.00 10 A -40C PIC18LFXXJ11 VDD = 2.5V, 3.00 10 A +25C A/D on, not converting VDDCORE = 2.5V 3.00 10 A +85C 3.00 10 A -40C VDD = 2.15V, 3.00 10 A +25C VDDCORE = 10 F PIC18FXXJ11 3.00 10 A +85C A/D on, not converting 3.20 11 A -40C VDD = 3.3V, 3.20 11 A +25C VDDCORE = 10 F 3.20 11 A +85C The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. (c) 2009 Microchip Technology Inc. DS39932C-page 473 PIC18F46J11 FAMILY 28.3 DC Characteristics: PIC18F46J50 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Input Low Voltage All I/O ports: D030 D030A D031 D032 D033 D033A D034 VIH with Schmitt Trigger Buffer MCLR OSC1 OSC1 T1CKI Input High Voltage I/O Ports with non 5.5V Tolerance:(4) D040 D040A D041 Dxxx DxxxA Dxxx D042 D043 D043A D044 IIL D060 D060A D061 D063 IPU D070 Note 1: IPURB with Schmitt Trigger Buffer MCLR OSC1 OSC1 T1CKI Input Leakage Current(1,2) -- -- -- -- 80 0.2 0.2 0.2 0.2 400 A A A A A VSS VPIN VDD, Pin at high-impedance 3.3V VPIN 5.5V, Pin at high-impedance Vss VPIN VDD Vss VPIN VDD VDD = 3.3V, VPIN = VSS I/O Ports with non 5.5V Tolerance:(4) I/O Ports with 5.5V Tolerance:(4) MCLR OSC1 Weak Pull-up Current PORTB, PORTD(3) and PORTE(3) Weak Pull-up Current with Schmitt Trigger Buffer I/O Ports with 5.5V Tolerance:(4) with TTL Buffer 0.25 VDD + 0.8V 2.0 0.8 VDD 0.8 VDD 0.7 VDD 0.8 VDD 1.6 5.5 5.5 5.5 5.5 VDD VDD VDD V V V V V V V HS, HSPLL modes EC, ECPLL modes VDD < 3.3V 3.3V VDD 3.6V with TTL Buffer 0.25 VDD + 0.8V 2.0 0.8 VDD VDD VDD VDD V V V VDD < 3.3V 3.3V VDD 3.6V with TTL Buffer VSS -- VSS VSS VSS VSS VSS 0.15 VDD 0.8 0.2 VDD 0.2 VDD 0.3 VDD 0.2 VDD 0.2 VDD V V V V V V V HS, HSPLL modes EC, ECPLL modes 3.3V VDD 3.6V Min Max Units Conditions DC CHARACTERISTICS Param Symbol No. VIL 2: 3: 4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Only available in 44-pin devices. Refer to Table 9-2 for the pins that have corresponding tolerance limits. DS39932C-page 474 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 28.3 DC Characteristics: PIC18F46J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Output Low Voltage I/O Ports: PORTA (Except RA6), PORTD, PORTE PORTB, PORTC, RA6 VOH D090 Output High Voltage I/O Ports: PORTA (Except RA6), PORTD, PORTE PORTB, PORTC, RA6 Capacitive Loading Specs on Output Pins D101 D102 Note 1: CIO CB All I/O Pins and OSC2 SCLx, SDAx -- -- 50 400 pF pF To meet the AC Timing Specifications I2CTM Specification 2.4 2.4 -- -- V V IOH = -2, VDD = 3.3V, -40C to +85C IOH = -6 mA, VDD = 3.3V, -40C to +85C -- -- 0.4 0.4 V V IOL = 2 mA, VDD = 3.3V, -40C to +85C IOL = 8.5 mA, VDD = 3.3V, -40C to +85C Min Max Units Conditions DC CHARACTERISTICS Param Symbol No. VOL D080 2: 3: 4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Only available in 44-pin devices. Refer to Table 9-2 for the pins that have corresponding tolerance limits. (c) 2009 Microchip Technology Inc. DS39932C-page 475 PIC18F46J11 FAMILY TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Ultra Low-Power Wake-up Current Min -- Typ 60 Max -- Units nA Conditions DC CHARACTERISTICS Param Sym No. D100 IULP Net of I/O leakage and current sink at 1.6V on pin, VDD = 3.3V See Application Note AN879, "Using the Microchip Ultra Low-Power Wake-up Module" (DS00879) -40C to +85C VMIN = Minimum operating voltage Program Flash Memory D130 D131 EP VPR Cell Endurance VDDcore for Read 10K VMIN 2.25 -- -- 20 -- -- -- -- 2.8 33.0 -- 3 -- 2.75 2.75 -- -- -- -- E/W V V ms ms Year mA Provided no other specifications are violated 64 bytes D132B VPEW VDDCORE for Self-Timed Erase or Write D133A TIW D133B TIE D134 D135 Self-Timed Write Cycle Time Self-Timed Block Erase Cycle Time TRETD Characteristic Retention IDDP Supply Current during Programming Data in "Typ" column is at 3.3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 28-2: Param No. D300 D301 D302 300 301 Note 1: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40C < TA < +85C (unless otherwise stated) Sym VIOFF VICM VIRV CMRR TRESP Characteristics Input Offset Voltage Input Common Mode Voltage Internal Reference Voltage Common Mode Rejection Ratio Response Time(1) Min -- 0 0.57 55 -- -- Typ 5 -- 0.60 -- 150 -- Max 25 VDD 0.63 -- 400 10 Units mV V V dB ns s Comments TMC2OV Comparator Mode Change to Output Valid Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. TABLE 28-3: CTMU CURRENT SOURCE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic CTMU Current Source, Base Range CTMU Current Source, 10x Range CTMU Current Source, 100x Range Min -- -- -- Typ(1) 550 5.5 55 Max -- -- -- Units nA A A Conditions CTMUICON<1:0> = 01 CTMUICON<1:0> = 10 CTMUICON<1:0> = 11 DC CHARACTERISTICS Param No. Sym IOUT1 IOUT2 IOUT3 Note 1: Nominal value at center point of current trim range (CTMUICON<7:2> = 000000). DS39932C-page 476 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 28-4: Param No. D310 D311 D312 310 Note 1: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40C < TA < +85C (unless otherwise stated) Sym VRES VRAA VRUR TSET Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time(1) Min VDD/24 -- -- -- Typ -- -- 2k -- Max VDD/32 1/2 -- 10 Units LSb LSb s Comments Settling time measured while CVRR = 1 and CVR<3:0> bits transition from `0000' to `1111'. TABLE 28-5: Param No. INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40C < TA < +85C (unless otherwise stated) Sym Characteristics Min 2.35 5.4 Typ 2.5 10 Max 2.7 18 Units V F Comments Regulator enabled, VDD = 3.0V ESR < 3 recommended ESR < 5 required VRGOUT Regulator Output Voltage CEFC Note 1: External Filter Capacitor Value(1) CEFC applies for PIC18F devices in the family. For PIC18LF devices in the family, there is no specific minimum or maximum capacitance for VDDCORE, although proper supply rail bypassing should still be used. (c) 2009 Microchip Technology Inc. DS39932C-page 477 PIC18F46J11 FAMILY FIGURE 28-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD VHLVD For VDIRMAG = 1: (LVDIF set by hardware) (LVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD LVDIF TABLE 28-6: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param Symbol No. D420 Characteristic HLVD Voltage on VDD HLVDL<3:0> = 1000 Transition High-toHLVDL<3:0> = 1001 Low HLVDL<3:0> = 1010 HLVDL<3:0> = 1011 HLVDL<3:0> = 1100 HLVDL<3:0> = 1101 HLVDL<3:0> = 1110 D421 D422 TIRVST TLVD Time for Internal Reference Voltage to become Stable High/Low-Voltage Detect Pulse Width Min 2.33 2.47 2.66 2.76 2.85 2.97 3.23 -- 200 Typ 2.45 2.60 2.80 2.90 3.00 3.13 3.40 20 -- Max 2.57 2.73 2.94 3.05 3.15 3.29 3.57 -- -- Units V V V V V V V s s Conditions DS39932C-page 478 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 28.4 28.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition 3. TCC:ST 4. Ts T (I2C specifications only) (I2C specifications only) Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T13CKI WR P R V Z High Low Period Rise Valid High-impedance High Low SU STO Setup Stop condition (c) 2009 Microchip Technology Inc. DS39932C-page 479 PIC18F46J11 FAMILY 28.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 28-7 apply to all timing specifications unless otherwise noted. Figure 28-4 specifies the load conditions for the timing specifications. TABLE 28-7: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Operating voltage VDD range as described in Section 28.1 and Section 28.3. AC CHARACTERISTICS FIGURE 28-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 VDD/2 RL Pin VSS Pin VSS CL RL = 464 CL = 50 pF CL = 15 pF for all pins except OSC2/CLKO/RA6 and including D and E outputs as ports for OSC2/CLKO/RA6 CL Load Condition 2 28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 FIGURE 28-5: OSC1 1 2 3 3 4 4 CLKO DS39932C-page 480 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 28-8: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic External CLKI Frequency(1) Oscillator Frequency(1) Min DC 4 4 4 20.8 83.3 Oscillator Period(1) 62.5 83.3 83.3 10 -- Max 48 12 16 12 -- -- 250 250 DC -- 7.5 ns ns ns ns ns MHz Units MHz Conditions EC Oscillator mode ECPLL Oscillator mode HS Oscillator mode HSPLL Oscillator mode EC Oscillator mode ECPLL Oscillator mode HS Oscillator mode HSPLL Oscillator mode TCY = 4/FOSC, Industrial EC Oscillator mode EC Oscillator mode Symbol FOSC 1 TOSC External CLKI Period(1) 2 3 4 Note 1: TCY TOSL, TOSH TOSR, TOSF Instruction Cycle Time(1) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. TABLE 28-9: Param No. F10 F11 F12 Sym PLL CLOCK TIMING SPECIFICATIONS Characteristic Min 4 16 -- Typ -- -- -- Max 12 48 2 Units MHz MHz ms Conditions FPLLIN PLL Input Frequency Range FPLLO PLL Output Frequency (4x FPLLIN) trc PLL Start-up Time (lock time) Data in "Typ" column is at 3.3V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 28-10: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES) Param No. Device Min Typ Max Units Conditions INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1) All Devices -1 -1 +/-0.15 +/-0.25 +1 +1 % % 0C to +85C -40C to +85C VDD = 2.0-3.3V VDD = 2.0-3.6V, VDDCORE = 2.0-2.7V VDD = 2.0-3.6V, VDDCORE = 2.0-2.7V INTRC Accuracy @ Freq = 31 kHz(1) All Devices Note 1: 20.3 -- 42.2 kHz -40C to +85C The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given time. When INTSRC (OSCTUNE<7>) is `1', use the INTOSC accuracy specification. When INTSRC is `0', use the INTRC accuracy specification. (c) 2009 Microchip Technology Inc. DS39932C-page 481 PIC18F46J11 FAMILY FIGURE 28-6: CLKO AND I/O TIMING Q4 OSC1 10 CLKO 13 14 I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 Note: Refer to Figure 28-4 for load conditions. 15 New Value 19 18 12 16 11 Q1 Q2 Q3 TABLE 28-11: CLKO AND I/O TIMING REQUIREMENTS Param No. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Symbol Characteristic Min -- -- -- -- -- 0.25 TCY + 25 0 -- 100 0 -- -- TCY TCY Typ 75 75 15 15 -- -- -- 50 -- -- -- -- -- -- Max 200 200 30 30 0.5 TCY + 20 -- -- 150 -- -- 6 5 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) TOSH2CKL OSC1 to CLKO TOSH2CKH OSC1 to CLKO TCKR TCKF TCKL2IOV TCKH2IOI TOSH2IOI CLKO Rise Time CLKO Fall Time CLKO to Port Out Valid Port In Hold after CLKO OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time) TIOV2CKH Port In Valid before CLKO TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) TIOR TIOF TINP TRBP Port Output Rise Time Port Output Fall Time INTx pin High or Low Time RB7:RB4 Change INTx High or Low Time These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC. DS39932C-page 482 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 28-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR Internal POR PWRT Time-out Oscillator Time-out Internal Reset Watchdog Timer Reset 34 I/O pins Note: Refer to Figure 28-4 for load conditions. 33 32 30 31 34 TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. 30 31 32 33 34 36 37 38 Note 1: 2: TMCL TWDT TOST TPWRT TIOZ TIRVST TLVD TCSD Characteristic MCLR Pulse-Width (low) Watchdog Timer Time-out Period (no postscaler) Oscillator Start-up Timer Period Power-up Timer Period I/O High-Impedance from MCLR Low or Watchdog Timer Reset Time for Internal Reference Voltage to become Stable High/Low-Voltage Detect Pulse Width CPU Start-up Time Min 2 2.8 1024 TOSC -- -- -- -- -- Typ -- 4.0 -- 1.0 -- 20 200 200 Max -- 5.3 1024 TOSC -- 3 TCY + 2 -- -- -- Units s ms -- ms s s s s (Note 2) (Note 1) -- -- Conditions -- -- TOSC = OSC1 period -- The maximum TIOZ is the lesser of (3 TCY + 2 s) or 700 s. MCLR rising edge to code execution, assuming TPWRT (and TOST if applicable) has already expired. (c) 2009 Microchip Technology Inc. DS39932C-page 483 PIC18F46J11 FAMILY FIGURE 28-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 42 T1OSO/T1CKI 41 45 47 TMR0 or TMR1 Note: Refer to Figure 28-4 for load conditions. 46 48 TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. 40 41 42 Symbol TT0H TT0L TT0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No prescaler With prescaler No prescaler With prescaler No prescaler With prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 10 Greater of: 20 ns or (TCY + 40)/N 0.5 TCY + 20 10 30 0.5 TCY + 5 10 30 Greater of: 20 ns or (TCY + 40)/N 83 DC 2 TOSC Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (1, 2, 4,..., 256) Conditions 45 TT1H T1CKI/T3CKI Synchronous, no prescaler High Time Synchronous, with prescaler Asynchronous T1CKI/T3CKI Synchronous, no prescaler Low Time Synchronous, with prescaler Asynchronous T1CKI/T3CKI Synchronous Input Period Asynchronous -- -- -- -- -- -- -- ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8) 46 TT1L 47 TT1P -- 12 7 TOSC ns MHz -- FT1 48 T1CKI Input Frequency Range(1) TCKE2TMRI Delay from External T1CKI Clock Edge to Timer Increment Note 1: The Timer1 oscillator is designed to drive 32.768 kHz crystals. When T1CKI is used as a digital input, frequencies up to 12 MHz are supported. DS39932C-page 484 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 28-9: ENHANCED CAPTURE/COMPARE/PWM TIMINGS ECCPx (Capture Mode) 50 52 51 ECCPx (Compare or PWM Mode) 53 Note: Refer to Figure 28-4 for load conditions. 54 TABLE 28-14: ENHANCED CAPTURE/COMPARE/PWM REQUIREMENTS Param Symbol No. 50 51 52 53 54 TCCL TCCH TCCP TCCR TCCF Characteristic ECCPx Input Low Time ECCPx Input High Time ECCPx Input Period ECCPx Output Fall Time ECCPx Output Fall Time No prescaler With prescaler No prescaler With prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 3 TCY + 40 N -- -- Max -- -- -- -- -- 25 25 Units ns ns ns ns ns ns ns N = prescale value (1, 4 or 16) Conditions (c) 2009 Microchip Technology Inc. DS39932C-page 485 PIC18F46J11 FAMILY FIGURE 28-10: PARALLEL MASTER PORT READ TIMING DIAGRAM Q1 System Clock PMA<13:18> Address Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 PMD<7:0> Address<7:0> PM2 PM6 PM3 Data PM7 PM5 PMRD PMWR PMALL/PMALH PM1 PMCS<2:1> Operating Conditions: 2.0V < VDD < 3.6V, -40C < TA < +85C unless otherwise stated. TABLE 28-15: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Param. No PM1 PM2 PM3 PM5 PM6 PM7 Symbol Characteristics PMALL/PMALH Pulse Width Address Out Valid to PMALL/PMALH Invalid (address setup time) PMALL/PMALH Invalid to Address Out Invalid (address hold time) PMRD Pulse Width PMRD or PMENB Active to Data In Valid (data setup time) PMRD or PMENB Inactive to Data In Invalid (data hold time) Min -- -- -- -- -- -- Typ 0.5 TCY 0.75 TCY 0.25 TCY 0.5 TCY -- -- Max -- -- -- -- -- -- Units ns ns ns ns ns ns DS39932C-page 486 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 28-11: PARALLEL MASTER PORT WRITE TIMING DIAGRAM Q1 System Clock PMA<13:18> Address Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 PMD<7:0> Address<7:0> Data PM12 PM13 PMRD PMWR PM11 PMALL/ PMALH PMCS<2:1> PM16 Note: Operating Conditions: 2.0V < VDD < 3.6V, -40C < TA < +85C unless otherwise stated. TABLE 28-16: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Param. No PM11 PM12 PM13 PM16 Symbol Characteristics PMWR Pulse Width Data Out Valid before PMWR or PMENB goes Inactive (data setup time) PMWR or PMEMB Invalid to Data Out Invalid (data hold time) PMCS Pulse Width Min -- -- -- TCY - 5 Typ 0.5 TCY -- -- -- Max -- -- -- -- Units ns ns ns ns (c) 2009 Microchip Technology Inc. DS39932C-page 487 PIC18F46J11 FAMILY FIGURE 28-12: SSx EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCKx (CKP = 0) 78 SCKx (CKP = 1) 79 SDOx MSb 75, 76 SDIx MSb In 74 73 Note: Refer to Figure 28-4 for load conditions. bit 6 - - - - 1 LSb In bit 6 - - - - - - 1 78 LSb 79 TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. 73 Symbol TDIV2SCH, TDIV2SCL Characteristic Setup Time of SDIx Data Input to SCKx Edge Min 35 100 73A 74 TB2B TSCH2DIL, TSCL2DIL TDOR TDOF TSCR TSCF Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 Hold Time of SDIx Data Input to SCKx Edge 1.5 TCY + 40 30 83 75 76 78 79 SDOx Data Output Rise Time SDOx Data Output Fall Time SCKx Output Rise Time (Master mode) SCKx Output Fall Time (Master mode) -- -- -- -- Max Units -- -- -- -- -- 25 25 25 25 ns ns ns ns ns ns ns ns ns VDD = 3.3V, VDDCORE = 2.5V VDD = 2.15V PORTB or PORTC PORTB or PORTC PORTB or PORTC PORTB or PORTC Conditions VDD = 3.3V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 2.15V DS39932C-page 488 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 28-13: SSx 81 SCKx (CKP = 0) 79 EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 73 SCKx (CKP = 1) 78 MSb 75, 76 SDIx MSb In 74 Note: Refer to Figure 28-4 for load conditions. bit 6 - - - - 1 LSb In bit 6 - - - - - - 1 LSb SDOx TABLE 28-18: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. 73 Symbol TDIV2SCH, TDIV2SCL Characteristic Setup Time of SDIx Data Input to SCKx Edge Min 35 100 74 TSCH2DIL, TSCL2DIL TDOR TDOF TSCR TSCF Hold Time of SDIx Data Input to SCKx Edge 30 83 75 76 78 79 81 SDOx Data Output Rise Time SDOx Data Output Fall Time SCKx Output Rise Time (Master mode) SCKx Output Fall Time (Master mode) -- -- -- -- TCY Max Units -- -- -- -- 25 25 25 25 -- ns ns ns ns ns ns ns ns ns Conditions VDD = 3.3V, VDDCORE = 2.5V VDD = 2.15V, VDDCORE = 2.15V VDD = 3.3V, VDDCORE = 2.5V VDD = 2.15V PORTB or PORTC PORTB or PORTC PORTB or PORTC PORTB or PORTC TDOV2SCH, SDOx Data Output Setup to SCKx Edge TDOV2SCL (c) 2009 Microchip Technology Inc. DS39932C-page 489 PIC18F46J11 FAMILY FIGURE 28-14: SSx 70 SCKx (CKP = 0) 71 72 83 EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SCKx (CKP = 1) 80 SDOx MSb 75, 76 SDIx SDI MSb In 74 73 Note: Refer to Figure 28-4 for load conditions. bit 6 - - - - 1 LSb In bit 6 - - - - - - 1 LSb 77 TABLE 28-19: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No. 70 70A 71 71A 72 72A 73 73A 74 TSCL Symbol Characteristic Min 3 TCY 3 TCY Continuous Single byte Continuous Single byte 1.25 TCY + 30 40 1.25 TCY + 30 40 25 1.5 TCY + 40 35 100 75 76 77 80 TDOR TDOF SDOx Data Output Rise Time SDOx Data Output Fall Time -- -- 10 -- Max Units -- -- -- -- -- -- -- -- -- -- 25 25 70 50 100 83 Note 1: 2: TSCH2SSH, SSx after SCKx Edge TSCL2SSH Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used. 1.5 TCY + 40 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD = 3.3V, VDDCORE = 2.5V VDD = 2.15V (Note 2) VDD = 3.3V, VDDCORE = 2.5V VDD = 2.15V PORTB or PORTC PORTB or PORTC (Note 1) (Note 1) Conditions TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL TSSL2WB TSCH SSx to Write to SSPxBUF SCKx Input High Time (Slave mode) SCKx Input Low Time (Slave mode) TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge TDIV2SCL TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge TSCL2DIL TSSH2DOZ SSx to SDOx Output High-Impedance TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV DS39932C-page 490 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY FIGURE 28-15: SSx 70 83 71 73 SCKx (CKP = 1) 80 MSb 75, 76 SDIx SDI MSb In 74 Note: Refer to Figure 28-4 for load conditions. bit 6 - - - - 1 LSb In bit 6 - - - - - - 1 LSb 77 72 EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SCKx (CKP = 0) SDOx TABLE 28-20: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. 70 70A 71 71A 72 72A 73 73A 74 Symbol TSSL2SCH, TSSL2SCL TSSL2WB TSCH TSCL TDIV2SCH, TDIV2SCL TB2B TSCH2DIL, TSCL2DIL TDOR TDOF TSSH2DOZ TSCR TSCF TSCH2DOV, TSCL2DOV Characteristic SSx to SCKx or SCKx Input SSx to Write to SSPxBUF SCKx Input High Time (Slave mode) Min 3 TCY 3 TCY 1.25 TCY + 30 40 1.25 TCY + 30 40 25 1.5 TCY + 40 35 100 -- -- 10 -- -- -- -- TCY -- 1.5 TCY + 40 Max -- -- -- -- -- -- -- -- -- -- 25 25 70 25 25 50 100 -- 50 -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions Continuous Single byte SCKx Input Low Time Continuous (Slave mode) Single byte Setup Time of SDIx Data Input to SCKx Edge Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 Hold Time of SDIx Data Input to SCKx Edge (Note 1) (Note 1) (Note 2) VDD = 3.3V, VDDCORE = 2.5V VDD = 2.15V 75 76 77 78 79 80 SDOx Data Output Rise Time SDOx Data Output Fall Time SSx to SDOx Output High-Impedance SCKx Output Rise Time (Master mode) SCKx Output Fall Time (Master mode) SDOx Data Output Valid after SCKx Edge VDD = 3.3V, VDDCORE = 2.5V VDD = 2.15V 81 82 83 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TDOV2SCL TSSL2DOV SDOx Data Output Valid after SSx Edge TSCH2SSH, SSx after SCKx Edge TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. (c) 2009 Microchip Technology Inc. DS39932C-page 491 PIC18F46J11 FAMILY FIGURE 28-16: I2CTM BUS START/STOP BITS TIMING SCLx 90 SDAx 91 92 93 Start Condition Stop Condition Note: Refer to Figure 28-4 for load conditions. TABLE 28-21: I2CTM BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No. 90 91 92 93 TSU:STA THD:STA TSU:STO Setup Time Start Condition Hold Time Stop Condition Setup Time THD:STO Stop Condition Hold Time Characteristic Start Condition 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Max -- -- -- -- -- -- -- -- ns ns ns Units ns Conditions Only relevant for Repeated Start condition After this period, the first clock pulse is generated FIGURE 28-17: I2CTM BUS DATA TIMING 103 100 101 102 SCLx 90 91 106 107 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure 28-4 for load conditions. DS39932C-page 492 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 28-22: I2CTM BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH Characteristic Clock High Time 100 kHz mode 400 kHz mode MSSP modules 101 TLOW Clock Low Time 100 kHz mode 400 kHz mode MSSP modules 102 TR SDAx and SCLx Rise Time 100 kHz mode 400 kHz mode 103 TF SDAx and SCLx Fall Time 100 kHz mode 400 kHz mode 90 91 106 107 92 109 110 TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF Start Condition Setup Time 100 kHz mode 400 kHz mode Start Condition Hold Time Data Input Hold Time Data Input Setup Time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Stop Condition Setup Time 100 kHz mode 400 kHz mode Output Valid from Clock Bus Free Time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode D102 Note 1: 2: CB Bus Capacitive Loading Min 4.0 0.6 1.5 TCY 4.7 1.3 1.5 TCY -- 20 + 0.1 CB -- 20 + 0.1 CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated CB is specified to be from 10 to 400 pF s s Units s s Conditions As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. A Fast mode I2CTM bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released. (c) 2009 Microchip Technology Inc. DS39932C-page 493 PIC18F46J11 FAMILY FIGURE 28-18: MSSPx I2CTM BUS START/STOP BITS TIMING WAVEFORMS SCLx 90 SDAx 91 92 93 Start Condition Note: Refer to Figure 28-4 for load conditions. Stop Condition TABLE 28-23: MSSPx I2CTM BUS START/STOP BITS REQUIREMENTS Param. Symbol No. 90 TSU:STA Characteristic Start Condition Setup Time 91 THD:STA Start Condition Hold Time 92 TSU:STO Stop Condition Setup Time 93 THD:STO Stop Condition Hold Time Note 1: 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) Max -- -- -- -- -- -- -- -- -- -- -- -- ns -- ns ns Units ns Conditions Only relevant for Repeated Start condition After this period, the first clock pulse is generated -- Maximum pin capacitance = 10 pF for all I2CTM pins. FIGURE 28-19: MSSPx I2CTM BUS DATA TIMING 103 100 101 102 SCLx SDAx In 90 91 106 107 92 109 109 110 SDAx Out Note: Refer to Figure 28-4 for load conditions. DS39932C-page 494 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 28-24: MSSPx I2CTM BUS DATA REQUIREMENTS Param. Symbol No. 100 THIGH Characteristic Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(1) 101 TLOW Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode 102 TR (1) Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 0 0 TBD 250 100 TBD 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- -- -- 4.7 1.3 TBD -- Max -- -- -- -- -- -- 1000 300 300 300 300 100 -- -- -- -- -- -- -- 0.9 -- -- -- -- -- -- -- 3500 1000 -- -- -- -- 400 Units ms ms ms ms ms ms ns ns ns ns ns ns ms ms ms ms ms ms ns ms ns ns ns ns ms ms ms ns ns ns ms ms ms pF Conditions SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode(1) SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode(1) Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode (1) CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated 103 TF 90 TSU:STA 91 THD:STA Start Condition Hold Time THD:DAT Data Input Hold Time TSU:DAT Data Input Setup Time 106 107 (Note 2) 92 TSU:STO Stop Condition Setup Time TAA Output Valid from Clock Bus Free Time 109 110 TBUF 100 kHz mode 400 kHz mode 1 MHz mode(1) Time the bus must be free before a new transmission can start D102 Note 1: 2: CB Bus Capacitive Loading Maximum pin capacitance = 10 pF for all I2CTM pins. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCLx line is released. (c) 2009 Microchip Technology Inc. DS39932C-page 495 PIC18F46J11 FAMILY FIGURE 28-20: TXx/CKx pin RXx/DTx pin 120 Note: Refer to Figure 28-4 for load conditions. EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING 121 121 122 TABLE 28-25: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. 120 121 122 Symbol Characteristic Min Max Units Conditions TCKH2DTV Sync XMIT (Master and Slave) Clock High to Data Out Valid TCKRF TDTRF Clock Out Rise Time and Fall Time (Master mode) Data Out Rise Time and Fall Time -- -- -- 40 20 20 ns ns ns FIGURE 28-21: TXx/CKx pin RXx/DTx pin EUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING 125 126 Note: Refer to Figure 28-4 for load conditions. TABLE 28-26: EUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. 125 126 Symbol Characteristic Min Max Units Conditions TDTV2CKL Sync RCV (Master and Slave) Data Hold before CKx (DTx hold time) TCKL2DTL Data Hold after CKx (DTx hold time) 10 15 -- -- ns ns DS39932C-page 496 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 28-27: A/D CONVERTER CHARACTERISTICS: PIC18F46J11 FAMILY (INDUSTRIAL) Param Symbol No. A01 A03 A04 A06 A07 A10 A20 A21 A22 A25 A30 A50 VREF VREFH VREFL VAIN ZAIN IREF NR EIL EDL EOFF EGN Characteristic Resolution Integral Linearity Error Differential Linearity Error Offset Error Gain Error Monotonicity Reference Voltage Range (VREFH - VREFL) Reference Voltage High Reference Voltage Low Analog Input Voltage Recommended Impedance of Analog Voltage Source VREF Input Current(2) 2.0 3 VSS VSS - 0.3V VREFL -- -- -- Min -- -- -- -- -- Typ -- -- -- -- -- Guaranteed(1) -- -- -- -- -- -- -- -- -- -- VREFH VDD - 3.0V VREFH 2.5 5 150 Max 10 <1 <1 <3 <3.5 Units bit Conditions VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V -- V V V V V k A A During VAIN acquisition. During A/D conversion cycle. VSS VAIN VREF VDD < 3.0V VDD 3.0V Note 1: 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. VREFH current is from RA3/AN3/VREF+/C1INB pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF-/CVREF/C2INB pin or VSS, whichever is selected as the VREFL source. FIGURE 28-22: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) Q4 A/D CLK 132 ... ... 131 130 A/D DATA 9 8 7 2 1 0 ADRES ADIF GO OLD_DATA NEW_DATA TCY (Note 1) DONE SAMPLE SAMPLING STOPPED Note 1: 2: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. (c) 2009 Microchip Technology Inc. DS39932C-page 497 PIC18F46J11 FAMILY TABLE 28-28: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 131 132 135 137 Note 1: 2: 3: 4: TAD TCNV TACQ TSWC TDIS Characteristic A/D Clock Period Conversion Time (not including acquisition time)(2) Acquisition Time(3) Switching Time from Convert Sample Discharge Time Min 0.7 11 -- 1.4 -- 0.2 Max 25.0(1) 12 1 -- (Note 4) -- s Units s TAD s s Conditions TOSC based, VREF 3.0V A/D RC Mode -40C to +85C The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. ADRES registers may be read on the following TCY cycle. The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. On the following cycle of the device clock. DS39932C-page 498 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 29.0 29.1 PACKAGING INFORMATION Package Marking Information 28-Lead SPDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F26J11 -I/SP e3 0910017 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Example PIC18F26J11 /SS e3 0910017 28-Lead SOIC (.300") XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F26J11/SO e3 0910017 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN 18F26J11 /ML e3 0910017 Legend: XX...X Y YY WW NNN * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2009 Microchip Technology Inc. DS39932C-page 499 PIC18F46J11 FAMILY 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 18F46J11 -I/ML e3 0910017 44-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 18F46J11 -I/PT e3 0910017 DS39932C-page 500 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 29.2 Package Details The following sections give the technical details of the packages. /HDG 6NLQQ\ 3ODVWLF 'XDO ,Q /LQH 63 1RWH PLO %RG\ >63',3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 23 D E A A2 L c eB A1 b1 b e 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 7RS WR 6HDWLQJ 3ODQH 0ROGHG 3DFNDJH 7KLFNQHVV %DVH WR 6HDWLQJ 3ODQH 6KRXOGHU WR 6KRXOGHU :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK 7LS WR 6HDWLQJ 3ODQH /HDG 7KLFNQHVV 8SSHU /HDG :LGWK /RZHU /HDG :LGWK 2YHUDOO 5RZ 6SDFLQJ 1 H $ $ $ ( ( ' / F E E H% 0,1 ,1&+(6 120 %6& 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % (c) 2009 Microchip Technology Inc. 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DS39932C-page 507 PIC18F46J11 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 b N 123 NOTE 1 c NOTE 2 A L A1 L1 A2 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E 0,1 0,//,0(7(56 120 %6& 5() %6& %6& %6& %6& 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\ 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS39932C-page 508 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ (c) 2009 Microchip Technology Inc. DS39932C-page 509 PIC18F46J11 FAMILY NOTES: DS39932C-page 510 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (October 2008) Original data sheet for the PIC18F46J11 family of devices. DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1, Revision B (February 2009) Changes to the Electrical Characteristics and minor edits throughout text. Revision C (October 2009) Removed "Preliminary" marking. TABLE B-1: Features Program Memory Program Memory (Instructions) I/O Ports (Pins) 10-Bit ADC Module Packages DEVICE DIFFERENCES BETWEEN PIC18F46J11 FAMILY MEMBERS PIC18F24J11 16K 8,192 PIC18F25J11 32K 16,384 Ports A, B, C 10 Input Channels 28-Pin QFN, SOIC, SSOP and SPDIP (300 mil) PIC18F26J11 64K 32,768 PIC18F44J11 16K 8,192 PIC18F45J11 32K 16,384 Ports A, B, C, D, E 13 Input Channels 44-Pin QFN and TQFP PIC18F46J11 64K 32,768 (c) 2009 Microchip Technology Inc. DS39932C-page 511 PIC18F46J11 FAMILY NOTES: DS39932C-page 512 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY INDEX A A/D ................................................................................... 345 A/D Converter Interrupt, Configuring ....................... 349 Acquisition Requirements ........................................ 350 ADCAL Bit ................................................................ 353 ADRESH Register .................................................... 348 Analog Port Pins, Configuring .................................. 351 Associated Registers ............................................... 354 Automatic Acquisition Time ...................................... 351 Calibration ................................................................ 353 Configuring the Module ............................................ 349 Conversion Clock (TAD) ........................................... 351 Conversion Requirements ....................................... 498 Conversion Status (GO/DONE Bit) .......................... 348 Conversions ............................................................. 352 Converter Characteristics ........................................ 497 Operation in Power-Managed Modes ...................... 353 Special Event Trigger (ECCPx) ............................... 352 Use of the ECCP2 Trigger ....................................... 352 Absolute Maximum Ratings ............................................. 461 AC (Timing) Characteristics ............................................. 479 Load Conditions for Device Timing Specifications ... 480 Parameter Symbology ............................................. 479 Temperature and Voltage Specifications ................. 480 Timing Conditions .................................................... 480 ACKSTAT ........................................................................ 310 ACKSTAT Status Flag ..................................................... 310 ADCAL Bit ........................................................................ 353 ADCON0 Register GO/DONE Bit ........................................................... 348 ADDFSR .......................................................................... 450 ADDLW ............................................................................ 413 ADDULNK ........................................................................ 450 ADDWF ............................................................................ 413 ADDWFC ......................................................................... 414 ADRESL Register ............................................................ 348 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 414 ANDWF ............................................................................ 415 Assembler MPASM Assembler .................................................. 458 Auto-Wake-up on Sync Break Character ......................... 334 CTMU ...................................................................... 373 CTMU Current Source Calibration Circuit ............... 376 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ............................. 384 CTMU Typical Connections and Internal Configuration for Time Measurement .................................... 383 Demultiplexed Addressing Mode ............................. 180 Device Clock .............................................................. 32 EUSART Transmit ................................................... 331 EUSARTx Receive .................................................. 333 Fail-Safe Clock Monitor ........................................... 404 Fully Multiplexed Addressing Mode ......................... 180 Generic I/O Port Operation ...................................... 125 High/Low-Voltage Detect with External Input .......... 368 Interrupt Logic .......................................................... 110 LCD Control ............................................................. 188 Legacy Parallel Slave Port ...................................... 174 MSSPx (I2C Master Mode) ...................................... 305 MSSPx (I2C Mode) .................................................. 285 MSSPx (SPI Mode) ................................................. 266 Multiplexed Addressing Application ......................... 187 On-Chip Reset Circuit ................................................ 57 Parallel EEPROM (Up to 15-Bit Address, 16-Bit Data) . 188 Parallel EEPROM (Up to 15-Bit Address, 8-Bit Data) ... 188 Parallel Master/Slave Connection Addressed Buffer 177 Parallel Master/Slave Connection Buffered ............. 176 Partially Multiplexed Addressing Application ........... 187 Partially Multiplexed Addressing Mode .................... 180 PIC18F2XJ11 (28-Pin) .............................................. 14 PIC18F4XJ11 (44-Pin) .............................................. 15 PMP Module ............................................................ 165 PWM (Enhanced) .................................................... 249 PWM Operation (Simplified) .................................... 246 Reads From Flash Program Memory ...................... 101 RTCC ....................................................................... 221 Simplified Steering ................................................... 262 Single Comparator ................................................... 358 Table Read Operation ............................................... 97 Table Write Operation ............................................... 98 Table Writes to Flash Program Memory .................. 103 Timer0 in 16-Bit Mode ............................................. 192 Timer0 in 8-Bit Mode ............................................... 192 Timer1 ..................................................................... 199 Timer2 ..................................................................... 208 Timer3 ..................................................................... 212 Timer4 ..................................................................... 220 Using the Open-Drain Output .................................. 126 Watchdog Timer ...................................................... 399 BN .................................................................................... 416 BNC ................................................................................. 417 BNN ................................................................................. 417 BNOV .............................................................................. 418 BNZ ................................................................................. 418 BOR. See Brown-out Reset. BOV ................................................................................. 421 BRA ................................................................................. 419 Break Character (12-Bit) Transmit and Receive .............. 336 BRG. See Baud Rate Generator. Brown-out Reset (BOR) ..................................................... 59 and On-Chip Voltage Regulator .............................. 402 Detecting ................................................................... 59 B Bank Select Register ......................................................... 78 Baud Rate Generator ....................................................... 306 BC .................................................................................... 415 BCF .................................................................................. 416 BF .................................................................................... 310 BF Status Flag ................................................................. 310 Block Diagrams +5V System Hardware Interface .............................. 126 8-Bit Multiplexed Address and Data Application ...... 187 A/D ........................................................................... 348 Analog Input Model .................................................. 349 Baud Rate Generator ............................................... 307 Capture Mode Operation ......................................... 244 Comparator Analog Input Model .............................. 358 Comparator Configurations ...................................... 360 Comparator Output .................................................. 355 Comparator Voltage Reference ............................... 363 Comparator Voltage Reference Output Buffer Example 365 (c) 2009 Microchip Technology Inc. DS39932C-page 513 PIC18F46J11 FAMILY Disabling in Sleep Mode ............................................ 59 BSF .................................................................................. 419 BTFSC ............................................................................. 420 BTFSS .............................................................................. 420 BTG .................................................................................. 421 BZ ..................................................................................... 422 Effects of a Reset .................................................... 362 Enable and Input Selection ...................................... 359 Enable and Output Selection ................................... 359 Interrupts ................................................................. 361 Operation ................................................................. 358 Operation During Sleep ........................................... 362 Registers ................................................................. 355 Response Time ........................................................ 358 Comparator Specifications ............................................... 476 Comparator Voltage Reference ....................................... 363 Accuracy and Error .................................................. 365 Associated Registers ............................................... 365 Configuring .............................................................. 364 Connection Considerations ...................................... 365 Effects of a Reset .................................................... 365 Operation During Sleep ........................................... 365 Compare (ECCP Module) ................................................ 245 CCPRx Register ...................................................... 245 Pin Configuration ..................................................... 245 Software Interrupt .................................................... 245 Special Event Trigger ...................................... 217, 245 Timer1/Timer3 Mode Selection ................................ 245 Compare (ECCPx Module) Special Event Trigger .............................................. 352 Computed GOTO ............................................................... 75 Configuration Bits ............................................................ 389 Configuration Mismatch (CM) Reset .................................. 60 Configuration Register Protection .................................... 405 Configuration Registers Bits and Device IDs ................................................. 390 Mapping Flash Configuration Words ....................... 390 Core Features Easy Migration ........................................................... 12 Expanded Memory ..................................................... 11 Extended Instruction Set ........................................... 12 nanoWatt Technology ................................................ 11 Oscillator Options and Features ................................ 11 CPFSEQ .......................................................................... 424 CPFSGT .......................................................................... 425 CPFSLT ........................................................................... 425 Crystal Oscillator/Ceramic Resonators .............................. 33 CTMU Associated Registers ............................................... 387 Calibrating ............................................................... 375 Creating a Delay with ............................................... 384 Effects of a Reset .................................................... 384 Initialization .............................................................. 375 Measuring Capacitance with .................................... 381 Measuring Time with ................................................ 383 Operation ................................................................. 374 Operation During Idle Mode ..................................... 384 Operation During Sleep Mode ................................. 384 CTMU Current Source Specifications .............................. 476 Customer Change Notification Service ............................ 525 Customer Notification Service ......................................... 525 Customer Support ............................................................ 525 C C Compilers MPLAB C18 ............................................................. 458 MPLAB C30 ............................................................. 458 Calibration (A/D Converter) .............................................. 353 CALL ................................................................................ 422 CALLW ............................................................................. 451 Capture (ECCP Module) .................................................. 243 CCPRxH:CCPRxL Registers ................................... 243 ECCP Pin Configuration .......................................... 243 Prescaler .................................................................. 244 Software Interrupt .................................................... 243 Timer1/Timer3 Mode Selection ................................ 243 Clock Sources .................................................................... 36 Effects of Power-Managed Modes ............................. 40 Selecting the 31 kHz Source ...................................... 37 Selection Using OSCCON Register ........................... 37 CLRF ................................................................................ 423 CLRWDT .......................................................................... 423 Code Examples 16 x 16 Signed Multiply Routine .............................. 108 16 x 16 Unsigned Multiply Routine .......................... 108 512-Byte SPI Master Mode Init and Transfer ........... 283 8 x 8 Signed Multiply Routine .................................. 107 8 x 8 Unsigned Multiply Routine .............................. 107 A/D Calibration Routine ........................................... 353 Calculating Baud Rate Error .................................... 326 Capacitance Calibration Routine ............................. 380 Capacitive Touch Switch Routine ............................ 382 Changing Between Capture Prescalers ................... 244 Communicating with the +5V System ...................... 126 Computed GOTO Using an Offset Value ................... 75 Configuring EUSART2 Input and Output Functions . 148 Current Calibration Routine ..................................... 378 Erasing Flash Program Memory .............................. 102 Fast Register Stack .................................................... 75 How to Clear RAM (Bank 1) Using Indirect Addressing . 90 Initializing PORTA .................................................... 129 Initializing PORTB .................................................... 132 Initializing PORTC .................................................... 136 Initializing PORTD .................................................... 139 Initializing PORTE .................................................... 142 Loading the SSP1BUF (SSP1SR) Register ............. 269 Reading a Flash Program Memory Word ................ 101 Saving STATUS, WREG and BSR Registers in RAM ... 124 Setup for CTMU Calibration Routines ...................... 377 Single-Word Write to Flash Program Memory ......... 105 Two-Word Instructions ............................................... 77 Ultra Low-Power Wake-up Initialization ..................... 56 Writing to Flash Program Memory ........................... 104 Code Protection ............................................................... 389 COMF ............................................................................... 424 Comparator ...................................................................... 355 Analog Input Connection Considerations ................. 358 Associated Registers ............................................... 362 Configuration ............................................................ 359 Control ..................................................................... 359 D Data Addressing Modes .................................................... 90 Comparing Addressing Modes with the Extended Instruction Set Enabled ........................................ 94 Direct ......................................................................... 90 Indexed Literal Offset ................................................ 93 BSR ................................................................... 95 Instructions Affected .......................................... 93 Mapping Access Bank ....................................... 95 DS39932C-page 514 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Indirect ....................................................................... 90 Inherent and Literal .................................................... 90 Data Memory ..................................................................... 78 Access Bank .............................................................. 80 Extended Instruction Set ............................................ 92 General Purpose Registers ........................................ 80 Memory Maps Access Bank Special Function Registers .......... 81 Non-Access Bank Special Function Registers .. 82 PIC18F46J11 Family Devices ........................... 79 Special Function Registers ........................................ 81 Context Defined SFRs ....................................... 83 DAW ................................................................................. 426 DC Characteristics ........................................................... 474 Power-Down and Supply Current ............................ 464 Supply Voltage ......................................................... 463 DCFSNZ .......................................................................... 427 DECF ............................................................................... 426 DECFSZ ........................................................................... 427 Development Support ...................................................... 457 Device Differences ........................................................... 511 Device Overview ................................................................ 11 Details on Individual Family Members ....................... 12 Features (28-Pin Devices) ......................................... 13 Features (44-Pin Devices) ......................................... 13 Other Special Features .............................................. 12 Direct Addressing ............................................................... 91 Auto-Wake-up on Sync Break ......................... 334 Receiver .......................................................... 333 Setting Up 9-Bit Mode with Address Detect .... 333 Transmitter ...................................................... 331 Baud Rate Generator Operation in Power-Managed Mode ................ 325 Baud Rate Generator (BRG) ................................... 325 Associated Registers ....................................... 326 Auto-Baud Rate Detect .................................... 329 Baud Rates, Asynchronous Modes ................. 327 Formulas .......................................................... 325 High Baud Rate Select (BRGH Bit) ................. 325 Sampling ......................................................... 325 Synchronous Master Mode ...................................... 337 Associated Registers, Reception ..................... 340 Associated Registers, Transmission ............... 338 Reception ........................................................ 339 Transmission ................................................... 337 Synchronous Slave Mode ........................................ 341 Associated Registers, Reception ..................... 343 Associated Registers, Transmission ............... 342 Reception ........................................................ 343 Transmission ................................................... 341 Extended Instruction Set ADDFSR .................................................................. 450 ADDULNK ............................................................... 450 CALLW .................................................................... 451 MOVSF .................................................................... 451 MOVSS .................................................................... 452 PUSHL ..................................................................... 452 SUBFSR .................................................................. 453 SUBULNK ................................................................ 453 Extended Instructions Considerations when Enabling ................................ 454 External Clock Input ........................................................... 34 E Effect on Standard PIC MCU Instructions ........................ 454 Electrical Characteristics .................................................. 461 Absolute Maximum Ratings ..................................... 461 Enhanced Capture/Compare/PWM (ECCP) .................... 241 Associated Registers ............................................... 263 Capture Mode. See Capture. Compare Mode. See Compare. ECCP Mode and Timer Resources .......................... 243 Enhanced PWM Mode ............................................. 249 Auto-Restart ..................................................... 258 Auto-Shutdown ................................................ 257 Direction Change in Full-Bridge Output Mode . 255 Full-Bridge Application ..................................... 253 Full-Bridge Mode ............................................. 253 Half-Bridge Application .................................... 252 Half-Bridge Application Examples ................... 259 Half-Bridge Mode ............................................. 252 Output Relationships (Active-High) .................. 250 Output Relationships Diagram (Active-Low) .... 251 Programmable Dead-Band Delay .................... 259 Shoot-Through Current .................................... 259 Start-up Considerations ................................... 256 Outputs and Configuration ....................................... 243 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). See EUSART. Equations A/D Acquisition Time ................................................ 350 A/D Minimum Charging Time ................................... 350 Bytes Transmitted for a Given DMABC ................... 281 Calculating the Minimum Required Acquisition Time ..... 350 Errata ................................................................................... 9 EUSART .......................................................................... 321 Asynchronous Mode ................................................ 331 12-Bit Break Transmit and Receive ................. 336 Associated Registers, Reception ..................... 334 Associated Registers, Transmission ................ 332 F Fail-Safe Clock Monitor ........................................... 389, 403 Interrupts in Power-Managed Modes ...................... 405 POR or Wake-up From Sleep .................................. 405 WDT During Oscillator Failure ................................. 404 Fast Register Stack ........................................................... 75 Features Overview ............................................................... 3 Comparative Table ...................................................... 4 Firmware Instructions ...................................................... 407 Flash Program Memory ..................................................... 97 Associated Registers ............................................... 106 Control Registers ....................................................... 98 EECON1 and EECON2 ..................................... 98 TABLAT (Table Latch) ..................................... 100 TBLPTR (Table Pointer) Register .................... 100 Erase Sequence ...................................................... 102 Erasing .................................................................... 102 Operation During Code-Protect ............................... 106 Reading ................................................................... 101 Table Pointer Boundaries Based on Operation ..................... 100 Table Pointer Boundaries ........................................ 100 Table Reads and Table Writes .................................. 97 Write Sequence ....................................................... 103 Write Sequence (Word Programming) .................... 105 Writing ..................................................................... 103 Unexpected Termination ................................. 106 Write Verify ...................................................... 106 FSCM. See Fail-Safe Clock Monitor. (c) 2009 Microchip Technology Inc. DS39932C-page 515 PIC18F46J11 FAMILY G GOTO ............................................................................... 428 H Hardware Multiplier .......................................................... 107 8 x 8 Multiplication Algorithms ................................. 107 Operation ................................................................. 107 Performance Comparison (table) ............................. 107 High/Low-Voltage Detect ................................................. 367 Applications .............................................................. 371 Associated Registers ............................................... 372 Characteristics ......................................................... 478 Current Consumption ............................................... 369 Effects of a Reset ..................................................... 372 Operation ................................................................. 368 During Sleep .................................................... 372 Setup ........................................................................ 369 Start-up Time ........................................................... 369 Typical Application ................................................... 371 I I/O Ports ........................................................................... 125 Open-Drain Outputs ................................................. 126 Pin Capabilities ........................................................ 125 TTL Input Buffer Option ........................................... 126 I2C Mode .......................................................................... 285 I2C Mode (MSSP) Acknowledge Sequence Timing ............................... 313 Associated Registers ............................................... 319 Baud Rate Generator ............................................... 306 Bus Collision During a Repeated Start Condition .................. 317 During a Stop Condition ................................... 318 Clock Arbitration ....................................................... 308 Clock Stretching ....................................................... 300 10-Bit Slave Receive Mode (SEN = 1) ............. 300 10-Bit Slave Transmit Mode ............................. 300 7-Bit Slave Receive Mode (SEN = 1) ............... 300 7-Bit Slave Transmit Mode ............................... 300 Clock Synchronization and CKP bit ......................... 301 Effects of a Reset ..................................................... 314 General Call Address Support ................................. 304 I2C Clock Rate w/BRG ............................................. 307 Master Mode ............................................................ 304 Operation ......................................................... 305 Reception ......................................................... 310 Repeated Start Condition Timing ..................... 309 Start Condition Timing ..................................... 308 Transmission .................................................... 310 Multi-Master Communication, Bus Collision and Arbitration ................................................................... 314 Multi-Master Mode ................................................... 314 Operation ................................................................. 290 Read/Write Bit Information (R/W Bit) ............... 290, 293 Registers .................................................................. 285 Serial Clock (SCLx Pin) ........................................... 293 Slave Mode .............................................................. 290 Addressing ....................................................... 290 Addressing Masking Modes 5-Bit ......................................................... 291 7-Bit ......................................................... 292 Reception ......................................................... 293 Transmission .................................................... 293 Sleep Operation ....................................................... 314 Stop Condition Timing .............................................. 313 INCF ................................................................................ 428 INCFSZ ............................................................................ 429 In-Circuit Debugger .......................................................... 406 In-Circuit Serial Programming (ICSP) ...................... 389, 406 Indexed Literal Offset Addressing and Standard PIC18 Instructions ............................. 454 Indexed Literal Offset Mode ............................................. 454 Indirect Addressing ............................................................ 91 INFSNZ ............................................................................ 429 Initialization Conditions ................................................ 63-69 Instruction Cycle ................................................................ 76 Clocking Scheme ....................................................... 76 Flow/Pipelining ........................................................... 76 Instruction Set .................................................................. 407 ADDLW .................................................................... 413 ADDWF .................................................................... 413 ADDWF (Indexed Literal Offset Mode) .................... 455 ADDWFC ................................................................. 414 ANDLW .................................................................... 414 ANDWF .................................................................... 415 BC ............................................................................ 415 BCF ......................................................................... 416 BN ............................................................................ 416 BNC ......................................................................... 417 BNN ......................................................................... 417 BNOV ...................................................................... 418 BNZ ......................................................................... 418 BOV ......................................................................... 421 BRA ......................................................................... 419 BSF .......................................................................... 419 BSF (Indexed Literal Offset Mode) .......................... 455 BTFSC ..................................................................... 420 BTFSS ..................................................................... 420 BTG ......................................................................... 421 BZ ............................................................................ 422 CALL ........................................................................ 422 CLRF ....................................................................... 423 CLRWDT ................................................................. 423 COMF ...................................................................... 424 CPFSEQ .................................................................. 424 CPFSGT .................................................................. 425 CPFSLT ................................................................... 425 DAW ........................................................................ 426 DCFSNZ .................................................................. 427 DECF ....................................................................... 426 DECFSZ .................................................................. 427 Extended Instructions .............................................. 449 Considerations when Enabling ........................ 454 Syntax .............................................................. 449 Use with MPLAB IDE Tools ............................. 456 General Format ........................................................ 409 GOTO ...................................................................... 428 INCF ........................................................................ 428 INCFSZ .................................................................... 429 INFSNZ .................................................................... 429 IORLW ..................................................................... 430 IORWF ..................................................................... 430 LFSR ....................................................................... 431 MOVF ...................................................................... 431 MOVFF .................................................................... 432 MOVLB .................................................................... 432 MOVLW ................................................................... 433 MOVWF ................................................................... 433 MULLW .................................................................... 434 MULWF .................................................................... 434 DS39932C-page 516 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY NEGF ....................................................................... 435 NOP ......................................................................... 435 Opcode Field Descriptions ....................................... 408 POP ......................................................................... 436 PUSH ....................................................................... 436 RCALL ..................................................................... 437 RESET ..................................................................... 437 RETFIE .................................................................... 438 RETLW .................................................................... 438 RETURN .................................................................. 439 RLCF ........................................................................ 439 RLNCF ..................................................................... 440 RRCF ....................................................................... 440 RRNCF .................................................................... 441 SETF ........................................................................ 441 SETF (Indexed Literal Offset Mode) ........................ 455 SLEEP ..................................................................... 442 Standard Instructions ............................................... 407 SUBFWB .................................................................. 442 SUBLW .................................................................... 443 SUBWF .................................................................... 443 SUBWFB .................................................................. 444 SWAPF .................................................................... 444 TBLRD ..................................................................... 445 TBLWT ..................................................................... 446 TSTFSZ ................................................................... 447 XORLW .................................................................... 447 XORWF .................................................................... 448 INTCON ........................................................................... 111 INTCON Registers ........................................................... 111 Inter-Integrated Circuit. See I2C. Internal Oscillator Frequency Drift. See INTOSC Frequency Drift. Internal Oscillator Block ..................................................... 34 Adjustment ................................................................. 35 OSCTUNE Register ................................................... 35 Internal RC Oscillator Use with WDT .......................................................... 399 Internal Voltage Reference Specifications ....................... 477 Internet Address ............................................................... 525 Interrupt Sources ............................................................. 389 A/D Conversion Complete ....................................... 349 Capture Complete (ECCP) ...................................... 243 Compare Complete (ECCP) .................................... 245 Interrupt-on-Change (RB7:RB4) .............................. 132 TMR0 Overflow ........................................................ 193 TMR1 Overflow ........................................................ 201 TMR3 Overflow ................................................ 209, 217 TMR4 to PR4 Match ................................................ 220 TMR4 to PR4 Match (PWM) .................................... 219 Interrupts .......................................................................... 109 Control Bits .............................................................. 109 Control Registers. See INTCON Registers. During, Context Saving ............................................ 124 INTx Pin ................................................................... 124 PORTB, Interrupt-on-Change .................................. 124 RCON Register ........................................................ 123 TMR0 ....................................................................... 124 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ..... 132 INTOSC Frequency Drift .................................................... 35 INTOSC, INTRC. See Internal Oscillator Block. IORLW ............................................................................. 430 IORWF ............................................................................. 430 L LFSR ............................................................................... 431 Low-Power Modes ............................................................. 41 Clock Transitions and Status Indicators .................... 42 Deep Sleep Mode ...................................................... 48 and RTCC Peripheral ........................................ 50 Brown-out Reset (DSBOR) ................................ 50 Preparing for ...................................................... 49 Registers ........................................................... 52 Typical Sequence .............................................. 51 Wake-up Sources .............................................. 50 Watchdog Timer (DSWDT) ................................ 50 Exiting Idle and Sleep Modes .................................... 48 By Interrupt ........................................................ 48 By Reset ............................................................ 48 By WDT Time-out .............................................. 48 Without an Oscillator Start-up Delay ................. 48 Idle Modes ................................................................. 46 PRI_IDLE .......................................................... 46 RC_IDLE ........................................................... 48 SEC_IDLE ......................................................... 46 Multiple Sleep Commands ......................................... 42 Run Modes ................................................................ 42 PRI_RUN ........................................................... 42 RC_RUN ............................................................ 44 SEC_RUN ......................................................... 42 Sleep Mode ............................................................... 45 Summary (table) ........................................................ 42 Ultra Low-Power Wake-up ......................................... 55 M Master Clear (MCLR) ......................................................... 59 Master Synchronous Serial Port (MSSP). See MSSP. Memory Organization ........................................................ 71 Data Memory ............................................................. 78 Program Memory ....................................................... 71 Return Address Stack ................................................ 73 Memory Programming Requirements .............................. 476 Microchip Internet Web Site ............................................. 525 MOVF .............................................................................. 431 MOVFF ............................................................................ 432 MOVLB ............................................................................ 432 MOVLW ........................................................................... 433 MOVSF ............................................................................ 451 MOVSS ............................................................................ 452 MOVWF ........................................................................... 433 MPLAB ASM30 Assembler, Linker, Librarian .................. 458 MPLAB ICD 2 In-Circuit Debugger .................................. 459 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ........................................................................ 459 MPLAB Integrated Development Environment Software . 457 MPLAB PM3 Device Programmer ................................... 459 MPLAB REAL ICE In-Circuit Emulator System ............... 459 MPLINK Object Linker/MPLIB Object Librarian ............... 458 MSSP ACK Pulse ....................................................... 290, 293 I2C Mode. See I2C Mode. Module Overview ..................................................... 265 SPI Master/Slave Connection .................................. 270 TMR4 Output for Clock Shift .................................... 220 MULLW ............................................................................ 434 MULWF ............................................................................ 434 N NEGF ............................................................................... 435 (c) 2009 Microchip Technology Inc. DS39932C-page 517 PIC18F46J11 FAMILY NOP ................................................................................. 435 O Oscillator Configuration Internal Oscillator Block ............................................. 34 Oscillator Control ....................................................... 31 Oscillator Modes ........................................................ 32 Oscillator Types ......................................................... 31 Oscillator Configurations .................................................... 31 Oscillator Selection .......................................................... 389 Oscillator Start-up Timer (OST) ......................................... 40 Oscillator Switching ............................................................ 36 Oscillator Transitions .......................................................... 37 Oscillator, Timer1 ............................................. 195, 200, 213 Oscillator, Timer3 ............................................................. 209 P P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/PWM (ECCP). .................................................................... 249 Packaging Details ...................................................................... 501 Marking .................................................................... 499 Parallel Master Port (PMP) .............................................. 165 Application Examples ............................................... 187 Associated Registers ............................................... 189 Data Registers ......................................................... 172 Master Port Modes ................................................... 179 Module Registers ..................................................... 166 Slave Port Modes ..................................................... 174 Peripheral Pin Select (PPS) ............................................. 144 PICSTART Plus Development Programmer .................... 460 Pin Diagrams .................................................................... 5-7 Pin Functions AVDD1 ........................................................................ 29 AVDD2 ........................................................................ 29 AVSS1 ........................................................................ 29 MCLR ................................................................... 16, 22 OSC1/CLKI/RA7 .................................................. 16, 22 OSC2/CLKO/RA6 ................................................ 16, 22 RA0/AN0/C1INA/ULPWU/PMA6/RP0 ........................ 23 RA0/AN0/C1INA/ULPWU/RP0 .................................. 17 RA1/AN1/C2INA/PMA7/RP1 ...................................... 23 RA1/AN1/C2INA/RP1 ................................................ 17 RA2/AN2/VREF-/CVREF/C2INB ............................ 17, 23 RA3/AN3/VREF+/C1INB ....................................... 17, 23 RA5/AN4/SS1/HLVDIN/RP2 ................................ 17, 23 RA6 ...................................................................... 17, 23 RA7 ...................................................................... 17, 23 RB0/AN12/INT0/RP3 ........................................... 18, 24 RB1/AN10/PMBE/RTCC/RP4 .................................... 24 RB1/AN10/RTCC/RP4 ............................................... 18 RB2/AN8/CTEDG1/PMA3/REFO/RP5 ....................... 24 RB2/AN8/CTEDG1/REFO/RP5 ................................. 18 RB3/AN9/CTEDG2/PMA2/RP6 .................................. 24 RB3/AN9/CTEDG2/RP6 ............................................ 18 RB4/KBI0/RP7 ........................................................... 18 RB4/PMA1/KBI0/RP7 ................................................ 25 RB5/KBI1/RP8 ........................................................... 18 RB5/PMA0/KBI1/RP8 ................................................ 25 RB6/KBI2/PGC/RP9 ............................................ 19, 25 RB7/KBI3/PGD/RP10 .......................................... 19, 25 RC0/T1OSO/T1CKI/RP11 ................................... 20, 26 RC1/T1OSI/RP12 ................................................ 20, 26 RC2/AN11/CTPLS/RP13 ..................................... 20, 26 RC3/SCK1/SCL1/RP14 ....................................... 20, 26 RC4/SDI1/SDA1/RP15 ........................................ 20, 26 RC5/SDO1/RP16 ................................................. 20, 26 RC6/PMA5/TX1/CK1/RP17 ....................................... 27 RC6/TX1/CK1/RP17 .................................................. 20 RC7/PMA4/RX1/DT1/RP18 ....................................... 27 RC7/RX1/DT1/RP18 .................................................. 20 RD0/PMD0/SCL2 ....................................................... 28 RD1/PMD1/SDA2 ...................................................... 28 RD2/PMD2/RP19 ....................................................... 28 RD3/PMD3/RP20 ....................................................... 28 RD4/PMD4/RP21 ....................................................... 28 RD5/PMD5/RP22 ....................................................... 28 RD6/PMD6/RP23 ....................................................... 28 RD7/PMD7/RP24 ....................................................... 28 RE0/AN5/PMRD ........................................................ 29 RE1/AN6/PMWR ....................................................... 29 RE2/AN7/PMCS ........................................................ 29 VDD ............................................................................ 21 VDD1 .......................................................................... 29 VDD2 .......................................................................... 29 VDDCORE/VCAP .................................................... 21, 29 VSS1 .................................................................... 21, 29 VSS2 .................................................................... 21, 29 Pinout I/O Descriptions PIC18F2XJ11 (28-Pin) ............................................... 16 PIC18F4XJ11 (44-Pin) ............................................... 22 PLL Frequency Multiplier ................................................... 34 POP ................................................................................. 436 POR. See Power-on Reset. PORTA Additional Pin Functions Ultra Low-Power Wake-up ................................. 55 Associated Registers ............................................... 131 LATA Register ......................................................... 129 PORTA Register ...................................................... 129 TRISA Register ........................................................ 129 PORTB Associated Registers ............................................... 135 LATB Register ......................................................... 132 PORTB Register ...................................................... 132 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 132 TRISB Register ........................................................ 132 PORTC Associated Registers ............................................... 138 LATC Register ......................................................... 136 PORTC Register ...................................................... 136 TRISC Register ........................................................ 136 PORTD Associated Registers ............................................... 141 LATD Register ......................................................... 139 PORTD Register ...................................................... 139 TRISD Register ........................................................ 139 PORTE Associated Registers ............................................... 143 LATE Register ......................................................... 142 PORTE Register ...................................................... 142 TRISE Register ........................................................ 142 Power-Managed Modes and EUSART Operation .......................................... 325 and PWM Operation ................................................ 263 and SPI Operation ................................................... 274 Clock Sources ............................................................ 41 Entering ..................................................................... 41 Selecting .................................................................... 41 Power-on Reset (POR) ...................................................... 59 Power-up Delays ............................................................... 40 DS39932C-page 518 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Power-up Timer (PWRT) ............................................. 40, 60 Time-out Sequence .................................................... 60 Prescaler, Timer0 ............................................................. 193 Prescaler, Timer2 (Timer4) .............................................. 247 PRI_IDLE Mode ................................................................. 46 PRI_RUN Mode ................................................................. 42 Product Identification System .......................................... 527 Program Counter ............................................................... 73 PCL, PCH and PCU Registers ................................... 73 PCLATH and PCLATU Registers .............................. 73 Program Memory ALU Status ................................................................. 89 Extended Instruction Set ............................................ 92 Flash Configuration Words ........................................ 72 Hard Memory Vectors ................................................ 72 Instructions ................................................................. 77 Two-Word .......................................................... 77 Interrupt Vector .......................................................... 72 Look-up Tables .......................................................... 75 Memory Maps ............................................................ 71 Hard Vectors and Configuration Words ............. 72 Reset Vector .............................................................. 72 Program Verification and Code Protection ....................... 405 Programming, Device Instructions ................................... 407 Pulse Steering .................................................................. 260 PUSH ............................................................................... 436 PUSH and POP Instructions .............................................. 74 PUSHL ............................................................................. 452 PWM (CCP Module) Associated Registers ............................................... 248 Duty Cycle ................................................................ 246 Example Frequencies/Resolutions .......................... 247 Operation Setup ....................................................... 247 Period ....................................................................... 246 PR2/PR4 Registers .................................................. 246 TMR2 (TMR4) to PR2 (PR4) Match ......................... 246 PWM (ECCP Module) Effects of a Reset ..................................................... 263 Operation in Power-Managed Modes ...................... 263 Operation with Fail-Safe Clock Monitor ................... 263 Pulse Steering .......................................................... 260 Steering Synchronization ......................................... 262 TMR4 to PR4 Match ................................................ 219 PWM Mode. See Enhanced Capture/Compare/PWM ..... 249 ALRMCFG (Alarm Configuration) ............................ 225 ALRMDAY (Alarm Day Value) ................................. 230 ALRMHR (Alarm Hours Value) ................................ 231 ALRMMIN (Alarm Minutes Value) ........................... 232 ALRMMNTH (Alarm Month Value) .......................... 230 ALRMRPT (Alarm Calibration) ................................ 226 ALRMSEC (Alarm Seconds Value) ......................... 232 ALRMWD (Alarm Weekday Value) .......................... 231 ANCON0 (A/D Port Configuration 2) ....................... 347 ANCON1 (A/D Port Configuration 1) ....................... 347 Associated with Comparator .................................... 355 Associated with Watchdog Timer ............................ 400 BAUDCONx (Baud Rate Control) ............................ 324 CCPxCON (Enhanced Capture/Compare/PWM x Control) .................................................................. 242 CMSTAT (Comparator Status) ................................ 357 CMxCON (Comparator Control x) ........................... 356 CONFIG1H (Configuration 1 High) .......................... 392 CONFIG1L (Configuration 1 Low) ........................... 391 CONFIG2H (Configuration 2 High) .......................... 394 CONFIG2L (Configuration 2 Low) ........................... 393 CONFIG3H (Configuration 3 High) .......................... 396 CONFIG3L (Configuration 3 Low) ........................... 395 CONFIG4H (Configuration 4 High) .......................... 397 CONFIG4L (Configuration 4 Low) ........................... 396 CTMUCONH (CTMU Control High) ......................... 385 CTMUCONL (CTMU Control Low) .......................... 386 CTMUICON (CTMU Current Control) ...................... 387 CVRCON (Comparator Voltage Reference Control) 364 DAY (Day Value) ..................................................... 228 DEVID1 (Device ID 1) .............................................. 397 DEVID2 (Device ID 2) .............................................. 398 DMACON1 (DMA Control 1) .................................... 278 DMACON2 (DMA Control 2) .................................... 279 DSCONH (Deep Sleep Control High Byte) ................ 52 DSCONL (Deep Sleep Control Low Byte) ................. 52 DSGPR0 (Deep Sleep Persistent General Purpose 0) . 53 DSGPR1 (Deep Sleep Persistent General Purpose 1) . 53 DSWAKEH (Deep Sleep Wake High Byte) ............... 54 DSWAKEL (Deep Sleep Wake Low Byte) ................. 54 ECCPxAS (ECCPx Auto-Shutdown Control) ........... 257 ECCPxDEL (Enhanced PWM Control) .................... 260 EECON1 (EEPROM Control 1) ................................. 99 File Summary ............................................................ 83 HLVDCON (High/Low-Voltage Detect Control) ....... 367 HOURS (Hours Value) ............................................ 229 I2C Mode (MSSP) .................................................... 285 INTCON (Interrupt Control) ..................................... 111 INTCON2 (Interrupt Control 2) ................................ 112 INTCON3 (Interrupt Control 3) ................................ 113 IPR1 (Peripheral Interrupt Priority 1) ....................... 120 IPR2 (Peripheral Interrupt Priority 2) ....................... 121 IPR3 (Peripheral Interrupt Priority 3) ....................... 122 MINUTES (Minutes Value) ...................................... 229 MONTH (Month Value) ............................................ 227 ODCON1 (Peripheral Open-Drain Control 1) .......... 127 ODCON2 (Peripheral Open-Drain Control 2) .......... 127 ODCON3 (Peripheral Open-Drain Control 3) .......... 128 OSCCON (Oscillator Control) .................................... 38 OSCTUNE (Oscillator Tuning) ................................... 36 PADCFG1 (Pad Configuration Control 1) ................ 128 PADCFG1 (Pad Configuration) ............................... 224 Parallel Master Port ................................................. 166 Q Q Clock ............................................................................ 247 R RAM. See Data Memory. RBIF Bit ............................................................................ 132 RC_IDLE Mode .................................................................. 48 RC_RUN Mode .................................................................. 44 RCALL ............................................................................. 437 RCON Register Bit Status During Initialization .................................... 62 Reader Response ............................................................ 526 Real-Time Clock and Calendar (RTCC) ........................... 221 Operation ................................................................. 233 Registers .................................................................. 222 Reference Clock Output ..................................................... 39 Register File ....................................................................... 80 Register File Summary ................................................ 83-88 Registers ADCON0 (A/D Control 0) ......................................... 345 ADCON1 (A/D Control 1) ......................................... 346 (c) 2009 Microchip Technology Inc. DS39932C-page 519 PIC18F46J11 FAMILY PIE1 (Peripheral Interrupt Enable 1) ........................ 117 PIE2 (Peripheral Interrupt Enable 2) ........................ 118 PIE3 (Peripheral Interrupt Enable 3) ........................ 119 PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 114 PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 115 PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 116 PMADDRH (Parallel Port Address High Byte) ......... 173 PMADDRL (Parallel Port Address Low Byte) .......... 173 PMCONH (Parallel Port Control High Byte) ............. 166 PMCONL (Parallel Port Control Low Byte) .............. 167 PMEH (Parallel Port Enable High Byte) ................... 170 PMEL (Parallel Port Enable Low Byte) .................... 170 PMMODEH (Parallel Port Mode High Byte) ............. 168 PMMODEL (Parallel Port Mode Low Byte) .............. 169 PMSTATH (Parallel Port Status High Byte) ............. 171 PMSTATL (Parallel Port Status Low Byte) .............. 171 PPSCON (Peripheral Pin Select Input 0) ................. 149 PSTRxCON (Pulse Steering Control) ...................... 261 RCON (Reset Control) ....................................... 58, 123 RCSTAx (Receive Status and Control) .................... 323 REF0CON (Reference Oscillator Control) ................. 39 Reserved .................................................................. 227 RPINR1 (Peripheral Pin Select Input 1) ................... 150 RPINR12 (Peripheral Pin Select Input 12) ............... 152 RPINR13 (Peripheral Pin Select Input 13) ............... 152 RPINR16 (Peripheral Pin Select Input 16) ............... 153 RPINR17 (Peripheral Pin Select Input 17) ............... 153 RPINR2 (Peripheral Pin Select Input 2) ................... 150 RPINR21 (Peripheral Pin Select Input 21) ............... 153 RPINR22 (Peripheral Pin Select Input 22) ............... 154 RPINR23 (Peripheral Pin Select Input 23) ............... 154 RPINR24 (Peripheral Pin Select Input 24) ............... 154 RPINR3 (Peripheral Pin Select Input 3) ................... 150 RPINR4 (Peripheral Pin Select Input 4) ................... 151 RPINR6 (Peripheral Pin Select Input 6) ................... 151 RPINR7 (Peripheral Pin Select Input 7) ................... 151 RPINR8 (Peripheral Pin Select Input 8) ................... 152 RPOR0 (Peripheral Pin Select Output 0) ................. 155 RPOR1 (Peripheral Pin Select Output 1) ................. 155 RPOR10 (Peripheral Pin Select Output 10) ............. 158 RPOR11 (Peripheral Pin Select Output 11) ............. 158 RPOR12 (Peripheral Pin Select Output 12) ............. 159 RPOR13 (Peripheral Pin Select Output 13) ............. 159 RPOR14 (Peripheral Pin Select Output 14) ............. 159 RPOR15 (Peripheral Pin Select Output 15) ............. 160 RPOR16 (Peripheral Pin Select Output 16) ............. 160 RPOR17 (Peripheral Pin Select Output 17) ............. 160 RPOR18 (Peripheral Pin Select Output 18) ............. 161 RPOR19 (Peripheral Pin Select Output 19) ............. 161 RPOR2 (Peripheral Pin Select Output 2) ................. 155 RPOR20 (Peripheral Pin Select Output 20) ............. 161 RPOR21 (Peripheral Pin Select Output 21) ............. 162 RPOR22 (Peripheral Pin Select Output 22) ............. 162 RPOR23 (Peripheral Pin Select Output 23) ............. 162 RPOR24 (Peripheral Pin Select Output 24) ............. 163 RPOR3 (Peripheral Pin Select Output 3) ................. 156 RPOR4 (Peripheral Pin Select Output 4) ................. 156 RPOR5 (Peripheral Pin Select Output 5) ................. 156 RPOR6 (Peripheral Pin Select Output 6) ................. 157 RPOR7 (Peripheral Pin Select Output 7) ................. 157 RPOR8 (Peripheral Pin Select Output 8) ................. 157 RPOR9 (Peripheral Pin Select Output 9) ................. 158 RTCCAL (RTCC Calibration) ................................... 224 RTCCFG (RTCC Configuration) .............................. 223 SECONDS (Seconds Value) .................................... 229 SPI Mode (MSSP) ................................................... 267 SSPxCON1 (MSSPx Control 1, I2C Mode) .............. 287 SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 268 SSPxCON2 (MSSPx Control 2, I2C Master Mode) .. 288 SSPxCON2 (MSSPx Control 2, I2C Slave Mode) .... 289 SSPxMSK (I2C Slave Address Mask) ...................... 289 SSPxSTAT (MSSPx Status, I2C Mode) ................... 286 SSPxSTAT (MSSPx Status, SPI Mode) .................. 267 STATUS .................................................................... 89 STKPTR (Stack Pointer) ............................................ 74 T0CON (Timer0 Control) ......................................... 191 T1CON (Timer1 Control) ......................................... 195 T1GCON (Timer1 Gate Control) .............................. 196 T2CON (Timer2 Control) ......................................... 207 T3CON (Timer3 Control) ......................................... 209 T3GCON (Timer3 Gate Control) .............................. 210 T4CON (Timer4 Control) ......................................... 219 TCLKCON (Timer Clock Control) .................... 197, 211 TXSTAx (Transmit Status and Control) ................... 322 WDTCON (Watchdog Timer Control) ...................... 400 WKDY (Weekday Value) ......................................... 228 YEAR (Year Value) .................................................. 227 RESET ............................................................................. 437 Reset ................................................................................. 57 Brown-out Reset ........................................................ 59 Brown-out Reset (BOR) ............................................. 57 Configuration Mismatch (CM) .................................... 57 Configuration Mismatch Reset ................................... 60 Deep Sleep ................................................................ 57 Fast Register Stack ................................................... 75 MCLR ........................................................................ 59 MCLR Reset, During Power-Managed Modes .......... 57 MCLR Reset, Normal Operation ................................ 57 Power-on Reset ......................................................... 59 Power-on Reset (POR) .............................................. 57 Power-up Timer ......................................................... 60 RESET Instruction ..................................................... 57 Stack Full ................................................................... 57 Stack Underflow ......................................................... 57 State of Registers ...................................................... 62 Watchdog Timer (WDT) Reset .................................. 57 Resets .............................................................................. 389 Brown-out Reset (BOR) ........................................... 389 Oscillator Start-up Timer (OST) ............................... 389 Power-on Reset (POR) ............................................ 389 Power-up Timer (PWRT) ......................................... 389 RETFIE ............................................................................ 438 RETLW ............................................................................ 438 RETURN .......................................................................... 439 Return Address Stack ........................................................ 73 Associated Registers ................................................. 73 Revision History ............................................................... 511 RLCF ............................................................................... 439 RLNCF ............................................................................. 440 RRCF ............................................................................... 440 RRNCF ............................................................................ 441 RTCC Alarm ....................................................................... 237 Configuring ...................................................... 237 Interrupt ........................................................... 238 Mask Settings .................................................. 237 Alarm Value Registers (ALRMVAL) ......................... 230 Control Registers ..................................................... 223 Low-Power Modes ................................................... 238 Operation DS39932C-page 520 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY ALRMVAL Register Mapping ........................... 236 Calibration ........................................................ 236 Clock Source ................................................... 234 Digit Carry Rules .............................................. 234 General Functionality ....................................... 235 Leap Year ........................................................ 235 Register Mapping ............................................. 235 RTCVAL Register Mapping ............................. 236 Safety Window for Register Reads and Writes 235 Write Lock ........................................................ 235 Peripheral Module Disable (PMD) Register ............. 238 Register Interface ..................................................... 233 Register Maps .......................................................... 239 Reset ........................................................................ 238 Device .............................................................. 238 Power-on Reset (POR) .................................... 238 Value Registers (RTCVAL) ...................................... 227 RTCEN Bit Write .............................................................. 233 SUBLW ............................................................................ 443 SUBULNK ........................................................................ 453 SUBWF ............................................................................ 443 SUBWFB ......................................................................... 444 SWAPF ............................................................................ 444 T Table Pointer Operations with TBLRD, TBLWT (table) ... 100 Table Reads/Table Writes ................................................. 75 TAD .................................................................................. 351 TBLRD ............................................................................. 445 TBLWT ............................................................................ 446 Timer0 ............................................................................. 191 Associated Registers ............................................... 193 Operation ................................................................. 192 Overflow Interrupt .................................................... 193 Prescaler ................................................................. 193 Switching Assignment ..................................... 193 Prescaler Assignment (PSA Bit) .............................. 193 Prescaler Select (T0PS2:T0PS0 Bits) ..................... 193 Reads and Writes in 16-Bit Mode ............................ 192 Source Edge Select (T0SE Bit) ............................... 192 Source Select (T0CS Bit) ........................................ 192 Timer1 ............................................................................. 195 16-Bit Read/Write Mode .......................................... 200 Associated Registers ............................................... 206 Clock Source Selection ........................................... 198 Gate ......................................................................... 202 Interrupt ................................................................... 201 Operation ................................................................. 198 Oscillator .......................................................... 195, 200 Layout Considerations ..................................... 201 Resetting, Using the ECCP Special Event Trigger .. 202 TMR1H Register ...................................................... 195 TMR1L Register ...................................................... 195 Use as a Clock Source ............................................ 201 Timer2 ............................................................................. 207 Associated Registers ............................................... 208 Interrupt ................................................................... 208 Operation ................................................................. 207 Output ...................................................................... 208 Timer3 ............................................................................. 209 16-Bit Read/Write Mode .......................................... 213 Associated Registers ............................................... 217 Gate ......................................................................... 213 Operation ................................................................. 212 Oscillator .......................................................... 209, 213 Overflow Interrupt ............................................ 209, 217 Special Event Trigger (ECCP) ................................. 217 TMR3H Register ...................................................... 209 TMR3L Register ...................................................... 209 Timer4 ............................................................................. 219 Associated Registers ............................................... 220 Interrupt ................................................................... 220 MSSP Clock Shift .................................................... 220 Operation ................................................................. 219 Output ...................................................................... 220 Postscaler. See Postscaler, Timer4. PR4 Register ........................................................... 219 Prescaler. See Prescaler, Timer4. TMR4 Register ........................................................ 219 TMR4 to PR4 Match Interrupt .......................... 219, 220 Timing Diagrams A/D Conversion ....................................................... 497 Asynchronous Reception ......................................... 334 Asynchronous Transmission ................................... 332 S SCKx ................................................................................ 266 SDIx ................................................................................. 266 SDOx ............................................................................... 266 SEC_IDLE Mode ................................................................ 46 SEC_RUN Mode ................................................................ 42 Serial Clock, SCKx ........................................................... 266 Serial Data In (SDIx) ........................................................ 266 Serial Data Out (SDOx) ................................................... 266 Serial Peripheral Interface. See SPI Mode. SETF ................................................................................ 441 Shoot-Through Current .................................................... 259 Slave Select (SSx) ........................................................... 266 SLEEP ............................................................................. 442 Software Simulator (MPLAB SIM) .................................... 458 Special Event Trigger. See Compare (ECCP Mode). Special Features of the CPU ........................................... 389 SPI Mode (MSSP) ............................................................ 266 Associated Registers ............................................... 275 Bus Mode Compatibility ........................................... 274 Clock Speed, Interactions ........................................ 274 Effects of a Reset ..................................................... 274 Enabling SPI I/O ...................................................... 270 Master Mode ............................................................ 271 Master/Slave Connection ......................................... 270 Operation ................................................................. 269 Open-Drain Output Option ............................... 269 Operation in Power-Managed Modes ...................... 274 Registers .................................................................. 267 Serial Clock .............................................................. 266 Serial Data In ........................................................... 266 Serial Data Out ........................................................ 266 Slave Mode .............................................................. 272 Slave Select ............................................................. 266 Slave Select Synchronization .................................. 272 SPI Clock ................................................................. 271 SSPxBUF Register .................................................. 271 SSPxSR Register ..................................................... 271 Typical Connection .................................................. 270 SSPOV ............................................................................. 310 SSPOV Status Flag ......................................................... 310 SSPxSTAT Register R/W Bit ............................................................. 290, 293 SSx .................................................................................. 266 Stack Full/Underflow Resets .............................................. 75 SUBFSR .......................................................................... 453 SUBFWB .......................................................................... 442 (c) 2009 Microchip Technology Inc. DS39932C-page 521 PIC18F46J11 FAMILY Asynchronous Transmission (Back-to-Back) ........... 332 Automatic Baud Rate Calculation ............................ 330 Auto-Wake-up Bit (WUE) During Normal Operation 335 Auto-Wake-up Bit (WUE) During Sleep ................... 335 Baud Rate Generator with Clock Arbitration ............ 308 BRG Overflow Sequence ......................................... 330 BRG Reset Due to SDAx Arbitration During Start Condition ................................................................... 316 Bus Collision During a Repeated Start Condition (Case 1) ...................................................................... 317 Bus Collision During a Repeated Start Condition (Case 2) ...................................................................... 317 Bus Collision During a Start Condition (SCLx = 0) ... 316 Bus Collision During a Stop Condition (Case 1) ...... 318 Bus Collision During a Stop Condition (Case 2) ...... 318 Bus Collision During Start Condition (SDAx Only) ... 315 Bus Collision for Transmit and Acknowledge ........... 314 CLKO and I/O .......................................................... 482 Clock Synchronization ............................................. 301 Clock/Instruction Cycle .............................................. 76 Enhanced Capture/Compare/PWM ......................... 485 EUSARTx Synchronous Receive (Master/Slave) .... 496 EUSARTx Synchronous Transmission (Master/Slave) .. 496 Example SPI Master Mode (CKE = 0) ..................... 488 Example SPI Master Mode (CKE = 1) ..................... 489 Example SPI Slave Mode (CKE = 0) ....................... 490 Example SPI Slave Mode (CKE = 1) ....................... 491 External Clock .......................................................... 480 Fail-Safe Clock Monitor ............................................ 404 First Start Bit ............................................................ 308 Full-Bridge PWM Output .......................................... 254 Half-Bridge PWM Output ................................. 252, 259 High/Low-Voltage Detect Characteristics ................ 478 High-Voltage Detect (VDIRMAG = 1) ....................... 371 I22C Bus Data .......................................................... 492 I2C Acknowledge Sequence .................................... 313 I2C Bus Start/Stop Bits ............................................. 492 I2C Master Mode (7 or 10-Bit Transmission) ........... 311 I2C Master Mode (7-Bit Reception) .......................... 312 I2C Slave Mode (10-Bit Reception, SEN = 0, ADMSK = 01001) .............................................................. 297 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 298 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 303 I2C Slave Mode (10-Bit Transmission) ..................... 299 I2C Slave Mode (7-Bit Reception, SEN = 0, ADMSK = 01011) .............................................................. 295 I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 294 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 302 I2C Slave Mode (7-Bit Transmission) ....................... 296 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Addressing Mode) ................................. 304 I2C Stop Condition Receive or Transmit Mode ........ 313 Low-Voltage Detect (VDIRMAG = 0) ....................... 370 MSSPx I2C Bus Data ............................................... 494 MSSPx I2C Bus Start/Stop Bits ................................ 494 Parallel Master Port Read ........................................ 486 Parallel Master Port Write ........................................ 487 Parallel Slave Port Read .................................. 175, 177 Parallel Slave Port Write .................................. 175, 178 PWM Auto-Shutdown with Auto-Restart Enabled .... 258 PWM Auto-Shutdown with Firmware Restart ........... 258 PWM Direction Change ........................................... 255 PWM Direction Change at Near 100% Duty Cycle .. 256 PWM Output ............................................................ 246 PWM Output (Active-High) ...................................... 250 PWM Output (Active-Low) ....................................... 251 Read and Write, 8-Bit Data, Demultiplexed Address 182 Read, 16-Bit Data, Demultiplexed Address ............. 185 Read, 16-Bit Multiplexed Data, Fully Multiplexed 16-Bit Address ........................................................... 186 Read, 16-Bit Multiplexed Data, Partially Multiplexed Address ................................................................ 185 Read, 8-Bit Data, Fully Multiplexed 16-Bit Address . 184 Read, 8-Bit Data, Partially Multiplexed Address ...... 182 Read, 8-Bit Data, Partially Multiplexed Address, Enable Strobe .............................................................. 183 Read, 8-Bit Data, Wait States Enabled, Partially Multiplexed Address ................................................ 182 Repeated Start Condition ........................................ 309 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ............... 483 Send Break Character Sequence ............................ 336 Slave Synchronization ............................................. 272 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................................................ 61 SPI Mode (Master Mode) ......................................... 271 SPI Mode (Slave Mode, CKE = 0) ........................... 273 SPI Mode (Slave Mode, CKE = 1) ........................... 273 Steering Event at Beginning of Instruction (STRSYNC = 1) ..................................................................... 262 Steering Event at End of Instruction (STRSYNC = 0) ... 262 Synchronous Reception (Master Mode, SREN) ...... 339 Synchronous Transmission ..................................... 337 Synchronous Transmission (Through TXEN) .......... 338 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ..................................................... 61 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ..................................................... 61 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise < TPWRT) ............................................ 60 Timer Pulse Generation ........................................... 238 Timer0 and Timer1 External Clock .......................... 484 Timer1 Gate Count Enable Mode ............................ 203 Timer1 Gate Single Pulse Mode .............................. 205 Timer1 Gate Single Pulse/Toggle Combined Mode 206 Timer1 Gate Toggle Mode ....................................... 204 Timer3 Gate Count Enable Mode) ........................... 213 Timer3 Gate Single Pulse Mode .............................. 215 Timer3 Gate Single Pulse/Toggle Combined Mode 216 Timer3 Gate Toggle Mode ....................................... 214 Transition for Entry to Idle Mode ................................ 47 Transition for Entry to SEC_RUN Mode .................... 43 Transition for Entry to Sleep Mode ............................ 45 Transition for Two-Speed Start-up (INTRC to HSPLL) .. 403 Transition for Wake From Idle to Run Mode .............. 47 Transition for Wake From Sleep (HSPLL) ................. 45 Transition From RC_RUN Mode to PRI_RUN Mode . 44 Transition From SEC_RUN Mode to PRI_RUN Mode (HSPLL) ............................................................. 43 Transition to RC_RUN Mode ..................................... 44 Write, 16-Bit Data, Demultiplexed Address ............. 185 Write, 16-Bit Multiplexed Data, Fully Multiplexed 16-Bit Address ........................................................... 186 Write, 16-Bit Multiplexed Data, Partially Multiplexed Address ................................................................ 186 Write, 8-Bit Data, Fully Multiplexed 16-Bit Address . 184 Write, 8-Bit Data, Partially Multiplexed Address ...... 183 DS39932C-page 522 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Write, 8-Bit Data, Partially Multiplexed Address, Enable Strobe .............................................................. 184 Write, 8-Bit Data, Wait States Enabled, Partially Multiplexed Address ................................................ 183 Timing Diagrams and Specifications AC Characteristics Internal RC Accuracy ....................................... 481 CLKO and I/O Requirements ................................... 482 Enhanced Capture/Compare/PWM Requirements .. 485 EUSARTx Synchronous Receive Requirements ..... 496 EUSARTx Synchronous Transmission Requirements ... 496 Example SPI Mode Requirements (Master Mode, CKE = 0) ...................................................................... 488 Example SPI Mode Requirements (Master Mode, CKE = 1) ...................................................................... 489 Example SPI Mode Requirements (Slave Mode, CKE = 0) ...................................................................... 490 Example SPI Slave Mode Requirements (CKE = 1) 491 External Clock Requirements .................................. 481 I2C Bus Data Requirements (Slave Mode) .............. 493 I2C Bus Start/Stop Bits Requirements (Slave Mode) ..... 492 MSSPx I2C Bus Data Requirements ........................ 495 MSSPx I2C Bus Start/Stop Bits Requirements ........ 494 Parallel Master Port Read Requirements ................ 486 Parallel Master Port Write Requirements ................. 487 PLL Clock ................................................................. 481 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements .. 483 Timer0 and Timer1 External Clock Requirements ... 484 TSTFSZ ........................................................................... 447 Two-Speed Start-up ................................................. 389, 403 Two-Word Instructions Example Cases .......................................................... 77 TXSTAx Register BRGH Bit ................................................................. 325 U Ultra Low-Power Wake-up ................................................. 55 V Voltage Reference Specifications .................................... 477 Voltage Regulator (On-Chip) ........................................... 401 Operation in Sleep Mode ......................................... 402 W Watchdog Timer (WDT) ........................................... 389, 399 Associated Registers ............................................... 400 Control Register ....................................................... 399 During Oscillator Failure .......................................... 404 Programming Considerations .................................. 399 WCOL ...................................................... 308, 309, 310, 313 WCOL Status Flag ................................... 308, 309, 310, 313 WWW Address ................................................................. 525 WWW, On-Line Support ...................................................... 9 X XORLW ............................................................................ 447 XORWF ............................................................................ 448 (c) 2009 Microchip Technology Inc. DS39932C-page 523 PIC18F46J11 FAMILY NOTES: DS39932C-page 524 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. (c) 2009 Microchip Technology Inc. DS39932C-page 525 PIC18F46J11 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39932C FAX: (______) _________ - _________ Device: PIC18F46J11 Family Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39932C-page 526 (c) 2009 Microchip Technology Inc. PIC18F46J11 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples: a) b) PIC18F46J11-I/PT 301 = Industrial temp., TQFP package, QTP pattern #301. PIC18F46J11T-I/PT = Tape and reel, Industrial temp., TQFP package. Device(1) PIC18F24J11 PIC18F25J11 PIC18F26J11 PIC18F44J11 PIC18F45J11 PIC18F46J11 PIC18LF24J11 PIC18LF25J11 PIC18LF26J11 PIC18LF44J11 PIC18LF45J11 PIC18LF46J11 I SP SS SO ML PT = -40C to +85C (Industrial) = Skinny PDIP = SSOP = SOIC = QFN = TQFP (Thin Quad Flatpack) Note 1: 2: F = Standard Voltage Range LF = Extended Voltage Range T = In tape and reel Temperature Range Package Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) (c) 2009 Microchip Technology Inc. DS39932C-page 527 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 03/26/09 DS39932C-page 528 (c) 2009 Microchip Technology Inc. |
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